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19-2405; Rev 0; 4/02
10Gbps 16:1 Serializer
General Description
The MAX3952 16:1 serializer is optimized for 10.3Gbps and 9.95Gbps Ethernet applications. A serial clock output is provided for retiming the data at the latch input of the laser driver. Both the high-speed data and clock are CML outputs. The serializer operates from a single +3.3V supply, consuming only 1.15W typical power. The clock multiplier reference clock frequency can be either 1/16 or 1/64 the serial output clock rate. A FIFO aligns the phase between the parallel clock input and the internally synthesized clock. In addition, a 1/16 counterdirectional clock output (LVDS) is provided for use as the clock signal of the XAUI codec IC or framer. The operating temperature range is from -40C to +85C. The MAX3952 is available in a 10mm 10mm 68-pin QFN package. o 16-Bit LVDS Interface o Single +3.3V Supply o 1.15W Power Dissipation o LVDS Source Clock Output o Built-In 27 - 1 PRBS Pattern Generator o Deterministic Jitter: 9ps (max) at 0C to +85C o Operating Temperature Range: -40C to +85C o 68-Pin QFN Package (10mm 10mm)
Features
o Operates at 9.953Gbps and 10.3125Gbps
MAX3952
Applications
10Gbps Ethernet LAN 10Gbps Ethernet WAN
PART MAX3952EGK
Ordering Information
TEMP RANGE -40C to +85C PIN-PACKAGE 68 QFN
Pin Configuration appears at end of data sheet.
Typical Application Circuit
644.53MHz REFCLK INPUT 3.3V 100 0.1F 5V
PDIO+ REFCLK+ REFCLK- CKSET VCC VCC_VCO PDIOPDI15+ MAC PDI15PCLKI+ PCLKIPCLKO+ PCLKOFIFOERR
FIL SDO+ SDO-
MAX3952
MAX3930
SCLKO+ SCLKORESET PRBSEN LOCK GND SCLKEN
TTL THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE (Z0 = 50).
________________________________________________________________ Maxim Integrated Products
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10Gbps 16:1 Serializer MAX3952
ABSOLUTE MAXIMUM RATINGS
Power Supply (VCC)....................................................-0.5 to +5V CML Output Current (SDO, SCLKO)..............................22mA LVDS Input Voltage Levels (PDI_, PCLKI).....................................-0.5V to (VCC + 0.5V) LVDS Output Voltage (PCLKO)................-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = +85C) QFN (derate 30.3mW/C above 70C) .......................2424mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +160C Voltage Levels at FIL, RESET, CKSET........-0.5V to (VCC + 0.5V) Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3V to +3.6V, TA = -40C to +85C. Typical values are at VCC = +3.3V, differential LVDS load = 100, TA = +25C, unless otherwise noted.)
PARAMETER Supply Current Input Voltage Range Differential Input Voltage Input Common-Mode Current Threshold Hysteresis Differential Input Impedance Output High Voltage Output Low Voltage Differential Output Voltage Change in Magnitude of Differential Outputs for Complementary Inputs Offset Output Voltage Change in Magnitude of Output Offset Voltage for Complementary States Differential Output Impedance Output Current Short together Short to ground |VOS| 80 RIN VOH VOL |VOD| |VOD| 1.125 0.925 250 400 25 1.275 25 140 12 40 85 LVDS OUTPUT SPECIFICATIONS (PCLKO) 1.475 V V mV mV V mV mA SYMBOL ICC VI |VID| Input, VOS = 1.2V (Note 1) 0 100 100 70 100 115 CONDITIONS MIN TYP 350 MAX 500 2400 UNITS mA mV mV A mV
LVDS INPUT SPECIFICATIONS (PDI[15...0], PCLKI)
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10Gbps 16:1 Serializer
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3V to +3.6V, TA = -40C to +85C. Typical values are at VCC = +3.3V, differential LVDS load = 100, TA = +25C, unless otherwise noted.)
PARAMETER Differential Output Differential Output Impedance Output Common-Mode Voltage RL = 50 to VCC SYMBOL CONDITIONS RL = 50 to VCC MIN 640 85 TYP 800 100 VCC 0.2 2.0 0.8 -28 -50 IOH = 20A IOL = 1mA VCC 1.16 VCC 1.81 VCC 1.3 1.4 300 1900 2.4 10 10 VCC 0.4 VCC 0.88 VCC 1.48 MAX 1000 115 UNITS mVP-P V
MAX3952
CML OUTPUT SPECIFICATIONS (SDO, SCLKO)
LVTTL SPECIFICATIONS (RESET, FIFO_ERROR, LOCK, PRBSEN) LVTTL Input High Voltage LVTTL Input Low Voltage LVTTL Input High Current LVTTL Input Low Current LVTTL Output High Voltage LVTTL Output Low Voltage VIH VIL IIH IIL VOH VOL V V A A V V
LVPECL INPUT SPECIFICATIONS (REFCLK) LVPECL Input High Voltage LVPECL Input Low Voltage LVPECL Input Bias Voltage LVPECL Single-Ended Impedance LVPECL Differential Input Voltage Swing VIH VIL V V V k mVP-P
Note 1: CML outputs AC-coupled to 100 differential load, PRBSEN = GND, and SCLKEN = GND.
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10Gbps 16:1 Serializer MAX3952
AC ELECTRICAL CHARACTERISTICS
(VCC = +3V to +3.6V, TA = -40C to +85C. Typical values are at VCC = +3.3V, differential LVDS and CML load = 100, TA = +25C, unless otherwise noted.) (Note 2)
PARAMETER Parallel Input Setup Time Parallel Input Hold Time Parallel Clock Output Rise/Fall Time Parallel Clock Output Duty Cycle SERIAL DATA OUTPUT SPECIFICATIONS (SDO, SCLKO) Bit-Error Rate Serial Data Output Rise/Fall Time Serial Output Clock-to-Data Delay Serial Data or Clock Output Random Jitter Serial Data Output Deterministic Jitter Serial Clock or Data Output Return Loss tr, tf tCK-Q tRJ tDJ 0C to +85C (Note 4) -40C to +85C (Note 4) 17 10 7 dB 20% to 80% (Note 3) -15 1 10
-12
SYMBOL tSU tH (Figure 1) (Figure 1)
CONDITIONS
MIN
TYP
MAX 200 200
UNITS ps ps
Tx DATA INPUT SPECIFICATIONS (PDI[15...0], PCLKI)
Tx SOURCE CLOCK OUTPUT SPECIFICATIONS (PCLKO) tr, tf 20% to 80% 45 100 250 55 ps %
28 +15 0.9 9 15
ps ps psRMS psP-P
100kHz to 10GHz RL = 10GHz to 13GHz -20log|S22| 13GHz to 15GHz
Tx REFERENCE CLOCK INPUT SPECIFICATIONS (REFCLK) Reference Clock Frequency Tolerance Reference Clock Input Duty Cycle RESET INPUT (RESET) Minimum Pulse Width of FIFO Reset Tolerated Drift Between PCLKI and PCLKO After Reset UI is PCLKO period UI is PCLKO period; drift is PCLKO crossing PCLKI crossing -1 4 +1 UI UI -100 30 +100 70 ppm %
Note 2: See Table 1 for valid operating clock frequencies. AC characteristics are guaranteed by design and characterization. Note 3: Relative to the falling edge of the SCLKO. Note 4: Deterministic jitter includes pattern-dependent jitter and pulse-width distortion. Measured with a pattern equivalent to 223 - 1 PRBS.
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10Gbps 16:1 Serializer
Typical Operating Characteristics
(TA = +25C, VCC = +3.3V, unless otherwise noted.)
RCLKI TO SCLKO JITTER TRANSFER
MAX3952 toc01
MAX3952
SERIAL CLOCK OUTPUT RANDOM JITTER
MAX3952 toc02
5 0 JITTER TRANSFER (dB) -5 -10 -15 -20 -25 10 100 1k
10k
fREFCLK = 155.52MHz, RANDOM JITTER = 513fsRMS
JITTER FREQUENCY (Hz)
SERIAL CLOCK AND DATA OUTPUTS
MAX3952 toc03
SUPPLY CURRENT vs. TEMPERATURE
430 SUPPLY CURRENT (mA) 410 390 370 350 330
MAX3952 toc04
450
SCLKO
SDO 310 290 20ps/div -40 10 60 110 TEMPERATURE (C)
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10Gbps 16:1 Serializer MAX3952
Pin Description
PIN 1, 4, 5, 13, 17, 18, 26, 34, 35, 51, 52, 68 2 3 6, 9, 12, 25, 43, 60 7 8 10 11 14 15 16 19, 21, 23, 27, 29, 31, 36, 38, 40, 44, 46, 48, 54, 56, 58, 61 20, 22, 24, 28, 30, 32, 37, 39, 41, 45, 47, 49, 55, 57, 59, 62 33 42 50 53 63 64 65 66 67 NAME FUNCTION
GND
Ground
REFCLK+ REFCLKVCC SCLKOSCLKO+ SDOSDO+ SCLKEN PCLKO+ PCLKO-
Positive Reference Clock Input, LVPECL Negative Reference Clock Input, LVPECL Positive Power Supply Negative Serial Clock Output, CML. 9.95328GHz or 10.3125GHz Positive Serial Clock Output, CML. 9.95328GHz or 10.3125GHz Negative Serial Data Output, CML. 9.95328Gbps or 10.3125Gbps Positive Serial Data Output, CML. 9.95328Gbps or 10.3125Gbps Control Input for Disabling SCLKO Output: SCLKEN = GND SCLKO Off SCLKEN = VCC SCLKO Active Positive Source Clock Output. LVDS, 622MHz or 644MHz. Clocks the MAC. Negative Source Clock Output. LVDS, 622MHz or 644MHz. Clocks the MAC.
PDI15+ to PDI0+
Positive Parallel Data Inputs, LVDS. PDI15+ is MSB
PDI15- to PDI0-
Negative Parallel Data Inputs, LVDS. PDI15- is MSB
RESET PRBSEN FIFO_ERROR LOCK PCLKI+ PCLKICKSET FIL VCC_VCO
16 x 4-Bit FIFO Reset Input, TTL, Active High PRBS Pattern Generator Enable Input, TTL, Active High FIFO Error, TTL, Active High PLL Lock Indicator, TTL, Active High Positive Parallel Clock Input, LVDS Negative Parallel Clock Input, LVDS Reference Clock Programming Pin. Programming instructions in Table 1. Filter Capacitor Input Pin Loop Filter and VCO Positive Power Supply
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10Gbps 16:1 Serializer
Detailed Description
The MAX3952 converts 16-bit-wide, 622Mbps/644Mbps data to 9.95Gbps/10.3Gbps serial data (Figures 3 and 4). Data is loaded into the 16:1 mux through a 16 x 4 FIFO buffer for wide tolerance to clock skew. Clock and data inputs are LVDS levels, and high-speed serial outputs are current-mode logic (CML). An internal PLL frequency synthesizer generates a serial clock from a low-speed reference clock. this condition, assert RESET high for at least 4UI. FIFO_ERROR can be connected directly to the RESET input to clear timing errors. After reset, the full elastic range of the FIFO is available again.
MAX3952
Frequency Synthesizer
The PLL synthesizes a 9.95GHz/10.31GHz clock from an external reference clock. The PLL reference clock (REFCLK) can be programmed as 622MHz/644MHz or 155MHz/161MHz using the CKSET pin. See Table 1 for CKSET settings. The parallel output clock (PCLKO) is derived from the synthesizer and is SCLKO / 16. A TTL-compatible loss-of-lock indicator (LOCK), asserts low when the VCO is unable to lock to the reference frequency. This pin can be used to directly drive an LED. If jitter on the REFCLK input is present, an error with respect to the divided down SCLKO frequency of 500ppm will be indicated by a low state on LOCK.
Low-Voltage Differential-Signal Inputs and Outputs
The MAX3952 has LVDS inputs for interfacing with high-speed digital circuitry. This technology uses 250mV to 400mV differential low-voltage swings to achieve fast transition times, minimal power dissipation, and noise immunity. For proper operation, the parallel clock LVDS outputs (PCLKO) require 100 differential DC terminations between the positive and negative outputs. Do not terminate these outputs to ground. The parallel data and parallel clock LVDS inputs (PDI_+, PDI_-, PCLKI+, PCLKI-) are internally terminated with a 100 differential input resistance and therefore do not require external termination.
Table 1. Setting REFCLK Frequency
REFERENCE CLOCK FREQUENCY (MHz) 622.08 644.53 155.52 161.13 CKSET PIN SETTING OPEN VCC GND 30k to GND SERIAL CLOCK FREQUENCY (GHz) 9.95 10.3 9.95 10.3
LVPECL Inputs
The reference clock (REFCLK) has LVPECL inputs for interfacing to a crystal oscillator using AC- or DC-coupling. The REFCLK inputs are self-biasing to VCC - 1.3V for AC-coupled inputs. Only a 100 differential termination resistance must be added when inputs are AC-coupled.
Internal Pattern Generator
The MAX3952 includes a SONET-compliant internal pattern generator capable of a 2 7 - 1 PRBS pattern. Connecting the PRBSEN pin to VCC enables the pattern generator.
Current-Mode Logic Outputs
The high-speed data and clock outputs (SDO, SCLKO) of the MAX3952 are designed using CML. The CML outputs include internal 50 back termination to V CC. These outputs are intended to drive a 50 transmission line terminated with a matched load impedance. For detailed instructions on how to interface with LVDS, PECL, and CML, refer to HFAN-01.0: Introduction to LVDS, PECL, and CML.
Layout Techniques
For best performance, use good high-frequency layout techniques. Filter voltage supplies and keep ground connections short. Use multiple vias where possible. Use controlled impedance transmission lines to interface with the MAX3952 clock and data inputs and outputs. Give special consideration to filtering the VCC_VCO pin; all other power supplies can be connected through a common filter.
FIFO Buffer
Data is latched into the MAX3952 by the parallel input clock (PCLKI). The parallel input clock is the FIFO write clock. The parallel output clock (PCLKO) is the FIFO read clock that loads the 16:1 mux. The FIFO allows the read and write clock to vary by up to 1UI (unit interval). This specification makes the MAX3952 noncompliant with the IEEE802.3ae standard, as this standard requires a tolerance of 14UI. Conditions that result in the read and write clock accessing the same FIFO address are indicated by FIFO_ERROR. To clear
Exposed Pad (EP) Package
The EP 68-pin QFN incorporates features that provide a very low thermal resistance path for heat removal from the IC to a PC board. The MAX3952's exposed paddle must be soldered directly to a ground plane with good thermal conductance. Refer to HFAN-08.1: Thermal Considerations of QFN and Other Exposed-Paddle Packages.
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10Gbps 16:1 Serializer MAX3952
Chip Information
TRANSISTOR COUNT:8400 PROCESS: SiGe bipolar
1.608ns 622MHz CLOCK (PCLKI)
100.47ps
9.953GHz CLOCK (SCLKO)
622Mbps DATA (PDI)
9.953Gbps DATA (SDO)
tSU
tH
tCLK-Q
Figure 1. Setup and Hold Time
Figure 2. Definition of Clock to Q
RESET FIFO-ERROR
PCLKI+ LVDS PCLKISDO+ PDI+[15...0] LVDS PDI-[15...0] 16 16 0 16 1 DATA READ 16-BIT REG 16 16 x 4-BIT FIFO 16 16:1 MUX CML SDOCLK WRITE
PRBSEN SIS PCLKO+
PRBS GENERATOR
MAX3952
SCLKO+ LVDS CML SCLKO-
PCLKOREFCLK+ LVPECL REFCLKFREQUENCY GENERATOR
CKSET
FIL
VCC_VCO
LOCK
SCLKEN
Figure 3. Functional Diagram 8 _______________________________________________________________________________________
10Gbps 16:1 Serializer MAX3952
PCLKO
PCLKI tSU PARALLEL INPUT DATA (PDI_) SERIAL OUTPUT DATA (SDO) *D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, PCLKO = (PCLKO+) - (PCLKO-). *PDI15 = D15; PDI14 = D14 ... PDIO = DO. THIS FIGURE IS NOT INTENDED TO SHOW A SPECIFIC TIMING RELATIONSHIP BETWEEN PARALLEL INPUT DATA AND SERIAL OUTPUT DATA. VALID PARALLEL DATA* tH
Figure 4. Parallel and Serial Data Timing
Pin Configuration
VCC_VCO PCLKI+ PCLKI-
TOP VIEW
GND
CKSET
PDIO+
PDIO-
PDI1+
PDI2+
PDI3+
LOCK
PDI1-
PDI2-
PDI3-
68
67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45
GND REFCLK+ REFCLKGND GND VCC SCLKOSCLKO+ VCC SDOSDO+ VCC GND SCLKEN PCLKO+ PCLKOGND
GND
VCC
FIL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
GND FIFO_ERROR PDI4PDI4+ PDI5PDI5+ PDI6PDI6+ VCC PRBSEN PDI7PDI7+ PDI8PDI8+ PDI9PDI9+ GND
MAX3951
44 43 42 41 40 39 38 37 36 35
PDI15+
PDI14+
PDI15-
PDI13+
PDI14-
PDI13-
PDI12+
PDI12-
PDI11+
PDI11-
PDI10+
PDI10-
RESET
GND
VCC
GND
*EXPOSED PAD IS CONNECTED TO GND.
QFN*
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GND
9
10Gbps 16:1 Serializer MAX3952
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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