View Z8530_258900.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Z85233 CPS DC-4058-03
CUSTOMER PROCUREMENT SPECIFICATION
Z85233
EMSCCTM ENHANCED MONO SERIAL COMMUNICATION CONTROLLER
GENERAL DESCRIPTION
The Zilog Enhanced Mono Serial Communication Controller, Z85233 EMSCC, is a software compatible CMOS member of the SCC family introduced by Zilog in 1981. The EMSCC is a full-duplex data communications controller capable of supporting a wide range of popular protocols. The Z85233 EMSCC is a single channel version (Channel A) of Zilog's Z85230 ESCC. Based on ZIlog's unique SuperintegrationTM Technology, the EMSCC is compatible with designs using Zilog's SCC and ESCC to receive and transmit data. It has many improvements that significantly reduce CPU overhead. The addition of a 4-byte transmit FIFO and an 8-byte receive FIFO significantly reduces the overhead required to provide data to, and get data from, the transmitter and receiver. The EMSCC also has many features that improve packet handling in SDLC mode. The EMSCC will automatically: transmit a flag before the data, reset the Tx Underrun/EOM latch, force the TxD pin high at the appropriate time when using NRZI encoding, deassert the /RTS pin after the closing flag, and better handle ABORTed frames when using the 10x19 status FIFO. The combination of these features along with the deeper data FIFOs significantly simplifies SDLC driver software. The CPU hardware interface has been simplified by relieving the databus setup time requirement and supporting the software generation of the interrupt acknowledge signal (/INTACK). These changes allow an interface with less external logic to many microprocessor families while maintaining compatibility with existing designs. I/O handling of the EMSCC is improved over the SCC with faster response of the /INT and /DTR//REQ pins. The many enhancements added to the EMSCC permits a system design that increases overall system performance with better data handling and less interface logic.
Notes: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD
VSS
DC 4058-03
(11-4-94)
1
Z85233 CPS DC-4058-03
PIN DESCRIPTIONS
/INT D7 D5 D3 D1 D0 D2 D4 D6 /RD /WR
33 32 31 30 29 28 27 26 25 24 23 IEO IEI /INTACK VCC /W//REQA /SYNCA /RTxCA RxDA /TRxCA TxDA GND 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 Z85233 (Top View) 22 21 20 19 18 17 16 15 14 13 12 NC /CE D//C NC GND NC NC NC NC NC NC
/DTR/REQA
/RTSA
/CTSA
/DCDA
PCLK
GND
NC
NC
NC
Z85233 PQFP Pin Assignments
2
NC
NC
Z85233 CPS DC-4058-03
/INT D7 /WR /RD D5 D3 D1 D0 D2 D4 D6
6 IEO IEI /INTACK VCC /W//REQA /SYNCA /RTxCA RxDA /TRxCA TxDA GND 7 8 9 10 11 12 13 14 15 16 17
5
4
3
2
1
44 43 42 41 40 39 38 37 36 35 NC /CE D//C NC GND NC NC NC NC NC NC
Z85233 (Top View)
34 33 32 31 30 29
18 19 20 21 22 23 24 25 26 27 28
/RTSA
/CTSA
PCLK
GND
NC
NC
NC
NC
/DTR//REQA
Z85233 PLCC Pin Assignments
/DCDA
NC
3
Z85233 CPS DC-4058-03
ABSOLUTE MAXIMUM RATINGS
VCC Supply Voltage range ......................... -0.3V to +7.0V Voltages on all pins with respect to GND .......................... -0.3V to VCC +0.3V Operating Ambient Temperature ............................ See Ordering Information Storage Temperature ............................ -65C to +150C Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
STANDARD TEST CONDITIONS
The DC Characteristics and capacitance sections below apply for the following standard test conditions, unless otherwise noted. All voltages are referenced to GND. Positive current flows into the referenced pin. Standard conditions are as follows:
s s s
+4.50 V VCC + 5.50 V GND = 0 V TA as specified in Ordering Information +5V
+5V 2.1 k From Output Under Test 100 pF 250 A
2.2 k From Output 50 pF
Standard Test Load
Open-Drain Test Load
CAPACITANCE
Symbol CIN COUT CI/O Parameter Input Capacitance Output Capacitance Bidirectional Capacitance Min Max 10 15 20 Unit pF pF pF Test Condition Unmeasured pins returned to ground.
Note: f = 1 MHz, over specified temperature range.
MISCELLANEOUS
Gate Count - 7000
4
Z85233 CPS DC-4058-03
DC CHARACTERISTICS Z85233
Symbol VIH VIL VOH1 VOH2 VOL IIL IOL ICC1 ICC(OSC) Parameter Input High Voltage Input Low Voltage Output High Voltage Output High Voltage Output Low Voltage Input Leakage Output Leakage VCC Supply Current Crystal OSC Current Min 2.2 -0.3 2.4 VCC-0.8 Typ Max VCC+0.3 0.8 Unit V V V V V A A mA mA mA Condition
0.4 10.0 10.0 8 (10 MHz) 10 (16 MHz)
IOH = -1.6 mA IOH = -250 A IOL= + 2.0 mA 0.4< VIN<+2.4V 0.4< VOUT <+2.4V VCC=5V VIH=4.8 VIL=0.2V Crystal Oscillators off Current for each osc. in addition to ICC1
4 5 6
Notes: [1] VCC = 5V 10% unless otherwise specified, over specified temperature range. [2] Typical ICC was measured with oscillator off. [3] No ICC(osc) max is specified due to dependency on the external circuit.
5
Z85233 CPS DC-4058-03
AC CHARACTERISTICS Z85233 Read and Write Timing Diagram
1
PCLK
2 6 5 3 4
A//B, D//C
7 8 9 10
/INTACK
11 10 13 14 12 15
/CE
16 18
/RD
19 22 20 21
D7-D0 Read
23
Active
Valid
24
25 27
26
17
/WR
28
D7-D0 Write
31 29 30
/W//REQ Wait
32 35
/W//REQ Request /DTR//REQ Request
33 34 36
/INT
37
Read and Write Timing Diagram
/WR
46 47 48
/RD
Reset Timing Diagram
6
Z85233 CPS DC-4058-03
PCLK
10 15
/INTACK
10 38 14
/RD
39 23 24
D7-D0
Active
40 41
Valid
26 42
IEI
43 44
IEO
45
/INT
Interrupt Acknowledge Timing Diagram
/CE
49
/RD or /WR
Cycle Timing Diagram
AC CHARACTERISTICS Z85233 Read and Write Timing Table
No 1 2 3 4 5 6 7 8 9 10 Symbol TwPCl TwPCh TfPC TrPC TcPC TsA(WR) ThA(WR) TsA(RD) ThA(RD) TsIA(PC) Parameter PCLK Low Width PCLK High Width PCLK Fall Time PCLK Rise Time PCLK Cycle Time Address to /WR Fall Setup Time Address to /WR Rise Hold Time Address to /RD Fall Setup Time Address to /RD Rise Hold Time /INTACK to PCLK Rise Setup Time 10 MHz Min Max 40 40 1000 1000 10 10 2000 16 MHz Min Max 26 26 1000 1000 5 5 2000 Notes
100 50 0 50 0 20
61 35 0 35 0 15
7
Z85233 CPS DC-4058-03
AC CHARACTERISTICS Z85233 Read and Write Timing Table
No 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35a 35b 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Symbol TsIAi(WR) ThIA(WR) TsIAi(RD) ThIA(RD) ThIA(PC) TsCEI(WR) ThCE(WR) TsCEh(WR) TsCEI(RD) ThCE(RD) TsCEh(RD) TwRDI TdRD(DRA) TdRDr(DR) TdRDI(DR) TdRD(DRz) TdA(DR) TwWRI TdWR(DW) ThDW(WR) TdWR(W) TdRD(W) TdWRf(REQ) TdRDf(REQ) TdWRr(REQ) TdWRr(REQ) TdRDr(REQ) TdPC(INT) TdIAi(RD) TwRDA TdRDA(DR) TsIEI(RDA) ThIEI(RDA) TdIEI(IEO) TdPC(IEO) TdRDA(INT) TdRD(WRQ) TdWRQ(RD) TwRES Trc Parameter /INTACK to /WR Fall Setup Time /INTACK to /WR Rise Hold Time /INTACK to /RD Fall Setup Time /INTACK to /RD Rise Hold Time /INTACK to PCLK Rise Hold Time /CE Low to /WR Fall Setup Time /CE to /WR Rise Hold Time /CE High to /WR Fall Setup Time /CE Low to /RD Fall Setup Time /CE to /RD Rise Hold Time /CE High to /RD Fall Setup Time /RD Low Width /RD Fall to Read Data Active Delay /RD Rise to Data Not Valid Delay /RD Fall to Read Data Valid Delay /RD Rise to Read Data Float Delay Addr to Read Data Valid Delay /WR Low Width /WR Fall to Write Data Valid Delay Write Data to /WR Rise Hold Time /WR Fall to Wait Valid Delay /RD Fall to Wait Valid Delay /WR Fall to /W//REQ Not Valid Delay /RD Fall to /W//REQ Not Valid Delay /WR Fall to /DTR//REQ Not Valid /WR Fall to /DTR//REQ Not Valid /RD Rise to /DTR//REQ Not Valid Delay PCLK Fall to /INT Valid Delay /INTACK to /RD Fall (Ack) Delay /RD (Acknowledge) Width /RD Fall(Ack) to Read Data Valid Delay IEI to /RD Fall (Ack) Setup Time IEI to /RD Rise (Ack) Hold Time IEI to IEO Delay Time PCLK Rise to IEO Delay /RD Fall to /INT Inactive Delay /RD Rise to /WR Fall Delay for No Reset /WR Rise to /RD Fall Delay for No Reset /WR and /RD Low for Reset Valid Access Recovery Time 10 MHz 16 MHz Min Max Min Max 130 0 130 0 30 0 0 50 0 0 50 125 0 0 120 35 180 125 20 0 100 100 120 120 4TcPc 100 NA 320 90 125 120 95 0 90 175 320 15 15 100 4TcPc 10 10 75 4TcPc 50 75 70 50 0 45 80 200 [4] 0 50 50 70 70 4TcPc 70 NA 175 [4] [4] [6] [6] 75 20 70 0 70 0 15 0 0 30 0 0 30 2TcPC 70 0 0 70 30 100 Notes [1] [1]
2TcPC
[1] [1] [1] [1]
[5]
[3]
Notes: [1] Parameter does not apply to Interrupt Acknowledge transactions. [3] Parameter applies only between transactions involving the EMSCC. [4] Open-drain output, measured with open-drain test load. [5] Parameter is system dependent. For any EMSCC in the daisy chain, TdIAi(RD) must be greater than the sum of TdPC(IEO) for the highest priority device in the daisy chain. TsIEI(RDA) for the EMSCC and TdIEI(IEO) for each device separating them in the daisy chain. [6] Parameter applies to enhanced Request mode only (WR7' D4=1)
8
Z85233 CPS DC-4058-03
AC CHARACTERISTICS Z85233 General Timing Diagram
PCLK
1
/W//REQ, /DTR//REQ Request
2
/W//REQ Wait
3
/RTxC, /TRxC Receive
4 5 6 7
RxD
8 9
/SYNC External
10
/TRxC, /RTxC T ransmit
11 12
TxD
13
/TRxC Output
14 15
/RTxC
16 17
/TRxC
18 20 19
/CTS, /DCD
21 21
/SYNC Input
22 22
General Timing Diagram
9
Z85233 CPS DC-4058-03
AC CHARACTERISTICS Z85233 General Timing Table (Preliminary)
10 MHz Min Max 200 200 300 NA 16 MHz Min Max 80 80 180 NA
No 1a 1b 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16a 16b 17 18 19 20 21 22
Symbol TdPC(REQ) TdPC(REQ) TdPC(W) TsRXC(PC) TsRXD(RXCr) ThRXD(RxCr) TsRXD(RXCf) ThRXD(RXCf) TsSY(RXC) ThSY(RXC) TsTXC(PC) TdTXCf(TXD) TdTxCr(TXD) TdTXD(TRX) TwRTXh TwRTXI TcRTX TxRX(DPLL) TcRTXX TwTRXh TwTRXl TcTRX TwEXT TwSY
Parameter /PCLK to W/REQ Valid /PCLK to DTR/ REQ Valid /PCLK to Wait Inactive /RxC to /PCLK Setup Time RxD to /RxC Setup Time RxD to /RXC Hold Time RxD to /RXC Setup Time RXD to /RXC Hold Time /SYNC to /RxC Setup Time /SYNC to/RXC Hold Time /TxC to /PCLK Setup Time /TxC to TxD Delay /TxC to TxD Delay TxD to TRxC Delay RTxC High Width TRxC Low Width RTxC Cycle Time DPLL Cycle Time Min Crystal Osc. Period TRxC High Width TRxC Low Width TRxC Cycle Time DCD or CTS Pulse Width SYNC Pulse Width
Notes [9] [1,4] [1] [1] [1,5] [1,5] [1] [1] [2,4] [2] [2,5] [6] [6] [6,7]
NA 0 125 0 125 -150 5TcPc NA
NA 0 50 0 50 -100 5TcPc NA
150 150 140 120 120 400 50 100 120 120 400 120 120 1000 80 80 244 31 61 80 80 244 70 70
80 80 80
1000
[7,8] [3] [6] [6] [6,7]
Notes: [1] RxC is /RTxC or /TRxC, whichever is supplying the receive clock. [2] TxC is /TRxC or /RTxC, whichever is supplying the transmit clock. [3] Both /RTxC and /SYNC have 30 pF capacitors to ground connected to them. [4] Synchronization of RxC to PCLK is eliminated in divide by four operation. [5] Parameter applies only to FM encoding/decoding. [6] Parameter applies only for transmitter and receiver; DPLL and baud rate generator timing requirements are identical to case PCLK requirements. [7] The maximum receive or transmit data rate is 1/4 PCLK. [8] Applies to DPLL clock source only. Maximum data rate of 1/4 PCLK still applies. DPLL clock should have a 50% duty cycle. [9] Parameter applies only when WR7' D4 is set to '1'.
10
Z85233 CPS DC-4058-03
AC CHARACTERISTICS Z85233 System Timing Diagram (Preliminary)
/RTxC, /TRxC Receive
/W/REQ Request
1
/W/REQ Wait
2
/SYNC Output
3
/INT
4
/RTxC, /TRxC Transmit
/W//REQ Request
5
/W//REQ Wait
6
/DTR//REQ Request
7
/INT
8
/CTS, /DCD
/SYNC Input
9
/INT
10
System Timing
11
Z85233 CPS DC-4058-03
AC CHARACTERISTICS Z85233 System Timing Table (Preliminary)
10 MHz Min Max 13 13 4 15 11 8 9 5 2 3 17 17 7 21 14 14 12 9 7 8 16 MHz Min Max 13 13 4 15 11 8 9 5 2 3 17 17 7 21 14 14 12 9 7 8
No 1 2 3 4 5 6 7 8 9 10
Symbol TdRXC(REQ) TdRXC(W) TdRXC(SY) TdRXC(INT) TdTXC(REQ) TdTXC(W) TdTXC(DRQ) TdTXC(INT) TdSY(INT) TdEXT(INT)
Parameter /RXC to /W//REQ Valid /RxC to /Wait Inactive /RxC to /SYNC Valid /RxC to /INT Valid /TxC to /W//REQ Valid /TxC to /Wait Inactive /TxC to /DTR//REQ Valid /TxC to /INT Valid /SYNC to /INT Valid /DCD or /CTS to /INT Valid
Notes [4] [2] [1,2] [2] [1,2] [3] [1,3] [3] [1,3] [1] [1]
Notes: [1] Open-drain output, measured with open-drain test load. [2] /RxC is /RTxC or /TRxC, whichever is supplying the receive clock. [3] /TxC is /TRxC or /RTxC, whichever is supplying the transmit clock. [4] Units equal to TcPc
12

▲Up To Search▲

Price & Availability of Z8530

	To Download Z8530 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .