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 PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
PM7326 S/UNI TM
APEX
S/UNI APEX
ATM/PACKET TRAFFIC MANAGER AND SWITCH
DATA SHEET
ISSUE 6: APRIL 2000
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
This Material Copyrighted By Its Respective Manufacturer
PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
REVISION HISTORY
Issue No. Issue 6
Issue Date April, 2000
Details of Change Final update for production release. Changes from Issue 5 marked with change bars
Issue 5
December, 1999
Removed Applications Examples and Operations sections, replaced with dedicated documents. IDDOP (operating current) value inserted. Datasheet re-written to incorporate extensive updates and clarifications. No material change from Issue 2, formatted for web site. Updates and clarifications throughout Document created.
Issue 4 Issue 3 Issue 2 Issue 1
August, 1999 June, 1999 February, 1999 November, 1998
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
CONTENTS
1 2 3 4 5 6 7 8 9
DEFINITIONS .......................................................................................... 1 FEATURES .............................................................................................. 3 APPLICATIONS ....................................................................................... 7 REFERENCES......................................................................................... 8 APPLICATION EXAMPLES ..................................................................... 9 BLOCK DIAGRAM ................................................................................. 10 DESCRIPTION ...................................................................................... 12 PIN DIAGRAM ....................................................................................... 16 PIN DESCRIPTION................................................................................ 17 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 LOOP ANY-PHY RECEIVE MASTER/TRANSMIT SLAVE INTERFACE (28 SIGNALS) ........................................................ 17 LOOP ANY-PHY TRANSMIT MASTER/RECEIVE SLAVE INTERFACE (34 SIGNALS) ........................................................ 22 WAN ANY-PHY RECEIVE MASTER/TRANSMIT SLAVE INTERFACE (25 SIGNALS) ........................................................ 26 WAN ANY-PHY TRANSMIT MASTER/RECEIVE SLAVE INTERFACE (25 SIGNALS) ........................................................ 31 CONTEXT MEMORY SYNCHRONOUS SSRAM INTERFACE (60 SIGNALS).................................................................................... 36 CELL BUFFER SDRAM INTERFACE (52 SIGNALS) ................. 38 MICROPROCESSOR INTERFACE (44 SIGNALS)..................... 40 GENERAL (9 SIGNALS) ............................................................. 44 JTAG & SCAN INTERFACE (7 SIGNALS) .................................. 45 POWER....................................................................................... 46
10
FUNCTIONAL DESCRIPTION............................................................... 48
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DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
10.1
ANY-PHY INTERFACES ............................................................. 48 10.1.1 RECEIVE INTERFACE..................................................... 48 10.1.2 TRANSMIT INTERFACE .................................................. 50
10.2 10.3 10.4 10.5 10.6 10.7 10.8
LOOP PORT SCHEDULER ........................................................ 53 WAN PORT SCHEDULER .......................................................... 54 WAN PORT ALIASING................................................................ 56 WAN AND LOOP ICI SELECTION.............................................. 57 MICROPROCESSOR INTERFACE ............................................ 57 MEMORY PORT ......................................................................... 61 SAR ASSIST ............................................................................... 62 10.8.1 TRANSMIT ....................................................................... 62 10.8.2 RECEIVE.......................................................................... 63
10.9
QUEUE ENGINE......................................................................... 64 10.9.1 SERVICE ARBITRATION ................................................. 65 10.9.2 CELL QUEUING ............................................................... 66 10.9.3 CLASS SCHEDULING ..................................................... 73 10.9.4 CONGESTION CONTROL ............................................... 75 10.9.5 STATISTICS ..................................................................... 82 10.9.6 MICROPROCESSOR QUEUE BUFFER REALLOCATION/TEAR DOWN ............................................ 84
10.10 CONTEXT MEMORY SSRAM INTERFACE ............................... 84 10.11 CELL BUFFER SDRAM INTERFACE ......................................... 89 10.12 JTAG TEST ACCESS PORT....................................................... 93 11 PERFORMANCE ................................................................................... 94 11.1 THROUGHPUT ........................................................................... 94
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
11.2 11.3 12
LATENCY .................................................................................... 96 CDV............................................................................................. 96
REGISTER............................................................................................. 97 12.1 12.2 12.3 12.4 12.5 GENERAL CONFIGURATION AND STATUS.............................. 98 LOOP CELL INTERFACE ......................................................... 107 WAN CELL INTERFACE............................................................113 MEMORY PORT ........................................................................119 SAR........................................................................................... 125 12.5.1 RECEIVE........................................................................ 125 12.5.2 TRANSMIT ..................................................................... 127 12.5.3 CELL BUFFER DIAGNOSTIC ACCESS......................... 128 12.6 12.7 12.8 12.9 QUEUE ENGINE....................................................................... 129 MEMORY INTERFACE ............................................................. 144 TEST INTERFACE .................................................................... 145 CBI INTERFACE ....................................................................... 149
13 14
CBI REGISTER PORT MAPPING ....................................................... 151 MEMORY PORT MAPPING................................................................. 157 14.1 14.2 CONTEXT SIZE AND LOCATION............................................. 157 QUEUE CONTEXT DEFINITION .............................................. 160 14.2.1 VC CONTEXT RECORDS.............................................. 161 14.2.2 PORT CONTEXT RECORDS......................................... 169 14.2.3 CLASS CONTEXT RECORDS....................................... 173 14.2.4 SHAPING CONTEXT RECORDS................................... 178 14.2.5 CELL CONTEXT RECORD ............................................ 180
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DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
14.2.6 MISC CONTEXT ............................................................ 180 14.3 WAN PORT SCHEDULER CONTEXT ...................................... 184 14.3.1 WAN TRANSMIT PORT POLLING WEIGHT RECORD. 184 14.3.2 WAN TRANSMIT CLASS STATUS RECORD ................ 185 14.4 LOOP PORT SCHEDULER CONTEXT .................................... 186 14.4.1 LOOP TRANSMIT PORT POLLING SEQUENCE RECORD ........................................................................................ 186 14.4.2 LOOP TRANSMIT PORT POLLING WEIGHT RECORD 187 14.4.3 LOOP TRANSMIT CLASS STATUS RECORD .............. 188 15 TEST FEATURES DESCRIPTION ...................................................... 190 15.1 16 17 JTAG TEST PORT .................................................................... 190
OPERATION ........................................................................................ 194 FUNCTIONAL TIMING......................................................................... 195 17.1 17.2 17.3 17.4 17.5 MICROPROCESSOR INTERFACE .......................................... 195 SDRAM INTERFACE ................................................................ 197 ZBT SSRAM INTERFACE......................................................... 199 LATE WRITE SSRAM INTERFACE .......................................... 200 ANY-PHY/UTOPIA INTERFACES ............................................. 201 17.5.1 RECEIVE MASTER/TRANSMIT SLAVE INTERFACES. 201 17.5.2 TRANSMIT MASTER/RECEIVE SLAVE INTERFACES. 204
18 19 20
ABSOLUTE MAXIMUM RATINGS ....................................................... 209 D.C. CHARACTERISTICS ................................................................... 210 A.C. TIMING CHARACTERISTICS...................................................... 212 20.1 JTAG INTERFACE .................................................................... 217
21
ORDERING AND THERMAL INFORMATION...................................... 219
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
22
MECHANICAL INFORMATION............................................................ 220
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DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
LIST OF REGISTERS
REGISTER 0X00: RESET AND IDENTITY ...................................................... 98 REGISTER 0X10: HI PRIORITY INTERRUPT STATUS REGISTER ............... 99 REGISTER 0X14: HIGH PRIORITY INTERRUPT MASK............................... 101 REGISTER 0X18: LOW PRIORITY INTERRUPT ERROR REGISTER ......... 102 REGISTER 0X1C: LOW PRIORITY INTERRUPT ERROR MASK................. 104 REGISTER 0X20: LOW PRIORITY INTERRUPT STATUS REGISTER ........ 105 REGISTER 0X24: LOW PRIORITY INTERRUPT STATUS MASK................. 106 REGISTER 0X100: LOOP CELL RX INTERFACE CONFIGURATION........... 107 REGISTER 0X104: LOOP CELL TX INTERFACE CONFIGURATION ............110 REGISTER 0X200: WAN CELL RX INTERFACE CONFIGURATION .............113 REGISTER 0X204: WAN CELL TX INTERFACE CONFIGURATION .............116 REGISTER 0X300: MEMORY PORT CONTROL............................................119 REGISTER 0X340-0X34C: MEMORY WRITE DATA (BURSTABLE) ............. 121 REGISTER 0X350: MEMORY WRITE DATA OVERFLOW (BURSTABLE) ... 122 REGISTER 0X380-0X38C: MEMORY READ DATA (BURSTABLE)............... 123 REGISTER 0X390: MEMORY READ DATA OVERFLOW (BURSTABLE) ..... 124 REGISTER 0X400-0X43C: SAR RECEIVE DATA (BURSTABLE).................. 125 REGISTER 0X500-0X53C: SAR TRANSMIT DATA, CLASS 0 (BURSTABLE)127 REGISTER 0X540-0X57C: SAR TRANSMIT DATA, CLASS 1 (BURSTABLE)127 REGISTER 0X580-0X5BC: SAR TRANSMIT DATA, CLASS 2 (BURSTABLE)127 REGISTER 0X5C0-0X5FC: SAR TRANSMIT DATA, CLASS 3 (BURSTABLE)127 REGISTER 0X600: CELL BUFFER DIAGNOSTIC CONTROL ...................... 128
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DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
REGISTER 0X700: QUEUE CONTEXT CONFIGURATION .......................... 129 REGISTER 0X704: RECEIVE AND TRANSMIT CONTROL .......................... 132 REGISTER 0X710: MAX DIRECTION CONGESTION THRESHOLDS ......... 134 REGISTER 0X714: CLP0 DIRECTION CONGESTION THRESHOLDS ........ 135 REGISTER 0X718: CLP1 DIRECTION CONGESTION THRESHOLDS ........ 136 REGISTER 0X71C: RE-ASSEMBLY MAXIMUM LENGTH............................. 137 REGISTER 0X720: WATCH DOG ICI PATROL RANGE ................................ 138 REGISTER 0X724: TEAR DOWN QUEUE ID................................................ 139 REGISTER 0X728: WATCH DOG / TEAR DOWN STATUS .......................... 140 REGISTER 0X730: SHAPER 0 CONFIGURATION (N = 0)............................ 141 REGISTER 0X734: SHAPER 1 CONFIGURATION (N = 1)............................ 141 REGISTER 0X738: SHAPER 2 CONFIGURATION (N = 2)............................ 141 REGISTER 0X73C: SHAPER 3 CONFIGURATION (N = 3) ........................... 141 REGISTER 0X800: SDRAM/SSRAM CONFIGURATION............................... 144 REGISTER 0X900: BIST_OK......................................................................... 145 REGISTER 0X904: BIST_MODE ................................................................... 146 REGISTER 0X908: BIST_RESULTS A........................................................... 147 REGISTER 0X90C: BIST_RESULTS B.......................................................... 148 REGISTER 0XA00: CBI REGISTER PORT ................................................... 149 CBI REGISTER 0X00: CONFIGURATION ..................................................... 151 CBI REGISTER 0X01: VERNIER CONTROL................................................. 153 CBI REGISTER 0X02: DELAY TAP STATUS ................................................. 154 CBI REGISTER 0X03: CONTROL STATUS ................................................... 155
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DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
LIST OF FIGURES
FIGURE 1 - S/UNI APEX BLOCK WITH DATAPATH .......................................11 FIGURE 2 - S/UNI APEX BOTTOM VIEW PIN OUT....................................... 16 FIGURE 3 - 16BIT RECEIVE CELL TRANSFER FORMAT............................. 48 FIGURE 4 - 8-BIT RECEIVE CELL TRANSFER FORMAT ............................. 49 FIGURE 5 - 16-BIT TRANSMIT CELL TRANSFER FORMAT ......................... 51 FIGURE 6 - 8-BIT TRANSMIT CELL TRANSFER FORMAT ........................... 52 FIGURE 7 - I960 (80960CF) INTERFACE....................................................... 60 FIGURE 8 - POWERPC (MPC860) INTERFACE............................................ 60 FIGURE 9 - SAR ASSIST TRANSMIT CELL TRANSFER FORMAT............... 63 FIGURE 10- SAR ASSIST RECEIVE CELL TRANSFER FORMAT ................. 64 FIGURE 11 - SERVICE ARBITRATION HIERARCHY ...................................... 66 FIGURE 12- QUEUE LINKED LIST STRUCTURE .......................................... 67 FIGURE 13- TRAFFIC SHAPING ON THE WAN PORT .................................. 71 FIGURE 14- NON-INTEGER SHPINCR........................................................... 72 FIGURE 15- THRESHOLDS AND COUNT DEFINITIONS............................... 76 FIGURE 16- EPD/PPD CONGESTION DISCARD RULES .............................. 79 FIGURE 17 CELL CONGESTION DISCARD RULES ...................................... 80 FIGURE 18 FCQ DISCARD RULES ................................................................ 81 FIGURE 19- 1 BANK CONFIGURATION FOR 1MB OF ZBT SSRAM ............. 85 FIGURE 20- 1 BANK CONFIGURATION FOR 1MB OF LATE WRITE SSRAM86 FIGURE 21- 2 BANK CONFIGURATION FOR 2MB OF ZBT SSRAM ............. 87 FIGURE 22- 2 BANK CONFIGURATION FOR 2MB OF LATE WRITE SSRAM88
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DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
FIGURE 23- 4 BANK CONFIGURATION FOR 4MB OF ZBT SSRAM ............. 89 FIGURE 24- CELL STORAGE MAP................................................................. 90 FIGURE 25- 4 MB - 64K CELLS...................................................................... 91 FIGURE 26- 8 MB - 128K CELLS.................................................................... 91 FIGURE 27- 16 MB - 256K CELLS.................................................................. 92 FIGURE 28- CONTEXT LOCATION............................................................... 157 FIGURE 29- INPUT OBSERVATION CELL (IN_CELL) .................................. 191 FIGURE 30- OUTPUT CELL (OUT_CELL) .................................................... 192 FIGURE 31- BI-DIRECTIONAL CELL (IO_CELL) .......................................... 192 FIGURE 32- LAYOUT OF OUTPUT ENABLE AND BIDIRECTIONAL CELLS 193 FIGURE 33- SINGLE WORD READ AND WRITE ......................................... 195 FIGURE 34- BURST READ AND WRITE....................................................... 196 FIGURE 35- CONSECUTIVE WRITE ACCESSES USING WRDONEB........ 197 FIGURE 36- READ TIMING ........................................................................... 198 FIGURE 37- WRITE TIMING.......................................................................... 198 FIGURE 38- REFRESH.................................................................................. 199 FIGURE 39- POWER UP AND INITIALIZATION SEQUENCE....................... 199 FIGURE 40- READ FOLLOWED BY WRITE TIMING.................................... 200 FIGURE 41- READ FOLLOWED BY WRITE TIMING.................................... 201 FIGURE 42- UTOPIA L2 TRANSMIT SLAVE (LOOP & WAN) ....................... 202 FIGURE 43- UTOPIA L1 RECEIVE MASTER (LOOP & WAN) ...................... 202 FIGURE 44- UTOPIA L2 RECEIVE MASTER (LOOP & WAN) ...................... 203 FIGURE 45- ANY-PHY RECEIVE MASTER (LOOP & WAN)......................... 204 FIGURE 46- UTOPIA L2 RECEIVE SLAVE (LOOP & WAN).......................... 205
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DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
FIGURE 47- WAN UTOPIA L1 TRANSMIT MASTER .................................... 205 FIGURE 48- LOOP UTOPIA L1 TRANSMIT MASTER................................... 206 FIGURE 49- WAN UTOPIA L2 TRANSMIT MASTER .................................... 206 FIGURE 50- LOOP UTOPIA L2 TRANSMIT MASTER................................... 207 FIGURE 51- WAN ANY-PHY TRANSMIT MASTER ....................................... 207 FIGURE 52- LOOP ANY-PHY TRANSMIT MASTER ..................................... 208 FIGURE 53- RSTB TIMING............................................................................ 212 FIGURE 54- SYNCHRONOUS I/O TIMING ................................................... 213 FIGURE 55- JTAG PORT INTERFACE TIMING ............................................ 217 FIGURE 56- MECHANICAL DRAWING 352 PIN BALL GRID ARRAY (SBGA)220
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DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
LIST OF TABLES
TABLE 1 TABLE 2 TABLE 3 TABLE 4 TABLE 5 TABLE 6 TABLE 7 TABLE 8 TABLE 9
- TERMINOLOGY ............................................................................ 1 - SAMPLE FEATURE SET AS A FUNCTION OF MEMORY CAPACITY ..................................................................................... 15 - PIN TYPE DEFINITION ............................................................... 17 - NUMBER OF PORTS SUPPORTED, RECEIVE INTERFACE .... 50 - NUMBER OF PORTS SUPPORTED, TRANSMIT INTERFACE.. 53 - EXAMPLE WIRR TRANSMISSION SEQUENCE ........................ 56 - AVAILABLE QUEUING PROCEDURES ...................................... 68 - OAM & RRM CELL IDENTIFICATION ......................................... 73 - CONGESTION ERROR FLAGS .................................................. 77
TABLE 10 - CONGESTION DISCARD RULES SELECTION ......................... 78 TABLE 11 - STATISTICAL COUNTS .............................................................. 82 TABLE 12 - IN/OUT BOUND CLP STATE FOR STATISTICAL COUNTS ....... 83 TABLE 13 - CONGESTION RULE & COUNT SUMMARY .............................. 83 TABLE 14 - RECEIVE INTERFACE THROUGHPUT, MCELLS/SEC ............. 94 TABLE 15 - QUEUE ENGINE THROUGHPUT, MCELLS/SEC....................... 95 TABLE 16 - TRANSMIT INTERFACE THROUGHPUT, MCELLS/SEC ........... 95 TABLE 17 - EXTERNAL QUEUE CONTEXT MEMORY MAP....................... 158 TABLE 18 - INTERNAL QUEUE CONTEXT MEMORY MAP........................ 158 TABLE 19 - INTERNAL WAN PORT SCHEDULER CONTEXT MEMORY MAP ..................................................................................................... 159 TABLE 20 - INTERNAL LOOP PORT SCHEDULER CONTEXT MEMORY MAP ..................................................................................................... 159 TABLE 21 - 2 BIT LOGARITHMIC, 2 BIT FRACTIONAL .............................. 160
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DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
TABLE 22 - 4 BIT LOGARITHMIC, 2 BIT FRACTIONAL .............................. 160 TABLE 23 - 4 BIT LOGARITHMIC, 4 BIT FRACTIONAL .............................. 160 TABLE 24 - VC CONTEXT RECORD STRUCTURE .................................... 161 TABLE 25 - VC STATISTICS RECORD STRUCTURE ................................. 168 TABLE 26 - VC ADDRESS MAP RECORD STRUCTURE ........................... 168 TABLE 27 - PORT THRESHOLD CONTEXT RECORD STRUCTURE ........ 170 TABLE 28 - PORT COUNT CONTEXT RECORD STRUCTURE.................. 171 TABLE 29 - CLASS SCHEDULER RECORD STRUCTURE ........................ 173 TABLE 30 - CLASS CONTEXT RECORD STRUCTURE ............................. 176 TABLE 31 - SHAPE TXSLOT CONTEXT RECORD STRUCTURE .............. 178 TABLE 32 - SHAPE RATE CONTEXT RECORD STRUCTURE................... 179 TABLE 33 - CELL CONTEXT RECORD STRUCTURE ................................ 180 TABLE 34 - FREE COUNT CONTEXT STRUCTURE .................................. 181 TABLE 35 - OVERALL COUNT CONTEXT STRUCTURE............................ 181 TABLE 36 - CONGESTION DISCARD CONTEXT STRUCTURE ................ 182 TABLE 37 - MAXIMUM CONGESTION ID CONTEXT STRUCTURE........... 183 TABLE 38 - MISC ERROR CONTEXT STRUCTURE................................... 183 TABLE 39 - WAN TRANSMIT PORT POLLING WEIGHT ............................ 184 TABLE 40 - WAN POLL WEIGHT FORMAT ................................................. 185 TABLE 41 - WAN CLASS STATUS ............................................................... 185 TABLE 42 - LOOP TRANSMIT PORT POLLING SEQUENCE ..................... 186 TABLE 43 - LOOP TRANSMIT PORT POLLING WEIGHT........................... 187 TABLE 44 - LOOP CLASS STATUS ............................................................. 188 TABLE 45 - INSTRUCTION REGISTER ....................................................... 190
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TABLE 46 - IDENTIFICATION REGISTER ................................................... 190 TABLE 47 - BOUNDARY SCAN REGISTER ................................................ 190 TABLE 48 - ABSOLUTE MAXIMUM RATINGS ............................................. 209 TABLE 49 - D.C. CHARACTERISTICS......................................................... 210 TABLE 50 - RTSB TIMING............................................................................ 212 TABLE 51 - SYSCLK TIMING ....................................................................... 213 TABLE 52 - CELL BUFFER SDRAM INTERFACE........................................ 213 TABLE 53 - CONTEXT MEMORY ZBT & LATE WRITE SSRAM INTERFACE ..................................................................................................... 213 TABLE 54 - MICROPROCESSOR INTERFACE ........................................... 214 TABLE 55 - LOOP ANY-PHY TRANSMIT INTERFACE ................................ 214 TABLE 56 - WAN ANY-PHY TRANSMIT INTERFACE .................................. 215 TABLE 57 - LOOP ANY-PHY RECEIVE INTERFACE................................... 215 TABLE 58 - WAN ANY-PHY RECEIVE INTERFACE .................................... 216 TABLE 59 - JTAG PORT INTERFACE.......................................................... 217
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DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
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1
DEFINITIONS Table 1 Term AAL5 ABR Any-PHY ATLAS ATM BOM CBI CBR CDV CDVT CES CLP COM COS CTD DLL DSL DSLAM DUPLEX ECI EFCI EOM EPD FIFO GCRA - Terminology Definition ATM Adaptation Layer Available Bit Rate Interoperable version of UTOPIA and SCI-PHY, with inband addressing. PMC's OAM and Address Resolution device Asynchronous Transfer Mode Beginning of Message Common Bus Interface Constant Bit Rate Cell Delay Variation Cell Delay Variation Tolerance Circuit Emulation Service Cell Loss Priority Continuation of Message Class of Service Cell Transfer Delay Delay Locked Loop Digital Subscriber Loop DSL access Multiplexer PMC UTOPIA deserializer Egress Connection Identifier Early forward congestion indicator End of Message Early Packet Discard First-In-First-Out Generic Cell Rate Algorithm
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DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
GFR IBT ICI MBS MCR OAM PCR PDU PHY PPD PTI QOS QRT QSE RRM SAR SCI-PHY SCR UBR UTOPIA VBR VCC VORTEX VPC WAN WIRR WRR ZBT
Guaranteed Frame Rate Intrinsic Burst Tolerance Ingress Connection Identifier Maximum Burst Size Minimum Cell Rate Operation, Administration and Maintenance Peak Cell Rate Packet Data Unit Physical Layer Device Partial Packet Discard Payload Type Indicator Quality of Service PMC's traffic management device PMC's switch fabric device Reserved or Resource Management Segmentation and Re-assembly PMC-Sierra enhanced UTOPIA bus Sustained Cell Rate Unspecified Bit Rate Universal Test & Operations PHY Interface for ATM Variable Bit Rate Virtual Channel Connection PMC UTOPIA/Any-PHY slave serializer Virtual Path Connection Wide Area Network Weighted Interleaved Round Robin Weighted Round Robin Zero Bus Turnaround
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DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
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FEATURES * Monolithic single chip ATM traffic manager providing VC queuing/shaping and VC, Class Of Service(COS), and Port scheduling, congestion management, and switching across 2048 ports. Targeted at systems where many low speed ATM data ports are multiplexed onto few high speed ports. 869 Kcells/s non shaped throughput in full duplex. 1.73 Mcells/s non shaped throughput in half duplex. 1.42 Mcells/s shaped throughput (aggregate of the four shapers) Supports four WAN uplink ports, with port aliasing Supports 2048 loop ports. Loop port can support an uncongested rate up to 230Kcells/sec. Provides 4 Classes of Service per port with configurable traffic parameters enabling support for a mix of CBR, VBR, GFR, and UBR classes. Provides 64k per-VC queues individually assignable to any COS in any port. Provides support of up to 256k cells of shared buffer Provides 2 independent cell emission schedulers, 1 for the WAN ports, and 1 for the Loop ports. The schedulers have the following features: Three level hierarchical cell emission scheduling at the port, class, and VC levels. * WAN Port Scheduling * * * Weighted Interleaved Round Robin WAN port scheduling. Per port Priority Fair Queued class scheduling with port independence. Per Class * Weighted Fair Queued VC scheduling with class independence or
* * * * * * * * * *
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DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
* * *
Shaped Fair Queued VC scheduling applying rate based per VC shaping or Frame Continuous Queued VC scheduling for VC Merge and packet re-assembly.
Loop Port Scheduling * * * Weighted Interleaved Round Robin Loop port scheduling. Per port Priority Fair Queued class scheduling with port independence. Per Class * * Weighted Fair Queued VC scheduling with class independence or Frame Continuous Queued scheduling for VC Merge and packet re-assembly
*
Congestion Control applied per-VC, per-class, per-port and per-direction. * Flexible, progressive hierarchical throttling of buffer consumption. Provides sharing of resources during low congestion, memory reservation during high congestion. Applies EPD and PPD on a per-VC, per-class, per-port, and per-direction basis with CLP differentiation, following emerging GFR standards. Provides EFCI marking on a per VC basis. Provides interrupts and indication of most recent VC/Class/Port that exceeded maximum thresholds.
* * * *
Provides flexible VPC or VCC switching selectable on a per VC basis as follows * * * * Any WAN port to any WAN port Any WAN port to any Loop port Any Loop port to any WAN port. Any Loop port to any Loop port.
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DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
* * * * * *
Microprocessor port to any loop or WAN port. Any loop or WAN port to microprocessor port VP Termination (in conjunction with ATLAS) VPI or VPI/VCI header mapping VC merge
Provides flexible signaling and control capabilities * * * * * Provides 4 independent uP transmit queues Provides simultaneous AAL5 SAR assistance for traffic to/from the uP on up to 64k VCs. Supports uP cell injection into any queue. Provides per VC selectable OAM cell pass through or switching to microprocessor port. Supports CRC10 calculation for OAM cells destined for/originating from the microprocessor.
* * * * * *
Diagnostic access provided to context memory and cell buffer memory via the microprocessor. Provides per VC CLP0/1 transmit counts. Provide global per CLP0/1 discard counts Provides various error statistics accumulation. Determines the ingress connection identifier from one of several locations: the cell prepend, the VPI/VCI field, or the HEC/UDF field. Interface support * * Provides a 8/16-bit Any-PHY compliant master/slave Loop side interface supporting up to 2048 ports (logical PHYs). Provides an 8/16-bit Any-PHY compliant master/slave WAN side interface supporting up to 4 ports (PHYs).
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DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
*
Provides a 32-bit multiplexed microprocessor bus interface for signaling, control, and cell message extraction and insertion, context memory access, control and status monitoring, and configuration of the IC. Provides a 32-bit SDRAM interface for cell buffering. Provides a 36-bit pipelined ZBT or register to register late write SSRAM interface for context storage.
* * *
Packaging * * * Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes. Implemented in low power, 0.25 micron, +2.5/3.3V CMOS technology with CMOS compatible inputs and outputs. 352-pin high-performance ball grid array (SBGA) package.
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6
PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
3
APPLICATIONS * * * * * * DSL Access Multiplexers ATM Switches Multiservice Access Multiplexers 3rd generation wireless base stations and base station controllers OC-12 ingress congestion and traffic management OC-12 egress traffic manager and shaper
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
4
REFERENCES
1. PMC-Sierra; "Saturn Compatible Interface For ATM PHY Layer And ATM Layer Devices, Level 2"; PMC-940212; Dec. 8, 1995 2. PMC-Sierra; VORTEX engineering document 3. PMC-Sierra; DSLAM engineering document 4. "Traffic Management And Switching With The Vortex Chip Set: S/UNI-APEX Technical Overview", PMC-981024 5. PMC-Sierra, "S/UNI APEX Test Bench Engineering Document", PMC-981029 6. ATM Forum, "Universal Test & Operations PHY Interface for ATM (UTOPIA), Level 2", Version 1.0, af-phy-0039.000, June 1995 7. ITU-T Recommendation I.432.1, "B-ISDN user-network interface - Physical layer specification: General characteristics", 08/96 8. ITU-T Recommendation I.363, "B-ISDN ATM Adaptation Layer (AAL) Specification", March 1993 9. AF Traffic Management Specification Version 4.1 AF-TM-0121.000, March 1999. 10. AF Traffic Management Baseline Text Document BTD-TM-01.01, April 1998 11. I.610 OAM 12. PMC Sierra, "Saturn Interface Specification and Interoperability Framework for Packet and Cell Transfer Between Physical Layer and Link Layer Devices", PMC980902 13. PMC Sierra, "S/UNI APEX H/W Programmer's Guide", PMC-991454
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
5
APPLICATION EXAMPLES Please refer to the document "Traffic Management And Switching With The Vortex Chip Set: S/UNI-APEX Technical Overview", PMC-981024
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
6
BLOCK DIAGRAM Figure 1 shows the function block diagram of the S/UNI APEX ATM traffic manager. The functional diagram is arranged such that cell traffic flows through the S/UNI APEX from left to right.
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
Figure 1
- S/UNI APEX Block with Datapath
CMD[33:0] CMP[1:0] CMA[19:0] CMRWB CMCEB CMAB[18:17] SSRAM I/F Queue Engine
BCLK CSB WR AD[31:0] ADSB BURSTB BLAST READYB WRDONEB INTHIB INTLOB BUSPOL LRCLK LRPA LRSX LRSOP LRDAT[15:0] LRPRTY LRENB LRADR[5:0] WRCLK WRPA WRSX WRSOP WRDAT[15:0] WRPRTY WRENB WRADDR[2:0]
uProc I/F
FIFO 4 chan 2 cell FIFO 2 cell
SAR Assist
FIFO 4 cell
Loop Tx Any-PHY
Loop Port Scheduler
LTADR[11:0] LTPA LTENB LTSX LTSOP LTDAT[15:0] LTPRTY LTCLK
Loop Rx Any-PHY
FIFO 4 cell
ICI Select
FIFO 4 chan 4 cell
WAN Tx Any-PHY
WTADR[2:0] WTPA WTENB WTSX WTSOP WTDAT[15:0] WTPRTY WTCLK TDO TDI TCK TMS TRSTB SYSCLK
WAN Rx Any-PHY
FIFO 4 cell
ICI Select
Wan Port Scheduler JTAG
SDRAM I/F
RSTB OE
CBCSB CBRASB CBCASB CBRWEB CBA[11:0] CBBS[1:0] CBDQM[1:0] CBDQ[31:0]
Cell Data Path Context Data Path
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
7
DESCRIPTION The PM7326 S/UNI APEX is a full duplex ATM traffic management device, providing cell switching, per VC queuing, traffic shaping, congestion management, and hierarchical scheduling to up to 2048 loop ports and up to 4 WAN ports. The S/UNI APEX provides per-VC queuing for 64K VCs. A per-VC queue may be allocated to any Class of Service (COS), within any port, in either direction (ingress or egress path). Per-VC queuing enables PCR or SCR per-VC shaping on WAN ports and greater fairness of bandwidth allocation between VCs within a COS. The S/UNI APEX provides three level hierarchical scheduling for port, COS, and VC level scheduling. There are two, three level schedulers; one for the loop ports and one for the WAN ports. The three level scheduler for the WAN ports provides * Weighted Interleaved Round Robin (WIRR) scheduling across the 4 WAN ports enabling selectability of bandwidth allocation between the ports. * Priority Fair scheduling across the 4 COS's within each port. This class scheduler is a modified priority scheduler allowing minimum bandwidth allocations to lower priority classes within the port. Class scheduling within a port is independent of activity on all other ports. * There are three types of VC schedulers. VC scheduling within a class is independent of activity on all other classes * Shaped fair queuing is available for 4 classes. If the COS is shaped, each VC within the class is scheduled for emission based on its VCs shaping rate. During class congestion, the VC scheduler may lower a VCs rate in proportion to a normalization factor calculated as a function of the VCs rate and the aggregate rate of all active VCs within the class. * Weighted Interleaved Round Robin scheduling in which weights are used to provide fairness between the VCs within a class. * Frame continuous scheduling where an entire packet is accumulated prior to transferring to a class queue. The three level scheduler for the loop ports provides * Weighted Interleaved Round Robin (WIRR) scheduling across the 2048 loop ports enabling selectability of bandwidth allocation between the ports
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
and ensuring minimal PHY layer FIFOing is required to support a wide range of port bandwidths. * Priority scheduling across the 4 COS's within each port. Class scheduling within a port is independent of activity on all other ports. * VCs within a class are scheduled with a Round Robin scheduler or Frame Continuous scheduling. VC scheduling within a class is independent of activity on all other classes. Shaping is not supported on loop ports. The S/UNI APEX forwards cells via tail of queue enqueuing and head of queue dequeuing (emission) where tail of queue enqueuing is controlled by the VC context record and subject to congestion control, and head of queue dequeuing is controlled by the three level hierarchical schedulers. The VC context record allows for enqueuing to any queue associated with any port, thus full switching is supported, any port to any port. The S/UNI APEX supports up to 256k cells of shared buffering in a 32-bit wide SDRAM. Memory protection is provided via an inband CRC on a cell by cell basis. Buffering is shared across direction, port, class, and VC levels. The congestion control mechanism provides guaranteed resources to all active VCs, allows sharing of available resources to VCs with excess bandwidth, and restricts buffer allocation on a per-VC, per-class, per-port, and per-direction basis. The congestion control mechanism supports PPD and EPD on a CLP0 and CLP1 basis across per-VC, per-class, per-port, and per-direction structures. EFCI marking is supported on a per-VC basis. Congestion thresholds and packet awareness is selectable on a per connection basis. The S/UNI APEX provides flexible capabilities for signaling, management, and control traffic. There are 4 independent uP receive queues to which both cell and AAL5 frame traffic may be en-queued for termination by the uP. A staging buffer is also provided enabling the uP to en-queue both cell and AAL5 frame traffic to any outgoing queue. AAL5 SAR assistance is provided for AAL5 frame traffic to and from the uP. AAL5 SAR assistance includes the generation and checking of the 32-bit CRC field and the ability to reassemble all the cells from a frame in the VC queue prior to placement on the uP queues. Any or all of the 64k VCs may be configured to be routed to/from the uP port. Any or all of the VCs configured to be routed to/from the uP port may also be configured for AAL5 SAR assistance simultaneously. OAM cells may optionally (per-VC selectable) be routed to a uP receive queue or switched with the user traffic. CRC10 generation and checking is optionally provided on OAM cells to/from the uP. The S/UNI APEX maintains cell counts of CLP0 and CLP1 cell transmits on a per-VC basis. Global CLP0 and CLP1 congestion discards are also maintained. Various error monitoring conditions and statistics are accumulated or flagged.
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
The uP has access to both internal S/UNI APEX registers and the context memory as well as diagnostic access to the cell buffer memory. The S/UNI APEX provides a 8/16-bit Any-PHY compliant loop side master/slave interface supporting up to 2048 ports. Egress cell transfers across the interface are identified via an inband port identifier prepended to the cell. The slave devices must match the inband port identifier with their own port ID or port ID range in order to accept the cell. Per port egress flow control is effected via an 12-bit address polling bus to which the appropriate slave device responds with out of band per port flow control status. Ingress cell transfers across the interface are effected via a combination of UTOPIA L2 flow control polling and device selection for up to 32 slave devices. The Any-PHY loop side interface may be reconfigured as a standard single port UTOPIA L2 compliant slave interface. 16bit prepends are optionally supported on both ingress and egress for cell flow identification enabling use with external address resolution devices, switch fabric interfaces, or other layer devices. The S/UNI APEX provides an 8/16-bit Any-PHY or UTOPIA L2 compliant WAN side master/slave interface supporting up to 4 ports. 16-bit prepends are optionally supported on both ingress and egress for cell flow identification enabling use with external address resolution devices, switch fabric interfaces, or other layer devices. The WAN port has port aliasing on the egress, providing in service re-direction without requiring re-programming the context of active VCs. The S/UNI APEX provides a 32-bit microprocessor bus interface for signaling, control, cell and frame message extraction and insertion, VC. Class and port context access, control and status monitoring, and configuration of the IC. Microprocessor burst access for registers, cell and frame traffic is supported. The S/UNI APEX provides a 36-bit ZBT or late write SSRAM interface for context storage supporting up to 4MB of context for up to 64kVCs and up to 256k cell buffer pointer storage. Context Memory protection is provided via 2 bits of parity over each 34-bit word. The total number of cells, the total number of VCs, support for address mapping and shaped fair queuing is limited to the amount of context and cell buffer memory available. Below is a table illustrating the most common combinations of memory/features.
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
Table 2
- Sample feature set as a function of memory capacity Cell Buffer Memory Size SDRAM 4MB 4MB 4MB 16MB 16 K 16 K 64 K 64 K 64 K 64 K 64 K 256 K # VC # Cell Buffers Address Mapping Support Shaping Support
Context Memory Size SSRAM 1 MB 2 MB 2 MB 4 MB
Yes Yes No Yes
No Yes No Yes
The S/UNI APEX provides facilities to enable sparing capability with another S/UNI APEX device. The facilities enable a 'warm standby' capability in which connection setup between the two devices can be maintained identically but some cell loss will occur at the point of device swapping. The facilities do not include a cell by cell lock step between the two S/UNI APEX devices. To avoid any cell replication, queues in the 'spare' S/UNI APEX will be kept empty, thus causing all queued traffic in the 'active' S/UNI APEX to be lost at the point of switch over. However, since connection setup is maintained identically between the two S/UNI APEX devices, switch over can happen instantaneously, thus avoiding any connection timeout or tear down issues. The S/UNI APEX facilities provided are the disable and filter control bits in the Receive and Transmit Control register. These control bits are asserted in the spare S/UNI APEX to ensure the queues remain empty until swapping is initiated. Alternatively, asserting only the filter enable bits allow signalling and control traffic continuity to be maintained to the spare S/UNI APEX to enable datapath integrity testing on the spare plane and to ensure control communications paths to the spare plane are usable.
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
8
PIN DIAGRAM The S/UNI APEX is packaged in a 352-pin ball grid array (SBGA) package having a body size of 35 mm by 35 mm. Figure 2
26 25 24 23 22 A vss5 vss4 C MD [0] C MD [4] CMD [7]
- S/UNI APEX Bottom View Pin out
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 C MD [11] C MD [14] CMD [18] CMD [21] PCH CMD [27] CMD [30] vss3 vss2 AD [2] AD [4] PCH AD [10] AD [13] AD [17] AD [20] A D [24] A D [27] AD [31] vss1 vss0 A
B
vss9
vd d 10
vss8
C MD [1]
CMD [5]
CMD [8]
C MD [12] CMD [15] CMD [19] CMD [23] CMD [25] CMD [29] CMD [32] CMD [ 33]
SYSCLK
AD [6]
AD [8]
AD [12]
AD [16]
AD [19]
AD [23]
A D [26]
A D [30]
vss7
vd d 9
vss6
B
C
C MRWB
vss11
vd d 12
CMP [1]
CMD [2]
CMD [6]
CMD [9]
CMD [13] CMD [16] CMD [20] CMD [24] CMD [28] CMD [31]
AD [0]
AD [3]
AD [7]
AD [11]
AD [15]
AD [18]
AD [22]
AD [25]
A D [29]
INT HIB
vd d 11
vss10
BCLK
C
D
CMAB [1]
CMCEB
CMP [0]
vd d 17
nc
CMD [3]
PCH
CMD [10]
vd d 16
CMD [17] CMD [22] CMD [26]
vd d 15
AD [1]
AD [5]
AD [9]
AD [14]
vd d 14
AD [21]
PCH
AD [28]
nc
vd d 13
INTLOB
WRDO NEB
BLAST
D
E
CMA [ 16] CMA [ 17] CMA [19]
nc
BUSPOL
BTERMB
BURSTB
CS B
E
F
CMA [ 12] CMA [ 15] CMAB [0] CMA [18]
READYB
WR
ADSB
LRADR [2]
F
G
CMA [9]
CMA [ 11] CMA [14]
PCH
PCH
LRA DR [ 0] LRA DR [ 3] LRADR [5]
G
H
CMA [5]
C MA [8]
CMA [10] CMA [13]
LRADR [ 1] LRA DR [ 4]
LRENB
LRPRTY
H
J
CMA [2]
C MA [4]
C MA [7]
vd d 18
vd d 19
LRPA
LRSOP
LRDAT [0]
J
K
PCH
C MA [0]
C MA [3]
C MA [6]
LRCLK
LRSX
LRDAT [ 1] LRDAT [3]
K
L
LTDAT [12] LTDAT [14] LTDAT [15] C MA [1]
PCH
LRDAT [ 2] LRDAT [ 4] LRDAT [6]
L
M
LTDAT [ 9] LTDAT [10] LTDAT [11] LTDAT [13]
LRDAT [ 5] LRDAT [ 7] LRDAT [ 8] LRDAT [9]
M
N
vss13
LTDAT [ 6]
LTDAT [ 7]
LTDAT [ 8]
vd d 20
LRDAT [10] LRDAT [ 11]
vss12
N
P
vss15
LTDAT [ 5]
LTDAT [ 4]
vd d 21
LRDAT [14] LRDAT [13] LRDAT [ 12]
vss14
P
R
LTDAT [ 3]
LTDAT [ 2]
LTDAT [ 1]
LTPA
PCH
WRADR [ 1]
WRADR LRDAT [ 15] [0]
R
T
LTDAT [ 0]
LTCLK
LTENB
LTSOP
WRSOP
WRCLK
WRENB
WRA DR [2]
T
U
PCH
LT SX
LTADR [11] LTADR [8]
WRDAT [3] WRDAT [0]
WRPRTY
WRPA
U
V
LTPRTY
LTADR [10] LTADR [7]
vd d 23
vd d 22
WRDAT [4] WRDA T [1]
WRSX
V
W
LTADR [9] LTADR [6] LTADR [4] LTADR [1]
PCH
WRDAT [7] WRDA T [5] WRDA T [2]
W
Y
LTADR [5] LTADR [3] LTADR [0]
WTDAT [14]
WRDA T [ 13]
WRDAT WRDA T [8] WRDA T [6] [ 10]
Y
AA
LTADR [2]
WTDAT [15]
WTDAT [13]
WTDAT [10]
RSTB
WRDAT [ 14]
WRDAT WRDA T [9] [ 11]
AA
AB
PCH
WTDAT [12]
WTDAT [9]
nc
nc
TDI
WRDAT [ 15]
WRDAT [ 12]
AB
AC
WTDAT [11]
WTDAT [8] WTDAT [6]
vd d 4
SCANMB WTDAT [ 2]
WTENB
WTSOP
vd d 3
CBA [9]
CBA [4]
CBA [0]
CBCA SB
vd d 2
CBDQ [26]
CBDQ [22]
CBDQ [17]
vd d 1
C BDQ [10]
C BDQ [7] C BDQ [3]
nc
vd d 0
TRSTB
TMS
OE
AC
AD
WTDAT [7]
vss17
vd d 6
SCANEN WTDAT [ 3]
WTPA
WTCLK
WTADR [1] CBA [ 10]
CBA [6]
CBA [2]
CBBS [ 0]
C BWEB
CBDQ [31]
CBDQ [28]
CBDQ [24]
CBDQ [20]
C BDQ [16]
C BDQ [13]
C BDQ [9] C BDQ [6] C BDQ [2]
T DO
vd d 5
vss16
TCK
AD
AE
vss21
vd d 8
vss19
WTDAT [4] WTDAT [ 0]
WT SX
WT DR [ 0] CBA [ 11] A
CBA [7]
CBA [3]
CBA [1]
C BCSB
CBDQ M [1]
CBDQM [0]
CBDQ [29]
CBDQ [25]
CBDQ [23]
C BDQ [19]
C BDQ [15]
C BDQ [12]
C BDQ [8] C BDQ [5] CBDQ [1]
vss20
vd d 7
vss18
AE
AF
vss27
vss26
WTDAT [5] WTDAT [1]
PCH
WTPRTY WT DR [ 2] A
CBA [ 8]
CBA [5]
PCH
CBBS [ 1]
CBRASB
vss25
vss24
CBDQ [30] 12
CBDQ [27] 11
PCH
C BDQ [21] 9
C BDQ [18] 8
C BDQ [14] 7
CBDQ [11] 6
PCH
CBDQ [4] CBDQ [0]
vss23
vss22
AF
26
25
24
23
22
21
20
19
18
17
16
15
14
13
10
5
4
3
2
1
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
9
PIN DESCRIPTION Notes on Pin Description: 1. All S/UNI APEX inputs and bi-directionals present minimum capacitative loading 2. LVCMOS, LVTTL compatible logic levels. 3. All pins are 5V tolerant. 4. Inputs RSTB, OE, TMS, TDI and TRSTB have internal pull-up resistors. 5. The recommended power supply sequencing is as follows: 3.1 VDD power must be supplied either before or simultaneously with PCH. 3.2 The VDD power must be applied before input pins are driven or the input current per pin be limited to less than the maximum DC input current specification. (20 mA) 3.3 Power down the device in the reverse sequence. Table 3 Type Input Output Tri-State BiDi OD - Pin Type Definition Definition Input Pin is always driven Pin is either driven, or held in Hi-Z Bidirectional Open drain. Either driven low or held in Hi-Z.
9.1
Loop Any-PHY Receive Master/Transmit Slave Interface (28 Signals) Pin Name LRCLK Type Input Pin No.
K4
Function Loop Receive Clock. LRCLK is used to transfer data blocks in the receive directions across the AnyPHY interface. LRCLK must cycle at a 52 MHz or lower instantaneous rate.
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
Pin Name LRPA
Type
Pin No.
Function Loop Receive Packet Available. LRPA indicates whether at least one cell is queued for transfer in the selected PHY device. This pin is in Hi-Z when the loop receive interface is not enabled. If receive master mode is selected, this signal is an input. The selected PHY device drives LRPA with the cell availability status N LRCLK cycles after LRADR[5:0] matches the PHY device address. If the PHY device is a UTOPIA device, N=1. If the PHY device is an Any-PHY device, N=2. Assertion of LRPA indicates that at least one entire cell is available. If transmit slave mode is selected, this signal is a tristate output. The S/UNI APEX drives LRPA high 1 LRCLK after LRADR[5:0] matches the programmed LoopRxSlaveAddr register. A logical high indicates that the S/UNI APEX is capable of accepting at least one cell. LRPA is sampled/updated/Hi-Z'd on the rising edge of LRCLK.
J3 Input (Master)
Tri-state (Slave)
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
Pin Name LRENB
Type Input (Slave) Output (Master)
Pin No.
H2
Function Loop Receive Enable. The active low receive enable (LRENB) signal is used to initiate the transfer of a data block from the selected Physical layer device to the S/UNI APEX. This pin is in Hi-Z when the loop receive interface is not enabled. If receive master mode is selected, this signal is an output and the start of block transfer must occur 1 or 2 LRCLK cycles after device selection occurs. If the PHY device is a UTOPIA device, N=1. If the PHY device is an Any-PHY device, N=2. Device selection occurs when the selected device address is placed on LRADR[5:0] with LRENB held high followed by LRENB low in the next LRCLK period. LRENB is held low for M cycles where M is the number of 8 or 16-bit words in the block transfer. If transmit slave mode is selected, this signal is an input and LRDAT[15:0] word is accepted coincident with LRENB being sampled. LRENB is sampled/updated on the rising edge of LRCLK.
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
Pin Name LRADR[0] .. LRADR[5]
Type Input (Slave) Output (Master)
Pin No.
G3 H4 F1 G2 H3 G1
Function Loop Receive Address. The LRADR[5:0] signals are used to address up to thirty two Physical layer devices for the purposes of polling and device selection. This pin is in Hi-Z when the loop receive interface is not enabled. If UL2 or Any-PHY receive master mode is selected, these signals are outputs. LRADR[5:0] selects a device for polling by applying the device address N LRCLK cycles prior to sampling LRPA. If the PHY device is a UTOPIA device, N=1. If the PHY device is an Any-PHY device, N=2. LRADR will insert 1 NULL address between address changes. If UL1 master mode is selected, this bus is driven to a high NULL address. LRADR[5:0] selects a device to transfer a data block when the LRENB is last sampled high. The start of data block transfer must occur 1 or 2 LRCLK cycles after device selection occurs. LRADR[5:0] = 3F hex is used as the NULL address. No PHY device can match the NULL address. If transmit slave mode is selected, these signals are inputs. The S/UNI drives the LRPA 1 LRCLK after the LRADR[4:0] matches the programmed LoopRxSlaveAddr register, and LRADR[5] is zero. LRADR[5:0] is sampled/updated or on the rising edge of LRCLK.
LRSX
Input
K3
Loop Receive Start of Transfer. LRSX is asserted by the selected PHY device during the first cycle of a data block transfer coinciding with the port address prepend. Required only during Any-PHY mode. For UTOPIA modes, this signal should be tied low. LRSX is sampled on the rising edge of LRCLK.
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
Pin Name LRSOP
Type Input
Pin No.
J2
Function Loop Receive Start of Packet . LRSOP marks the start of the cell on the LRDAT[15:0] bus. When LRSOP is high, the first data word of the cell is present on the LRDAT[15:0] stream. If the selected device is an Any-PHY device, the LRSOP cycle will be preceded by the LRSX cycle marking the AnyPHY port address transfer cycle. LRSOP considered valid only when the LRENB signal is low. LRSOP becomes high impedance upon sampling LRENB high or if no physical layer device was selected for transfer. LRSOP is sampled on the rising edge of LRCLK.
LRDAT[0] .. LRDAT[15]
Input
J1 K2 L3 K1 L2 M4 L1 M3 M2 M1 N3 N2 P2 P3 P4 R1
Loop Receive Data. LRDAT[15:0] carries the transfer block words that have been read from the physical layer device to the S/UNI APEX internal cell buffers. LRDAT bus is considered valid only when the LRENB signal was low N cycles previous. LRDAT is expected to become high impedance N LRCLK cycles after sampling LRENB high or upon completion of a data block transfer. If the PHY device is a UTOPIA device, N=1. If the PHY device is an Any-PHY device, N=2. All 16 bits are used in 16-bit mode. In 8 bit mode, LRDAT[15:8] should either be tied high or low, as only the first 8 bits LTDAT[7:0] are valid. LRDAT[15:0] is sampled on the rising edge of LRCLK.
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
Pin Name LRPRTY
Type Input
Pin No.
H1
Function Loop Receive Parity. LRPRTY provides programmable odd/even parity of the LRDAT[15:0] bus. LRPRTY is considered valid only when the LRENB signal was low N cycles previous. If the PHY device is a UTOPIA device, N=1. If the PHY device is an Any-PHY device, N=2. LRPRTY is expected to become high impedance N LRCLK cycles after sampling LRENB high. A parity error is indicated by a status bit and a maskable interrupt. LRPRTY is sampled on the rising edge of LRCLK.
9.2
Loop Any-PHY Transmit Master/Receive Slave Interface (34 Signals) Pin Name LTCLK Type Input Pin No.
T25
Function Loop Transmit Clock. LTCLK is used to transfer data blocks in the transmit direction across the AnyPHY interface. LTCLK must cycle at a 52 MHz or lower instantaneous rate.
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
Pin Name
LTADR[0] .. LTADR[11]
Type
Pin No.
Function
Output Y24 (Master) W23 Input (Slave)
W24 Y26 W25 V24 U23 W26 V25 U24
Loop Transmit Address. The LTADR[11:0] signals are used to address up to 2048 logical channels for AA26 the purposes of polling on the LTPA signal. 1 or Y25 more PHY devices can share the LTPA signal This pin is in Hi-Z when the loop transmit interface is not enabled. If transmit master mode is selected, these signals are outputs. LTADR[11:0] selects a logical channel for polling by applying the logical channel address N LTCLK cycles prior to sampling LTPA. If the PHY device is a UTOPIA device, N=1. If the PHY device is an Any-PHY device, N=2. LTADR inserts NULL cycles between addresses. For Any-PHY transmit master, LTADR[11:0] corresponds to the PORTID[11:0] fields in the AnyPHY address word prepend format. For UTOPIA L2 transmit master, LTADR[5:0] is also used to select a UTOPIA device to transfer a cell to, when LTENB is last sampled high. LTADR[11:6] should be left unconnected. For UTOPIA L1 transmit master, LTADR[11:0] is unused and should be left unconnected. If UTOPIA L2 receive slave mode is selected, these signals are inputs. The S/UNI APEX drives LTPA high 1 LTCLK after the LTADR[5:0] matches the programmed LoopTxSlaveAddr register. LTADR[11:6] are unused and should be tied either high or low. LTADR[11:0] is sampled/updated on the rising edge of LTCLK.
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
Pin Name LTPA
Type
Pin No.
Function Loop Transmit Packet Available. LTPA indicates the availability of space in the selected polled port when polled using the LTADR[11:0] signals. This pin is in Hi-Z when the loop transmit interface is not enabled. If transmit master mode is selected, this signal is an input. The PHY device whose address or address range matches LTADR[11:0] drives the LTPA signal with the transmit FIFO availability status of the selected logical channel N LTCLK cycles after the match. If the PHY device is a UTOPIA device, N=1. If the PHY device is an Any-PHY device, N=2. Assertion of LTPA indicates that at least K entire cell buffer is available in that logical channel. K = 1 if the register LoopTxTwoCellEn = 0. K = 2 if the register LoopTxTwoCellEn = 1. If receive slave mode is selected, this signal is a tristate output. The S/UNI APEX drives LTPA 1 LTCLK after LTADR[5:0] matches the programmed LoopTxSlaveAddr register. A logical high indicates that at least one cell is available for transmission. LTPA is sampled/updated/Hi-Z'd on the rising edge of LTCLK.
Input R23 (Master) Tri-state (Slave)
LTENB
Output T24 (Master) Input (Slave)
Loop Transmit Enable. LTENB indicates cell transfers to UTOPIA and SCI-PHY devices. The device is selected via a match on LTADR[11:0] when LTENB is last sampled high. This pin is in Hi-Z when the loop transmit interface is not enabled. If transmit master mode is selected, this signal is an output. LTENB is held low for the duration of the cell transfer. If receive slave mode is selected, this signal is an input. LTENB is sampled/updated on the rising edge of LTCLK.
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
Pin Name LTSX
Type Output
Pin No.
U25
Function Loop Transmit Start of Transfer. LTSX is asserted by the S/UNI APEX during the first cycle of a data block transfer. LTSX assertion will coincide with the port address prepend, if the cell being transferred has a prepended port address. Required only during Any-PHY mode. Should be left unconnected during UTOPIA modes. LTSX is updated on the rising edge of LTCLK. Loop Transmit Start of Cell. LTSOP marks the start of cell on the LTDAT[15:0] data bus. LTSOP is driven high when the first word of the cell (excluding address prepend) is present on the LTDAT[15:0] stream. LTSOP is asserted for each cell. In transmit master mode, the signal is always driven. In receive slave mode, this signal is driven 1 LTCLK after LTENB is asserted. LTSOP is updated/Hi-Z'd on the rising edge of LTCLK.
LTSOP
Output T23 (Master) Tri-state (Slave)
LTDAT[0] .. LTDAT[15]
Output T26 (Master) R24 Tri-state (Slave)
R25 R26 P24 P25 N25 N24 N23 M26 M25 M24 L26 M23 L25 L24
Loop Transmit Data. LTDAT[15:0] carries the data block transfers to the physical layer devices. In 8 bit mode, only LTDAT[7:0] are valid. In transmit master mode, the entire bus is always driven. In receive slave mode, this bus is driven 1 LTCLK after LTENB is asserted. Pull up/downs are required for the entire bus, regardless of whether the bus is in 8 or 16 bit mode. LTDAT[15:0] is updated/Hi-Z'd on the rising edge of LTCLK.
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25
PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
Pin Name LTPRTY
Type
Pin No.
Function Loop Transmit Parity. This signal provides programmable odd/even parity of the LTDAT[15:0] bus. In transmit master mode, the signal is always driven. In receive slave mode, this signal is driven 1 LTCLK after LTENB is asserted. LTPRTY is updated/Hi-Z'd on the rising edge of LTCLK.
Output V26 (Master) Tri-state (Slave)
9.3
WAN Any-PHY Receive Master/Transmit Slave Interface (25 Signals) Pin Name WRCLK Type Input Pin No.
T3
Function WAN Receive Clock. WRCLK is used to transfer data blocks in the receive direction across the AnyPHY interface. WRCLK must cycle at a 52 MHz or lower instantaneous rate.
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
Pin Name WRPA
Type
Pin No.
Function WAN Receive Packet Available. WRPA indicates cell availability. This pin is in Hi-Z when the WAN receive interface is not enabled. If master mode is selected, the selected PHY device drives WRPA with the cell availability status N WRCLK cycles after WRADR[2:0] matches the PHY device address. If the PHY device is a UTOPIA device, N=1. If the PHY device is an Any-PHY device, N=2. Assertion of WRPA indicates that at least one entire cell is available. If slave mode is selected, this signal is an output and the S/UNI APEX plays the roll of a single port UTOPIA L2 slave device driving the WRPA when the WRADR matches the programmed WANRxSlaveAddr register. A logical high indicates that the S/UNI APEX is capable of accepting at least one cell. WRPA is sampled/updated/Hi-Z'd on the rising edge of WRCLK.
Input U1 (Master) Tri-state (Slave)
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
Pin Name WRENB
Type
Pin No.
Function WAN Receive Enable. The active low receive enable (WRENB) output is used to initiate the transfer of a data block from the selected Physical layer device to the S/UNI APEX. This pin is in Hi-Z when the WAN receive interface is not enabled. If master mode is selected, this signal is an output and the start of block transfer must occur 1 or 2 WRCLK cycles after device selection occurs. Device selection occurs when the selected device address is placed on WRADR[2:0] with WRENB held high followed by WRENB low in the next WRCLK period. WRENB is held low for M cycles where M is the number of 8 or 16-bit words in the block transfer. If slave mode is selected, this signal is an input and WRDAT[15:0] word is accepted coincident with WRENB being sampled. WRENB is sampled/updated on the rising edge of WRCLK.
Output T2 (Master) Input (Slave)
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
Pin Name WRADR[0] .. WRADR[2]
Type
Pin No.
Function WAN Receive Address. The WRADR[2:0] signals are used to address up to four Physical layer devices for the purposes of polling and device selection. This pin is in Hi-Z when the WAN receive interface is not enabled. If UL2 or Any-PHY receive master mode is selected, this bus is an output. WRADR[2:0] selects a device for polling by applying the device address N WRCLK cycles prior to sampling WRPA. If the PHY device selected is a UTOPIA device, N=1. If the PHY device selected is an Any-PHY device, N=2. When supporting multiple PHYs, WRADR will insert 1 NULL address between address changes. If UL1 master mode is selected, this bus is driven to a high NULL address. WRADR[2:0] selects a device to transfer a data block when the WRENB is last sampled high. The start of data block transfer must occur 1 or 2 WRCLK cycles after device selection occurs. WRADR[2:0] = 7 hex is used as the NULL address. No PHY device can match the NULL address. If slave mode is selected, this signal is an input and the S/UNI APEX plays the roll of a single port UTOPIA L2 slave device driving the WRPA 1 WRCLK after the WRADR[1:0] matches the programmed WANRxSlaveAddr register, and WRADR[2] is zero. WRADR[2:0] is sampled/updated on the rising edge of WRCLK.
Output R2 (Master) R3
T1
Input (Slave)
WRSX
Input
V1
WAN Receive Start of Transfer. WRSX is asserted by the selected PHY device during the first cycle of a data block transfer coinciding with the port address prepend. WRSX is ignored during cell transfers from UTOPIA or SCI-PHY devices. WRSX is updated on the rising edge of WRCLK.
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29
PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
Pin Name WRSOP
Type Input
Pin No.
T4
Function WAN Receive Start of Packet . WRSOP marks the start of the cell on the WRDAT[15:0] bus. When WRSOP is high, the first data word of the cell is present on the WRDAT[15:0] stream. If the selected device is an Any-PHY device, the WRSOP cycle will be preceeded by the WRSX cycle marking the AnyPHY port address transfer cycle. WRSOP is considered valid only when the WRENB signal is low. WRSOP becomes high impedance upon sampling WRENB high or if no physical layer device was selected for transfer. WRSOP is sampled on the rising edge of WRCLK.
WRDAT[0] .. WRDAT[15]
Input
U3 V2 W1 U4 V3 W2 Y1 W3 Y2 AA1 Y3 AA2 AB1 Y4 AA3 AB2
WAN Receive Data. WRDAT[15:0] carries the transfer block words that have been read from the physical layer device to the S/UNI APEX internal cell buffers. All 16 bits are used in 16-bit mode, only the first 8 bits WRDAT[7:0] are valid in 8-bit mode. The WRDAT bus is considered valid only when the WRENB signal was low N cycles previous. WRDAT is expected to become high impedance N WRCLK cycles after sampling WRENB high or upon completion of a data block transfer. If the PHY device selected is a UTOPIA device, N=1. If the PHY device selected is an Any-PHY device, N=2. WRDAT[15:0] is sampled on the rising edge of WRCLK.
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30
PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
Pin Name WRPRTY
Type Input
Pin No.
U2
Function WAN Receive Parity. WRPRTY provides programmable odd/even parity of the WRDAT[15:0] bus. The WRPRTY signal is considered valid only when the WRENB signal was low N cycles previous. If the PHY device selected is a UTOPIA device, N=1. If the PHY device selected is an Any-PHY device, N=2. WRPRTY is expected to become high impedance N WRCLK cycles after sampling WRENB high. A parity error is indicated by a status bit and a maskable interrupt. WRPRTY is sampled on the rising edge of WRCLK.
9.4
WAN Any-PHY Transmit Master/Receive Slave Interface (25 Signals) Pin Name WTCLK Type Input Pin No.
AD20
Function WAN Transmit Clock. WTCLK is used to transfer data blocks in the transmit direction across the AnyPHY interface. WTCLK must cycle at a 52 MHz or lower instantaneous rate.
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
Pin Name
WTADR[0] .. WTADR[2]
Type Output (Master) Input (Slave)
Pin No.
AE20 AD19 AF20
Function WAN Transmit Address. The WTADR[2:0] signals are used to address up to four logical channels for the purposes of polling. This pin is in Hi-Z when the WAN transmit interface is not enabled. If master mode is selected, these signals are outputs. WTADR[2:0] selects a logical channel for polling by applying the logical channel address N WTCLK cycles prior to sampling WTPA. If the PHY devices are UTOPIA devices, N=1. If the PHY devices are Any-PHY devices, N=2. , WTADR will insert 1 NULL address between address changes For Any-PHY transmit master, WTADR[1:0] corresponds to the PORTID[1:0] fields in the AnyPHY address word prepend format. WTADR[2:0] = 7 hex is used as the NULL address. No PHY device can match the NULL address. For UTOPIA L2 transmit master, WTADR[2:0] signals are also used for cell transfer PHY selection to UTOPIA compliant PHY devices. WTADR[2:0] selects a device to transfer a data block to when the WRENB is last sampled high. For UTOPIA L1 transmit master, WTADR[1:0] contains the value of the WANTxSlaveAddr register. WTADR[2] is held low. If UTOPIA L2 receive slave mode is selected, these signals are inputs and the S/UNI APEX plays the roll of a single port UTOPIA L2 slave device driving the WTPA 1 WTCLK after the WTADR matches the programmed WANTxSlaveAddr register. WTADR[2:0] is sampled/updated on the rising edge of WTCLK.
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
Pin Name WTPA
Type Input (Master) Tri-state (Slave)
Pin No.
AD21
Function WAN Transmit Packet Available. WTPA indicates cell availability. This pin is in Hi-Z when the WAN transmit interface is not enabled. If master mode is selected, this signal is an input. The PHY device whose address or address range matches WTADR[2:0] drives the WTPA signal with the transmit FIFO availability status of the selected logical channel N WTCLK cycles after the match. If the PHY devices are UTOPIA devices, N=1. If the PHY devices are Any-PHY devices, N=2. Assertion of WTPA indicates that at least one entire cell buffer is available in that logical channel. If slave mode is selected, this signal is a tri-state output and the S/UNI APEX plays the roll of a single port UTOPIA L2 slave device driving the WTPA when the WTADR matches the programmed WANTxSlaveAddr register. A logical high indicates that at least one cell is available for transmission. WTPA is sampled/updated/Hi-Z'd on the rising edge of WTCLK.
WTENB
Output (Master) Input (Slave)
AC20
WAN Transmit Enable. WTENB indicates cell transfers to UTOPIA and SCI-PHY devices. The device is selected via a match on WTADR[2:0] when WTENB is last sampled high. This pin is in Hi-Z when the WAN transmit interface is not enabled. If master mode is selected, this signal is an output. If slave mode is selected, this signal is an input. WTENB is held low for the duration of the cell transfer. WTENB is sampled/updated on the rising edge of WTCLK.
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
Pin Name WTSX
Type Output
Pin No.
AE21
Function WAN Transmit Start of Transfer. WTSX is asserted by the S/UNI APEX during the first cycle of a data block transfer. WTSX assertion will coincide with the port address prepend, if the cell being transferred has a prepended port address. Required only during Any-PHY mode. WTSX is updated on the rising edge of WTCLK. WAN Transmit Start of Packet. WTSOP marks the start of cell on the WTDAT[15:0] data bus. WTSOP is driven high when the first word of the cell (excluding address prepend) is present on the WTDAT[15:0] stream. WTSOP is asserted for each cell. In transmit master mode, the signal is always driven. In receive slave mode, this signal is driven 1 WTCLK after WTENB is asserted. WTSOP is updated/Hi-Z'd on the rising edge of WTCLK.
WTSOP
Output (Master) Tri-state (Slave)
AC19
WTDAT[0] .. WTDAT[15]
Output (Master) Tri-state (Slave)
AE22 AF23 AC21 AD22 AE23 AF24 AC24 AD26 AC25 AB24 AA23 AC26 AB25 AA24 Y23 AA25
WAN Transmit Data. WTDAT[15:0] carries the data block transfers to the physical layer devices. In 8 bit mode, only WTDAT[7:0] are valid. In 8/16bit transmit master mode, the entire bus is always driven. In receive slave mode, this bus is driven 1 WTCLK after WTENB is asserted Pull up/downs are required for the entire bus, regardless of whether the bus is in 8 or 16 bit mode. WTDAT[15:0] is updated/Hi-Z'd on the rising edge of WTCLK.
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
Pin Name WTPRTY
Type Output (Master) Tri-state (Slave)
Pin No.
AF21
Function WAN Transmit Parity. This signal provides programmable odd/even parity of the WTDAT[15:0] bus. In transmit master mode, the signal is always driven. In receive slave mode, this signal is driven 1 WTCLK after WTENB is asserted. WTPRTY is updated/Hi-Z'd on the rising edge of WTCLK.
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
9.5
Context Memory Synchronous SSRAM Interface (60 Signals) Pin Name CMD[0] .. CMD[33] Type BiDi Pin No.
A24 B23 C22 D21 A23 B22 C21 A22 B21 C20 D19 A21 B20 C19 A20 B19 C18 D17 A19 B18 C17 A18 D16 B17 C16 B16 D15 A16 C15 B15 A15 C14 B14 B13
Function Context Memory SSRAM Data. The bi-directional SSRAM data bus pins interface directly with the synchronous SSRAM data ports. The S/UNI APEX presents valid data on the CMD[33:0] pins upon the rising edge of SYSCLK during write cycles. CMD[33:0] is Hi-Z'd on the rising edge of SYSCLK for read cycles. CMD[33:0] is sampled/updated/Hi-Z'd on the rising edge of SYSCLK.
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36
PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
Pin Name CMP[0] .. CMP[1]
Type BiDi
Pin No.
D24 C23
Function Context Memory SSRAM Data Parity. The SSRAM parity pins provide parity protection over the CMD[33:0] data bus. CMP[0] completes the odd parity for CMD[16:0] CMP[1] completes the odd parity for CMD[33:17] CMP[1:0] has the same timing as CMD[33:0]. The CMP[1:0] may be unconnected if parity protection is not required. CMP[1:0] is sampled/updated/Hi-Z'd on the rising edge of SYSCLK.
CMA[0] .. CMA[19]
Output
K25 L23 J26 K24 J25 H26 K23 J24 H25 G26 H24 G25 F26 H23 G24 F25 E26 E25 F23 E24
Context Memory SSRAM Address. The SSRAM address outputs identify the SSRAM locations accessed. The maximum size of the SSRAM is 4M bytes but smaller configurations are possible depending on the number of ports and VCs supported by the particular application. In the case where smaller SSRAM sizes are used the most significant bits of CMA[19:0] may be left unconnected. CMA[19:0] is updated on the rising edge of SYSCLK.
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37
PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
Pin Name CMAB[17] .. CMAB[18]
Type Output
Pin No.
F24 D26
Function Context Memory SSRAM Address Bar. These active low address outputs are provided to enable glueless connection to 4 banks of ZBT SSRAM, or 2 banks of Late Write SSRAM. In ZBT SSRAM mode, these bits are the inverse of CMA[18:17]. In Late Write SSRAM mode, CMAB[17] is the chip enable bar for even addresses, CMAB[18] is the chip enable bar for odd addresses. CMAB[18:17] is updated on the rising edge of SYSCLK.
CMRWB
Output
C26
Context Memory SSRAM Read Write Bar. CMRWB determines the cycle type when CMCEB is asserted low. When CMRWB is asserted high, the cycle type is a read. When CMRWB is asserted low, the cycle type is a write. CMRWB is updated on the rising edge of SYSCLK. Context Memory SSRAM Chip Enable Bar. CMCEB initiates an access. When CMCEB is asserted low, the external SSRAM samples the address and CMRWB asserted by the S/UNI APEX. CMCEB is updated on the rising edge of SYSCLK.
CMCEB
Output
D25
9.6
Cell Buffer SDRAM Interface (52 Signals) Pin Name CBCSB Type Output Pin No.
AE15
Function Cell Buffer SDRAM Chip Select Bar. CBCSB, CBRASB, CBCASB, and CBWEB define the command being sent to the SDRAM. CBCSB is updated on the rising edge of SYSCLK. Cell Buffer SDRAM Row Address Strobe Bar. CBCSB, CBRASB, CBCASB, and CBWEB define the command being sent to the SDRAM. CBRASB is updated on the rising edge of SYSCLK.
CBRASB
Output
AF15
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
Pin Name CBCASB
Type Output
Pin No.
AC14
Function Cell Buffer SDRAM Column Address Strobe Bar. CBCSB, CBRASB, CBCASB, and CBWEB define the command being sent to the SDRAM. CBCASB is updated on the rising edge of SYSCLK. Cell Buffer SDRAM Write Enable Bar. CBCSB, CBRASB, CBCASB, and CBWEB define the command being sent to the SDRAM. CBWEB is updated on the rising edge of SYSCLK. Cell Buffer SDRAM Address. The Cell Buffer SDRAM address outputs identify the row address (CBA[11:0]) and column address (CBA[7:0]) for the locations accessed. CBA[11:0] is updated on the rising edge of SYSCLK.
CBWEB
Output
AD14
CBA[0] .. CBA[11]
Output
AC15 AE16 AD16 AE17 AC16 AF18 AD17 AE18 AF19 AC17 AD18 AE19 AD15 AF16
CBBS[0] .. CBBS[1]
Output
Cell Buffer SDRAM Bank Select. The bank select signal determines which bank of a dual/quad bank Cell Buffer SDRAM chip is active. CBBS[1:0] is generated along with the row address when CBRASB is asserted low. CBBS is updated on the rising edge of SYSCLK. Cell Buffer SDRAM Input/Output Data Mask. The data mask changes state from high to low when the SDRAM is enabled. These pins are held low during normal operation CBDQM is updated on the rising edge of SYSCLK.
CBDQM[0] .. CBDQM[1]
Output
AE13 AE14
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39
PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
Pin Name CBDQ[0] .. CBDQ[31]
Type BiDi
Pin No.
AF3 AE4 AD5 AC6 AF4 AE5 AD6 AC7 AE6 AD7 AC8 AF6 AE7 AD8 AF7 AE8 AD9 AC10 AF8 AE9 AD10 AF9 AC11 AE10 AD11 AE11 AC12 AF11 AD12 AE12 AF12 AD13
Function Cell Buffer SDRAM Data. The bi-directional Cell Buffer SDRAM data bus pins interface directly with the Cell Buffer SDRAM data ports. The Cell Buffer SDRAM is accessed as a burst of 32-bit long words. CBDQ[31:0] is updated/Hi-Z'd on the rising edge of SYSCLK.
9.7
Microprocessor Interface (44 Signals) Pin Name BCLK Type Input Pin No.
C1
Function Bus Clock. This clock is the bus clock for the microprocessor interface. BCLK must cycle at 66 MHz or lower instantaneous rate.
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40
PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
Pin Name AD[0] .. AD[31]
Type BiDi
Pin No.
C13 D13 A12 C12 A11 D12 B11 C11 B10 D11 A9 C10 B9 A8 D10 C9 B8 A7 C8 B7 A6 D8 C7 B6 A5 C6 B5 A4 D6 C5 B4 A3 F2
Function Multiplexed Address Data Bus. The multiplexed address data bi-directional bus AD[31:0] is used to connect the S/UNI APEX to the microprocessor. During the address phase when ADSB = 0, AD[1:0] are ignored as all transfers are 32 bits wide. AD[31:0] is sampled/updated/Hi-Z'd on the rising edge of BCLK.
ADSB
Input
Address Status. This signal is active-low and indicates a long-word address is present on the address/data bus AD[31:2]. Address space used is 0->4K. Attempts to access above this address space is prohibited. ADSB is sampled on the rising edge of BCLK.
CSB
Input
E1
Active Low Chip Select. The chip select (CSB) signal is low during the address cycle (as defined by ADSB) of S/UNI APEX register accesses. CSB is sampled on the rising edge of BCLK.
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Pin Name WR
Type Input
Pin No.
F3
Function Write/Read. The write/read (WR) signal is evaluated when the ADSB and CSB are sampled active by S/UNI APEX. The BUSPOL input pin controls the polarity of this input. WR is sampled on the rising edge of BCLK. Burst Bar. This signal is evaluated when the ADSB and CSB are sample active by S/UNI APEX. When low, this signal indicates that the current access is a burst access (and the BLAST input can be used to detect the end of the transaction). BURSTB is sampled on the rising edge of BCLK. Burst Last. This signal indicates the last data access of the transfer. When the BURSTB input is low, the BLAST input is driven active during the last transfer of a transaction (even if the transaction is one word in length). When the BURSTB input is high, the BLAST input is ignored by S/UNI APEX. The BUSPOL input pin controls the polarity of this input. BLAST is sampled on the rising edge of BCLK. Ready Bar. This signal is asserted low by S/UNI APEX when the data on the AD[31:0] bus has been accepted (for writes), or when the data on the AD[31:0] is valid (for reads). This signal may be used by S/UNI APEX to delay a data transaction. This output is Hi-Z'd one clock cycle after an S/UNI APEX access, allowing multiple slave device to be tied together in the system. This output should be pulled up externally. READYB is updated on the rising edge of BCLK.
BURSTB
Input
E2
BLAST
Input
D1
READYB
Tri-state
F4
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Pin Name BTERMB
Type Tri-state
Pin No.
E3
Function Burst Terminate Bar. This signal is asserted low by S/UNI APEX when a data transfer has reached the address boundary of a burstable range. Attempts to extend the burst transfer after this signal is asserted will be ignored. This output is Hi-Z'd one clock cycle after an S/UNI APEX access, allowing multiple slave device to be tied together in the system. This output should be pulled up externally. BTERMB is updated on the rising edge of BCLK. Write Done Bar. This signal is asserted low by S/UNI APEX when the most recent write access to internal registers is complete. This signal may be used by external circuitry to delay the issuance of a write operation address cycle until S/UNI APEX can accept write data. This signal is only needed in systems where the READYB output cannot be used to delay a write data transaction (due to microprocessor restrictions). WRDONEB is updated on the rising edge of BCLK. Active Low Open-Drain High Priority Interrupt. This signal goes low when an S/UNI APEX high priority interrupt source is active and that source is unmasked. The S/UNI APEX may be enabled to report many alarms or events via interrupts. INTHIB becomes high impedance when the interrupt is acknowledged via an appropriate register access. INTHIB is an asynchronous signal. Active Low Open-Drain Low Priority Interrupt. This signal goes low when an S/UNI APEX low priority interrupt source is active and that source is unmasked. The S/UNI APEX may be enabled to report many alarms or events via interrupts. INTLOB becomes high impedance when the interrupt is acknowledged via an appropriate register access. INTLOB is an asynchronous signal.
WRDONEB
Output
D2
INTHIB
OD
C4
INTLOB
OD
D3
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Pin Name BUSPOL
Type Input
Pin No.
E4
Function Bus Control Polarity. This signal indicates the polarity of the WR and BLAST inputs to S/UNI APEX. When high, the BLAST pin is active high (high indicates the last word of the burst) and the WR pin is active low (low indicates write). When low, the BLAST pin is active low (low indicates the last word of the burst) and the WR pin is active high (high indicates write). BUSPOL is sampled on the rising edge of BCLK.
9.8
General (9 signals) Pin Name RSTB Type Input Pin No.
AA4
Function Reset Bar. This signal provides an asynchronous S/UNI APEX reset. RSTB is a Schmitt triggered input with an internal pull-up resistor. Output Enable OE is an active high signal, which allows all of the outputs of the device to operate in their functional state. When this signal is low, all outputs of the S/UNI APEX are Hi-Z'd, with the exception of TDO. OE has an internal pull up resistor. System Clock. This clock is the master clock for the S/UNI APEX device. All non-Any-PHY or microprocessor interface related internal synchronous logic is timed to this signal. SYSCLK must cycle at a 80 MHz or lower instantaneous rate. External SSRAM and SDRAM devices share this clock and must have clocks aligned within 0.2ns skew of the clock seen by the S/UNI APEX device. This clock must be stable prior to deasserting RSTB 0->1.
OE
Input
AC1
SYSCLK
Input
B12
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Pin Name NC
Type
Pin No.
AB4 AC5 AB23 E23 D22 D5
Function No Connect. These balls are not connected to the die.
9.9
JTAG & Scan Interface (7 Signals) Pin Name TCK Type Input Pin No.
AD1
Function Test Clock. This signal provides timing for test operations that are carried out using the IEEE P1149.1 test access port. Test Mode Select. This signal controls the test operations that are carried out using the IEEE P1149.1 test access port. TMS is sampled on the rising edge of TCK. TMS has an integral pull-up resistor. Test Data Input. This signal carries test data into the S/UNI APEX via the IEEE P1149.1 test access port. TDI is sampled on the rising edge of TCK. TDI has an integral pull-up resistor. Test Data Output. This signal carries test data out of the S/UNI APEX via the IEEE P1149.1 test access port. TDO is a tri-state output, which is inactive except when scanning of data is in progress. TDO is updated/Hi-Z'd on the falling edge of TCK. Active low Test Reset. This signal provides an asynchronous S/UNI APEX test access port reset via the IEEE P1149.1 test access port. TRSTB is a Schmitt triggered input with an integral pull-up resistor. Note that when not being used, TRSTB must be connected to the RSTB input.
TMS
Input
AC2
TDI
Input
AB3
TDO
Tri-state
AD4
TRSTB
Input
AC3
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Pin Name SCANEN
Type Input
Pin No.
AD23
Function Scan Enable This signal enables the internal scan logic for production testing. Should be held to its inactive low state. Scan Mux This signal is connected directly to the control of the internal scan muxes. Should be held to its inactive high state.
SCANMB
Input
AC22
9.10 Power Pin Name VDD Type Power Pin No.
AC4 AC9 AC13 AC18 AC23 AD3 AD24 AE2 AE25 B2 B25 C3 C24 D4 D9 D14 D18 D23 J23 J4 N4 P23 V4 V23
Function The pad ring power pins should be connected to a well de-coupled +3.3 V DC.
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Pin Name PCH
Type Power
Pin No.
G4 L4 R4 W4 AF5 AF10 AF17 AF22 AB26 U26 K26 G23 D20 A17 A10 D7 A1 A2 A13 A14 A25 A26 B1 B3 B24 B26 C2 C25 N1 N26 P1 P26 AD2 AD25 AE1 AE24 AE3 AE26 AF1 AF2 AF13 AF14 AF25 AF26
Function The core power pins should be connected to a welldecoupled +2.5 V DC.
VSS
Ground
The pad ring and core ground pins should be connected to GND.
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10
FUNCTIONAL DESCRIPTION This section describes the function of each entity in the S/UNI APEX block diagram. In this document, receive and transmit are used with the S/UNI APEX as the frame of reference. For example, receive is used to describe data paths which are coming into the device.
10.1 Any-PHY Interfaces The S/UNI APEX Interface are Any-PHY compliant 8/16-bit master/slave interface for both Loop and WAN ports. The loop and WAN interfaces are configured independently. Both interfaces are fully compatible with the following Any-PHY options: * Any-PHY master. * UTOPIA L2 master (UL2M). * UTOPIA L1 master (UL1M). * UTOPIA L2 slave (UL2S). 10.1.1 Receive Interface The S/UNI APEX requires a 16-bit Ingress Connection Identifier (ICI) to be received with every cell. The ICI uniquely identifies the VCC or VPC. The ICI can be received within the HEC/UDF field (16bit I/F only), as a user prepend, or encoded within the VPI/VCI field. In Any-PHY mode, an address prepend is expected to be in the first word/byte of every cell. Inclusion of optional words/bytes are statically configured for the interface. The Receive Cell Transfer Format is shown in Figure 3 and Figure 4. Figure 3
Word 0 (Any-PHY only) Word 1 (Optional) Word 2 Word 3 Word 4 (Optional) Word 5
- 16bit Receive Cell Transfer Format Bits 15-8 Address Prepend User Prepend H1 H3 HEC/UDF PAYLOAD1 PAYLOAD2 H2 H4 Bits 7-0
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Word 6
PAYLOAD3
* * *
PAYLOAD4
* * *
Word 28
PAYLOAD47 - 8-bit Receive Cell Transfer Format Bits 7-0
PAYLOAD48
Figure 4
Byte 0 (Any-PHY only) Byte 1 (Required) Byte 2 (Required) Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 (Optional) Byte 8
Address Prepend
User Prepend[15:8] User Prepend[7:0] H1 H2 H3 H4 H5 PAYLOAD1
* * *
Byte 55
PAYLOAD48
The Loop and WAN receive master mode interface supports per-device or perport RPA (Receive Packet Available) status polling via round robin polling address enabling support for up to 32 loop or 4 WAN devices and/or ports. Polling ceases once a device or port has been identified as having a cell available. Polling recommences on the following address that was serviced. Since the S/UNI APEX requires a unique 16-bit ICI with every cell, knowledge of which polling addresses are associated with devices and which are associated with ports is not required.
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If UL2M or Any-PHY, and the number of ports connected is less than 32 (loop) or 4 (WAN), there is an option of limiting the polling range; thereby providing optimal polling efficiency. The UL1M is effectively a UL2M without address polling, but retains the port selection handshake. Hence a single external UL2S may be connected to the S/UNI APEX UL1M transmit interface. If Any-PHY, the S/UNI APEX expects the Any-PHY slave device to act as a proxy for its internal ports. The S/UNI APEX places no restrictions on the number of internal ports within an Any-PHY slave device. Since the polling is tied to the data transfer, both the WAN and loop Any-PHY receive interface is capable of mixing prepend enabled UL2 and Any-PHY slaves on the same bus with some external glue logic. If UL2S, the S/UNI APEX operates as a single port UTOPIA L2 transmit slave port. The address pins become inputs and can be configured to respond to any port identifier from 0 to 31 for loop, and 0 to 3 for WAN. Table 4 Mode Any-PHY Master UTOPIA L2 Master UTOPIA L1 Master UTOPIA L2 Slave 10.1.2 Transmit Interface The Transmit Cell Transfer Format is shown in Figure 5 and Figure 6. Word/byte 0 is required for cell transfers to Any-PHY slaves. The address prepend is the S/UNI APEX port id associated with the transmit queue in which the cell was enqueued. The unused bits in the address prepend are reserved and devices should not rely on the content. Optional word 1 or bytes {1,2} enables the prepending of a 16-bit switch tag. Optional word 2 or bytes {3,4} enables the prepending of a 16-bit Egress Connection Identifier (ECI). Both the Switch tag and the Egress Connection Identifier are sourced on a per-VC basis from VC context. The S/UNI APEX also maps the ECI tag to the HEC/UDF field (word 5) for 16-bit transfer. Word 5 or byte 9 is optional. The S/UNI APEX supports optional VPI and/or VCI mapping, selectable on a per VC basis. Inclusion of optional words is statically configurable for the interface. Selection of the usage of the included optional words is configurable on a per-VC basis. On a - Number of Ports Supported, Receive Interface Loop (8/16bit) 32 32 1 1 of 32 WAN (8/16bit) 4 4 1 1 of 4
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per-VC basis, either mapping of switch tag and/or ECI or mapping of the switch tag and VPI, or of VPI and VCI is supported. If optional words 2, and/or 5 are included on the interface, they contain the original ICI if ECI remapping is not supported for the VC. If optional word 1 is included on the interface, it is defined as a reserved field for those VCs that are not mapping the switch tag. Figure 5
Word 0 (Any-PHY only) Word 1 (Optional) Word 2 (Optional) Word 3 Word 4 Word 5 (Optional) Word 6 Word 7
- 16-bit Transmit Cell Transfer Format Bits 15-8 Bits 7-0
Address Prepend Loop I/F: {4 MSB reserved, PortID[11:0]} WAN I/F: {14 MSB reserved, PortID[1:0]} Switch Tag Prepend ECI Prepend H1 H3 ECI Prepend PAYLOAD1 PAYLOAD3
* * *
H2 H4
PAYLOAD2 PAYLOAD4
* * *
Word 29
PAYLOAD47
PAYLOAD48
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Figure 6
Byte 0 (Any-PHY only)
- 8-bit Transmit Cell Transfer Format Bits 7-0 Address Prepend Loop I/F: {PortID[7:0]} WAN I/F: {6 MSB reserved, PortID[1:0]} Switch Tag Prepend[15:8] Switch Tag Prepend[7:0] ECI Prepend[15:8] ECI Prepend[7:0] H1 H2 H3 H4 ECI Prepend[7:0] PAYLOAD1
* * *
Byte 1 (Optional) Byte 2 (Optional) Byte 3 (Optional) Byte 4 (Optional) Byte 5 Byte 6 Byte 7 Byte 8 Byte 9 (Optional) Byte 10
Byte 57
PAYLOAD48
In the loop interface Any-PHY mode, 16bit, per-port status polling is supported via a 12 bit polling address bus and a single transmit packet available input enabling up to 2048 port polling. 8-bit loop interface is limited to an 8-bit polling address, enabling 256 port polling. The loop interface polling is completely independent of the data transfer. In the WAN interface Any-PHY mode, 8/16bit, per-port status polling is supported via a 3 bit polling address bus and a single transmit packet available input enabling up to 4 port polling. The WAN interface polling ceases once a device or port has been identified as having a cell available. WAN polling recommences on the following address that was serviced. Since the polling is tied to the data
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transfer, the WAN transmit interface is capable of mixing prepend enabled UL2 and Any-PHY slaves on the same bus with some external glue logic. In UL2M, loop interface port selection is done via the 6 lower bits of the 12-bit polling address bus, supporting up to 32 ports. WAN interface port selection is done via the 3-bit polling address bus, supporting up to 4 ports. Details of the polling algorithm for the loop and WAN interface can be found in the loop port scheduler and WAN port scheduler section respectively. The UL1M is effectively a UL2M without address polling, but retains the port selection handshake. Hence a single external UL2S may be connected to the S/UNI APEX UL1M transmit interface. Specific only to the WAN UL1M mode, port address is presented with a programmable value , giving the option of port sparing. In slave mode, the transmit interface operates as a single port UTOPIA L2 receive slave port. The 6 lower bits of the 12-bit loop polling address, or the entire 3 bits of the WAN polling address become inputs. The loop interface can be configured to respond to any port identifier from 0 to 31. The WAN interface can be configured to respond to any port identifier from 0 to 3. Table 5 Mode Any-PHY Master UTOPIA L2 Master UTOPIA L1 Master UTOPIA L2 Slave - Number of Ports Supported, Transmit Interface Loop (8 bit) 256 32 1 (no sparing) 1 of 32 Loop (16 bit) 2048 32 1 (no sparing) 1 of 32 WAN (8 bit) 4 4 1 (4 sparing) 1 of 4 WAN (16bit) 4 4 1 (4 sparing) 1 of 4
10.2 Loop Port Scheduler The S/UNI APEX loop port scheduler provides weighted interleaved round robin scheduling of up to 2k Any-PHY addresses. To achieve fairness among the 2k ports and to avoid wasted polling opportunities, the selection of what ports to poll is based on what ports have transmit data queued and have a high probability of being able to accept the cell. The scheduler has 128 polling sequences and 8 different weighting groups. Software configures the number of polling sequences a port should participate in by assigning a 3-bit logarithmic weight value and a 7-bit sequence number to
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each port. The scheduler maintains a 7-bit polling sequence number and increments it after each scheduler polling cycle. During a scheduler polling cycle each of the 2k ports is evaluated. The port will be polled if the following conditions are met: * * the port's transmit data queue is not empty the n LSB's of the scheduler poll sequence number match the n LSB's of the port's sequence number (n is equal to the port's weight). For ports with a weight of zero, this compare is ignored. For ports with a weight of one, then only the LSB is compared. For ports with a weight of seven, then the entire seven bits are compared.
To maintain even distribution of ports within the same weight class, software must assign sequence numbers to ports evenly across the 128 polling sequences. This sequence number need only be changed when a port's weight is changed or the distribution ports in a weight group becomes significantly unbalanced due to port deactivations. Sequence numbers and weights may be modified at any time. The logarithmic weights are set so that lower speed ports are evaluated less often relative to higher speed ports. The following formula show relationship between the 3 bit logarithmic weights (lw) and the assigned relative throughput weight (rw) in the case where the aggregate throughput of all the ports is greater than the available bandwidth: rw = 2
(7-lw)
The maximum polling rate for any given port is dictated by the number of active ports. In Any-PHY mode, if only one port is active for all 2k ports (port's transmit data queue is not empty), the maximum polling rate is governed by the following formula: Max. polling rate = f(SYSCLK) / (64 * 2lw) The equivalent equation for UL2M mode is the following: Max. polling rate = f(SYSCLK) / 2 10.3 Wan Port Scheduler The WAN port scheduler operates between the queue engine and the multichannel WAN port FIFO. The S/UNI APEX WAN port scheduler provides weighted interleaved round robin scheduling of up to 4 WAN ports. The dynamic range of the weights is 8 to 1.
lw
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The scheduler has 8 polling sequences and 4 different weighting groups. Port weighting is achieved by configuring the number of polling sequences a port should participate in. This configuration is done by assigning a 2-bit logarithmic weight value and a 3-bit sequence number to each port. Software assigns the 2bit weight value, and the hardware always maps the 4 ports to the following sequence numbers: port 0 is assigned 000, port 1 is assigned 010, port 2 is assigned 101, and port 3 is assigned 111. The scheduler maintains a 3-bit polling sequence number and increments it after each scheduler polling cycle. During a scheduler polling cycle each of the 4 ports is evaluated. The port will be selected for transmission if the following conditions are met: * * the port's transmit data queue is not empty the n LSB's of the scheduler poll sequence number match the n LSB's of the port's sequence number (n is equal to the port's weight). For ports with a weight of zero, this compare is ignored and assumed successful. For ports with a weight of one, only the LSB is compared. For ports with a weight of two, only the first two LSBs are compared. For ports with a weight of three, all three bits are compared. the S/UNI APEX internal WAN FIFO for the port is not full
*
The logarithmic weights are set so that lower speed ports are evaluated less often relative to higher speed ports. The following formula shows relationship between the logarithmic weights values and the resulting linear relative weight. rw = 2
(3-lw)
If port 0 were assigned a weight of 0, port 1 a weight of 1, port 2 a weight of 2, and port 3 a weight of 3, and all the ports had data to send, and none of the WAN FIFOs were full, then cells would be transmitted in the following order:
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Table 6
- Example WIRR Transmission Sequence Sequence Number 000 001 010 011 100 101 110 111 Ports Transmitted 0,1 0,2 0,1 0 0,1 0,2 0,1 0,3
The above example was constrained by several conditions under which the queue engine WAN interface bandwidth was the transmission bottleneck. In the WAN transmit datapath, there are actually three places where a transmission bottleneck can occur: the queue engine's WAN interface bandwidth, the AnyPHY bus, and the actual physical lines. If the queue engine's WAN interface bandwidth is the bottleneck, then the WIRR WAN scheduler will determine the transmission order. In this case, the queue engine's WAN interface does not have enough bandwidth to service all of the physical lines and each physical line will receive a weighted proportion the queue engine's available WAN bandwidth. If the Any-PHY bus becomes the bottleneck, then a simple round robin scheduler at the Any-PHY interface will determine the transmission order. For this reason, the system designers should ensure that the Any-PHY bus does not become the bottleneck. Finally, if the physical lines are the bottleneck, then the physical line rates and the WIRR WAN scheduler will determine the transmission order. This last situation is the most desirable one because in this case no transmission opportunities will ever be missed. 10.4 WAN Port Aliasing For each of the four channels, a port aliasing register is provided to allow for port sparing for the uplinks. These registers map the internal VC's PortID to the external Any-PHY address. By having this layer of indirection, it is possible to redirect all traffic from one Any-PHY address to another by modifying a single register, and without having to change any per-VC context information.
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10.5 WAN and Loop ICI Selection The S/UNI APEX requires that an ICI be received with every cell. A connection identified by a single ICI may be either a VCC or a VPC connection. The ICI may be prepended to the cell or embedded in the VPI/VCI header for interfacing to devices that cannot add prepends to the cell. The S/UNI APEX accepts cells from the following sources: WAN ports, loop ports, and the microprocessor port. Each cell is directed to a particular connection, which is identified by an ICI. For cells from the microprocessor port, the ICI is given directly. For the WAN and Loop ports, this ICI may be selected from one of several locations within the cell and is programmable per interface. The ICI may be: * * * A two byte user tag prepended to the cell. The two byte HEC/UDF field of the cell. Embedded in the 12 bit VPI & 16 bit VCI field as defined as follows: If the VPI < "FFF" then ICI = "0" & VPI; -- This connection is a VPC connection. else ICI = VCI; -- This connection is a VCC connection. end if; In an UNI environment, the S/UNI APEX considers the 4 bit GFC field plus the 8 bit VPI field as the VPI field described above. 10.6 Microprocessor Interface The microprocessor interface supports the following features: * * 32-bit wide multiplexed address data bus. Synchronous microprocessor interface supporting linear bursts of up to 16long words for cell transfers, up to 5 long words for performance sensitive context memory, and single long word accesses for registers and remaining context memory.
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* *
Microprocessor clock independent of the system clock, allowing for easy integration into any host system without altering device performance. Addressing: * * * Direct addressing for internal control and status, SAR assist, CBI register port and memory port. Indirect addressing (via the Memory Port) for context memory accesses. Indirect addressing (via the CBI Register Port) for CBI register accesses.
* * *
High and Low Priority Interrupt outputs provided for efficient task management. Bus Polarity Select pin provided to allow interconnect between the S/UNI APEX and PowerPC or i960 microprocessors. Write Done Indicator output provided to allow interconnect with the IDT MIPS microprocessor (with minimal external logic for system command generation and interpretation).
The microprocessor interface receives a multiplexed address and data bus, where an address strobe input defines the address cycle. During the address cycle, the bus contains the address for the beginning of the transaction. Also during this cycle, the chip select, write indicator, and burst indicator are latched to define the transaction. The interpreted polarity of the write indicator and burst indicator are controlled by a single configuration input pin, for compatibility with multiple microprocessors such as the PowerPC or the i960. If a read transaction is indicated at the address cycle, then S/UNI APEX will respond with a ready indicator concurrent with each long word of valid data, until the burst is complete. The delay between the address cycle and the first valid long word of read data is variable, depending on the specific register address (not less than 2 clock cycles). If a read transaction is issued to the receive SAR when no data is available, or issued to the memory port when the current command is not yet complete, the first word of valid read data will be delayed until data is available (this can be many clock cycles). If excessive delay for the first word of valid read data cannot be tolerated, then polling (or interrupt processing) must be used for accesses to these regions. The ready indicator may be deasserted by S/UNI APEX in the middle of a burst read operation to allow for read data synchronization delay. If a write transaction is indicated at the address cycle, then S/UNI APEX will respond with a ready indicator concurrent with each long word of valid data, until
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the burst is complete. The delay between the address cycle and the first valid long word of write data is variable, depending on the specific register address (not less than 1 clock cycle). If a write transaction is issued to the transmit SAR when the buffer is full, or issued to the memory port when the current command is not yet complete, the first word of valid write data will be delayed by the ready indicator until buffer space is available (this can be many clock cycles). If excessive delay for the first word of valid write data cannot be tolerated, then polling (or interrupt processing) must be used for accesses to these regions. Once the ready indicator has been asserted, it will remain asserted until the completion of the burst. An additional output is provided to indicate when the current write operation is complete (write done indicator). Processors which do not allow the ready indicator to be used to delay the advance of write data, but do allow a write operation to be delayed before it is issued (such as the IDT MIPS processor) may use this output. The write done indicator is asserted when S/UNI APEX can accept another write command. Typically, an external circuit may be employed which uses this S/UNI APEX output to determine when to allow the processor to issue another write command. When this output is used prior to the address cycle, the normal ready indicator need not be used for write operations, as S/UNI APEX can accept write data always once the write done indicator is asserted (unless polling of buffer status is disabled). Note that polling of buffer status must be employed when the processor does not allow the ready indicator to be used to delay the advance of write data. If a burst is indicated at the address cycle, then the transaction will not complete until the processor asserts the burst last indicator. If a burst is not indicated, then the transaction will be completed after the ready indicator is asserted by S/UNI APEX. The multiplexed address/data bus will be Hi-Z'd immediately following the last word of read data to allow a new address cycle to commence. The microprocessor interface will allow an address cycle to occur with no wait states between the last word of valid data and the new address; however, care must be taken to minimize bus contention in the system design if no wait states are provided by the microprocessor. The diagrams below illustrate possible connections between the APEX and various microprocessors. For the i960 interface, the two lower order bits of the address may be tied to ground as all accesses to the APEX are 32bits wide.
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Figure 7
- i960 (80960CF) Interface
BCLK PCLK[2:1] A[31:2] BE#[3:0]
AD[31:0] ADSB CSB WR BURSTB BLASTB READYB BTERMB WRDONEB VCC BUSPOL
D[31:0] ADS# W/R# BLAST# READY# BTERM# BOFF# HOLD HOLDA i960 (80960CF)
Figure 8
- PowerPC (MPC860) Interface
BCLK CLKOUT A[31:0]
AD[31:0] ADSB CSB WR BURSTB BLAST(B) READYB BTERMB WRDONEB BUSPOL VCC
DP[3:0] D[31:0] TS# R/W# BURST# BDIP# TA# BI# TEA# BR# BG# MPC860
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10.7 Memory Port Much of the configuration information that S/UNI APEX requires for normal operation is accessed indirectly through the memory port, as the configuration storage is tightly coupled to performance. Register arrays are provided to allow access to the following memory apertures: * * * External Queue context Internal Queue context Internal Loop context
The memory port is primarily used for context setup, but may also be used for diagnostic purposes. Features include * Control register allows the microprocessor to specify the aperture, address, and length of the burst. Access to the internal loop context are restricted to single long word accesses. 4-word burst write buffer with 8-bit overflow register, supporting writes of up to 4 contiguous 34-bit words to valid apertures. Masked write mechanism, which can be used to overwrite specific bits of 1 word without affecting other bits. 4-word burst read buffer with 8-bit overflow register, supporting reads of up to 4 contiguous 34-bit words from valid apertures. Memory port status provided in the low priority interrupt status register, allowing for polling or for interrupt driven accesses to memory.
* * * *
Memory is accessed using a 4-long word address in the control register, along with 4 long-word enables. This approach allows non-contiguous bursts within a 4-long word section of memory, or to specify which long word is to be accessed in single long word transfer. (For example, the first and third word of a section may be modified without changing the second and fourth). To compensate for the difference between the 34-bit context memory bus and the 32-bit microprocessor bus, an 8-bit overflow register is provided for both reads and writes. The overflow register represents the most significant 2 bits of up to 4 words in a burst access. In this manner, 4 34-bit words can be accessed using a 5-word burst on the microprocessor bus.
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The masked write mechanism is provided to allow the microprocessor to change a field within a word in context memory while traffic is present, without risk of context corruption. The masked write can be performed on one word per operation. In this mode (as indicated in the control register), the second word in the 4-word burst write buffer and the second pair of bits in the overflow register represent a bit mask which will be used by S/UNI APEX to perform a masked write function. 10.8 SAR Assist The SAR assist module allows cells or AAL5 frames to be transferred to and from the queue engine. Burst transfers from the microprocessor into and out of the SAR staging buffers enable efficient access to the queuing structures. The staging buffers are organized as 64 byte units, including the ICI/ECI, the cell header, the payload, and control or status information. A complete buffer can be written or read in one continuous burst, or the data can be accessed individually or with a series of shorter bursts. Within this structure, both the cell header and the payload are aligned on 32-bit boundaries, to simplify microprocessor access. The SAR assist module can also optionally perform calculation, checking, and insertion of AAL5 CRC32 or CRC10. One staging buffer is provided for cell or frame injection, while four staging buffers are provided for cell or frame reception (one for each microprocessor class queue). 10.8.1 Transmit The transmit function of the SAR has the following features: * * * * * Read staging buffer for each of the 4 class queues associated with the microprocessor. CRC-32 checking for AAL5 re-assembly. Simultaneous re-assembly assist on all 4 class queues. CRC-10 checking for OAM. Cell header is provided with each PDU, including PTI for end-of-message detection by the microprocessor.
Each read buffer represents a 2-cell pipeline, providing minimum latency for cell retrieval. While a cell is read out, a second cell is retrieved from the queue engine automatically. By having read buffers for each class, the microprocessor can decide which class has the highest priority. The microprocessor can
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interrupt the retrieval of a frame from one class to transmit a higher priority packet/cell from another class without impacting the CRC32 calculation. The SAR will accept another cell from the queue engine when the 14th long word of the transmit buffer has been read. The SAR assist transmit cell transfer format is shown in Figure 9. Figure 9 Register SarTxData0 SarTxData1 SarTxData2 - SAR Assist Transmit Cell Transfer Format Bits 31-24 H0 Payload1
* * *
Bits 23-16 H1 Payload2
* * *
Bits 15-8 H2 Payload3
* * *
Bits 7-0 H3 Payload4
* * *
CRC Status
SarTxECI
SarTxData13
Payload45
Payload46
Payload47
Payload 48
The SAR performs CRC32 error checking over the entire frame. The CRC32 accumulator for a class is automatically reset on frame boundaries or when a non-user or WFQ cell is encountered (see Table 8). A CRC32 status bit is updated as the EOM cell enters the read buffer. The SAR performs CRC10 error checking over an OAM cell. A CRC10 status bit is updated as the OAM cell enters the read buffer. The processor should verify the cell type (via the cell header) when determining the validity of these status bits. All the CRC status bits in the buffer are updated prior to indicating data is available. Should a CRC error be detected, the microprocessor can skip reading th the cell's entire payload and move on to the next cell by reading the 14 word of the transmit buffer. 10.8.2 Receive The receive function of the SAR has the following features: * * * Single write staging buffer ICI (Ingress Connection Identifier) prepended to all cells Option to overwrite the end of a cell with AAL5 CRC32 or OAM CRC-10
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The single write buffer represents a 2-cell pipeline, allowing the microprocessor to fill one payload while the other one is waiting to be queued. A Not Full status bit is provided, indicating whether the write buffer is capable of accepting at least one cell. Cell enqueuing is initiated by writing to the 14th word of the receive buffer. The SAR assist receive cell transfer format is shown in Figure 10. Figure 10 Register SarRxLWord0 SarRxLWord1 SarRxLWord2 - SAR Assist Receive Cell Transfer Format Bits 31-24 H0 Payload1
* * *
Bits 23-16 H1 Payload2
* * *
Bits 15-8 H2 Payload3
* * *
Bits 7-0 H3 Payload4
* * *
CRC Control
SarRxICI
SarRxLWord13
Payload45
Payload46
Payload47
Payload 48
Once there are 2 cells in the process of being en-queued, any further attempts to write to the write buffer will be held pending until the first cell has been enqueued. The CRC Control gives each cell the option of being overwritten with an AAL5 CRC-32 or an OAM CRC-10 trailer. These CRC values cannot be invoked if OAM cells are interspersed within AAL5 packets. For frame traffic, it is necessary to write SarRxLWord0&1 for the first two cells, SarRxLWord0 for the third cell and SarRxLWord0 for the last cell of the frame SarRxLWord0&1 write of the first cell is required to reset the CRC, and establish the ICI and header for the first pipe. SarRxLWord0&1 write of the second cell is required to set the CRC for normal operation, and establish the ICI and header for the second pipe. SarRxLWord0 write of the third cell is required to remove the reset of the CRC established in the first cell and set the CRC for normal operation. SarRxLWord0 write of the last cell is required to concatenate the CRC onto the end of the cell. The middle cells of the frame only require the payload to be updated. 10.9 Queue Engine The queue engine performs the following functions:
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* * * * * * *
Service Arbitration Congestion Control Statistics Cell Queuing (VC Scheduling) Class Scheduling Watch Dog: VC time out patrol and re-allocation Microprocessor queue buffer re-allocation
10.9.1 Service Arbitration There are 9 components that request services from the queue engine. Three components (SAR Rx, WAN Rx, and Loop Rx) can request a cell to be enqueued. Another three components (SAR Tx, WAN Tx, and Loop Tx) can request a cell to be de-queued. The shaper, if enabled, can request the transmission slots to be advanced (see section on Shape Fair Queuing). There are two possible requests from the watch dog, one to patrol a range of VC queues to detect a timed out VC, and another request to re-allocate buffers from a VC that has timed out. The uP can request a VC or Class queue to have their buffers re-allocated and removed from service. The queue engine is capable of simultaneously servicing any one or all of the requests from an en-queue component, a de-queue component, watch dog patrol and transmission slot advancement. The queue engine is capable of servicing the re-allocation of buffers from either the uP or watch dog alone. To resolve all these requests, there are four arbitration units. See Figure 11.
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Figure 11
- Service Arbitration Hierarchy
Queue Engine
RR Arbiter
"Queue Arbiter" Rx arbiter Tx Arbiter
RR Arbiter
SAR Rx I/F
WAN Rx I/F
Loop Rx I/F
SAR Tx I/F
WAN Tx I/F
Loop Tx I/F
Watch Dog Re-allocate
uP Re-allocate
Watch Dog Patrol
Advance TxSlot
There is a Rx arbiter that receives requests to queue a cell from the SAR, loop and WAN Rx interfaces. There is a Tx arbiter that receives requests to de-queue a cell from the SAR, loop and WAN Tx interfaces. These Rx and Tx arbiters have two options for arbitration. The default option is to have the arbiters use round robin to select between the three interfaces. The alternate option is to have the arbiters use round robin between the loop and the WAN interfaces, with the SAR set to the lowest priority. The results of the Rx and Tx arbiters, along with the request from the watch dog patrol and the shaper transmission slot advancement, are OR'd together to represent a single request from the "queue arbiter". There is a round robin arbiter that receives re-allocation requests from the watch dog and uP. The results of this arbiter, and the one from the "queue arbiter" goes to the final round robin arbiter. 10.9.2 Cell Queuing After congestion control, a cell will be queued onto a linked list structure. The structure is made up of context records, on a per-Port, per-Class, and per-VC basis. Context records are stored in both the external SSRAM and internal RAM. Figure 12 below illustrates the structure of the linked lists, and the relationships between the different context records.
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Figure 12
- Queue Linked List Structure
Class Queue
VC Queue
Class0
Class1
Class2
Class3 VCRecord Group max. 64K Cell Record 64-256K Port Record Group max. 2Kfor Loop max. 4 for WAN max 1 for uP
Cell Flow
Note: The class queue and VC queue as illustrated in the above diagram cannot be directly correlated with the per-Class and per-VC levels as defined in the congestion control. The rules for queuing, and the way the linked lists are utilized is configured on a per-VC basis. A VC may be configured to one of three mutually exclusive queuing procedures. In addition, the queuing of non user cells may be handled differently. The available queuing procedures as a function of the port destination are outlined in Table 7.
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Table 7
- Available Queuing Procedures Loop WAN x x x x x x uP x x
Weighted Fair Queuing Frame Continuous Queuing Shape Fair Queuing Non User Cell Queuing 10.9.2.1 Weighted Fair Queuing
x x
Weighted fair queuing is available to cells destined for the loop, uP and WAN ports. It is configured on a per-Class basis. The VC and class queue work together to provide weighted fair queuing. The class queue is a staging area for cells from different VCs to be lined up for their final destination. The VC demographics in the class queue are defined by each VC's scheduled weight. The WFQ maintains N cells from a VC in the class queue, where N is the weight of the VC. If greater than N cells exist, the excess is maintained in the VC queue. Cells are transferred from the VC queue to the Class queue to maintain the VC weight in the class queue. 10.9.2.2 Frame Continuous Queuing
Frame continuous queuing, or VC merge is available to all ports. It is configured on a per-VC basis. The VC queue is transformed into a frame re-assembly area. Frame traffic is assumed to use the AAL5 EOM PTI field indicator to delineate frame boundaries. Frames are completely assembled in the VC queue before being transferred over to the class queue. Non-user cells encountered on FCQ VCs are handled differently. Please refer the section on Non-User Cell Queuing. The maximum length of the re-assembled frame can be one of two globally defined sizes, selected on a per-VC basis. Should a VC that is in process of reassembly exceed the maximum length, a frame discard will be invoked. The cells in the VC queue will be discarded, as well as the cells that are about to be received up to and including the EOM. From a statistical count perspective, this frame discard is identical to a frame discard caused by congestion. In addition, a per-VC maskable interrupt is invoked and the ICI is stored in a register that only holds the ICI of the last VC that violated the maximum re-assembly length. If a frame has a zero length field in the AAL5 trailer, there is a per-VC context parameter VcLenChkEn that will configure the queue engine to perform an frame discard. As with the maximum length frame discard, this zero length frame
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discard is identical to a frame discard caused by congestion from a statistical count perspective. A VC timeout watchdog is provided to protect memory resource should a reassembly not complete in a timely manner. There are two procedures that are carried out by the watch dog. The first procedure is the patrol, which is performed by the queue engine during regular cell en-queue and de-queue sequence. Within the context record, there is a re-assembly parking state bit, ReasPark. The watch dog has a current re-assembly parking state bit, CurrentReasPark. Whenever a user cell (ie not RRM or OAM cell) arrives, the ReasPark state bit is set to the CurrentReasPark. The watch dog, initiated by the microprocessor, will walk through a programmable range of marked VCs, that are currently being re-assembled, to check and see if ReasPark = CurrentReasPark. If this is true, then the VC is deemed OK. If it finds a valid VC with ReasPark != CurrentReasPark, the VC is deemed dead. The discovery of a dead VC initiates the watch dog re-allocation procedure. When the patrol is complete, the CurrentReasPark bit is automatically inverted to prepare for the next patrol. The watch dog re-allocation procedure is performed between the cell receive/transmit servicing. All the buffers in the VC queue are reclaimed, the VC Q congestion counters are reset to zero, the general discard count is updated, and VC status is reset to receive the next incoming cell as a BOM. A per-VC maskable interrupt is invoked and the ICI is stored in a register that only holds the ICI of the last timed out VC. 10.9.2.3 Shape Fair Queuing
The S/UNI APEX shaper is a passive dual rate shaper based on a time slot design. It will shape on a per VC basis, to the traffic parameters PCR, SCR & MBS. Traffic shaping is available on the four WAN ports, but not on the loop ports. A maximum of four out of the sixteen WAN port classes (four ports, four classes per port) can have shaping applied to their output. Every VC connected to a shaped class will have shaping applied to it, but each VC can have a unique shape rate. Classes that are not shaped can coexist on the same port as classes that are shaped, and there can be more than one shaped class on a single port. Each shaper has a fundamental time unit, QShpNRTRate, which defines the minimum time increment between successively scheduled cells. Although each shaper is independent, the aggregate shape rate (1/QShpNRTRate) of the active shapers must be less than the device overall cell rate limit (1.42Mc/s @ 80MHz). The VC's SCR is defined by the number of fundamental time units, ShpIncr, inserted between the VC's cell as they are scheduled by the shaper. The SCR is
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proportional to 1/ShpIncr. The CDV introduced is within 1 fundamental time unit. When there is neither contention (brief period where multiple VCs are scheduled to transmit at the same time) nor congestion (over-subscription of the port/class), the shaper will always transmit at SCR. See ideal emission of Figure 13. The PCR and MBS only come into effect when the VC experiences one or more periods of contention or congestion (and hence the term passive dual rate shaper). An internal "late counter" is maintained that represents how late the current cell's scheduled emission time slot is relative to the ideal emission time slot. A non-zero late counter will cause the shaper to attempt to recover the lost opportunities by scheduling the cell with an increment value no smaller than ShpIncr - ShpCdvt. The ShpCdvt parameter, user defined on a per-VC basis, is in terms of the shaper's fundamental time unit. The difference (ShpIncr - ShpCdvt) is minimum number of fundamental time units inserted between cells, and is proportional to the VC's 1/PCR. Given the opportunity, the shaper will 1 burst at PCR rates until the late counter returns to zero . The size of the counter, programmable on a per-VC basis, therefore defines the MBS. See case #1 of Figure 13. If congestion persists for an extended period, the late counter will continue to accumulate and eventually wrap around once MBS is reached. The resulting emission pattern is one where the duration of bursting is the remainder of the rolled counter. Every time the counter wraps, a CDV, equal to the MBS, is introduced into the emission stream. Recovery of the cumulative CDVs can only occur if the ingress stream pauses long enough for the VC queue to empty entirely. MaxCDV can be imposed by limiting the length of the VC queue via the per-VC max congestion threshold. See case #2 of Figure 13.
Note that the inter-cell transmission times may actually exceed 1/PCR. Factors include the number of active WAN ports, the number of active loop ports, and back pressure created by the external WAN port.
1
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Figure 13
- Traffic Shaping on the WAN Port
Time 1/SCR
ideal emission 0 1 2 3 4 5 6 <= MBS 1/PCR Case #1 emission after contention, within burst limit 0 Case #2 emission after contention, beyond burst limit 0 1 2 3 4 5 6 1 2 3 4 5 6 7 8 CDV 7 8
For VCs that are shaped to rates approaching the fundamental time unit, there is the issue of granularity caused by the nature of time slots. For example, if the fundamental time unit is the equivalent of 100Mb/s, the maximum shaped rate is 100Mb/s (ShpIncr = 1), the next possible shaped rate is 50Mb/s (ShpIncr = 2). In order to achieve shaped rates between 100Mb/s and 50Mb/s, the ShpIncr may be defined as an integer plus a fractional component. The shaper will schedule a cell to its integer value of ShpIncr, while maintaining a remainder count of the fractional portion. Whenever the remainder count exceeds a unit value, the shaper will schedule the next cell to the integer value + 1. The effective SCR rate over time will be the correct rate, but a CDV equal to the fractional value is introduced into the egress stream. If the ShpIncr is an integer value, then there is no additional CDV introduced due to time slot granularity. PCR and MBS parameters are not supported when non-integer ShpIncr is invoked. See Figure 14 where the ShpIncr has been set to 1.5.
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Figure 14
emission with ShpIncr = 1.5
- Non-integer ShpIncr
fundamental time slots
User programming can also define the action of the shaper when overall egress congestion (i.e. too much traffic being sent through the shaper) is causing all VCs on that port/class to experience shaping delay due to congestion. When congestion is detected, the shaper will temporarily increase the fundamental shaping time unit, thereby causing each VC to schedule cells less frequently. This will eventually relieve the congestion, at which point the time unit will be brought back to its previous value. The impact of the congestion is distributed fairly across all VCs on the congested port because all VCs on the port experience the same relative decrease in scheduling frequency. 10.9.2.4 Non-User Cell Queuing
When a non-user cell is encountered, it may be queued with special handling. The cases requiring special handling are: * Cells identified as an end to end OAM may be redirected to the uP's class 0 queue. This can occur independent of the queuing mechanism selected for the VC (WFQ, FCQ, and SFQ). Cells identified as a segment OAM may be redirected to the uP's class 0 queue. This can occur independent of the queuing mechanism selected for the VC (WFQ, FCQ, and SFQ). During FCQ, a cell identified as an OAM that is not being redirected to the uP will bypass the VC queue re-assembly area and go directly to the class queue. During FCQ, a cell identified as an RRM (Reserved or Resource Management) will bypass the VC queue re-assembly area and go directly to the class queue.
*
*
*
The table below lists the rules used to identify OAM and RRM cell types.
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Table 8 Type
- OAM & RRM Cell Identification Parameter VcVPC = 1 VCI = 4 VcVPC = 1 VCI = 3 VcVPC = 0 PTI = 5 VcVPC = 0 PTI = 4 VcVPC = 0 PTI = 11x Location VC Context Cell header VC Context Cell header VC Context Cell header VC Context Cell header VC Context Cell header
VPC End to End OAM VPC Segment OAM VCC End to End OAM VCC Segment OAM RRM
VPC/VCC End to End OAM cells will be redirected to the uP's class 0 queue if the context parameter VcEEOam = 1, independent of the queue method selected. If VcEEOam = 0 and FCQ is selected, then the cell will be queued directly onto the class queue. VPC/VCC segment OAM cells will be redirected to the uP's class 0 queue if the context parameter VcSegOam = 1, independent of the queue method selected. If VcSegOam = 0 and FCQ is selected, then the cell will be queued directly onto the class queue. Non user cells not meeting any of the above conditions will not be redirected and will be treated like a normal user cell in terms of queuing. The re-direction applied on OAM cells will preclude any performance measuring sessions on VCs that are programmed with FCQ. 10.9.3 Class Scheduling Class scheduling is performed on the loop and WAN ports. There is no class scheduling for the uP ports as all four classes are accessible simultaneously. The class scheduler provides modified priority scheduling with class zero having the highest priority and class three having the lowest. The high priority classes can be utilized for real time services such as CBR and VBR-rt. The lower priority classes can be utilized for VBR-nrt, GFR and UBR services. There are three configurations for class scheduling:
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* * *
strict priority, round robin or modified strict priority between classes, evaluated after the transmission of each cell. strict priority between classes, evaluated after the transmission of an entire packet, and available only to those VCs configured for FCQ. strict priority between classes, evaluated after the transmission of a partial packet of a programmable length, and available only to those VCs configured for FCQ. Cell and Packet Scheduling
10.9.3.1
In order to ensure that the lower priority classes are not starved when the high priority classes are under heavy utilization, a minimum bandwidth reservation scheme is employed. The user can program the minimum bandwidth requirements of classes one, two, and three and thus avoid starvation. Setting the minimum bandwidth requirements to zero (ClassXCellLmt = 0) on all classes will result in the class scheduler acting as a strict priority scheduler. Setting the minimum bandwidth requirements to three (ClassXCellLmt = 3) on all classes will result in the class scheduler acting as a round robin scheduler. The mechanism utilized to ensure that a class does not starve is as follows. The class scheduler keeps track of the number of missed transmit opportunities the lower priority classes within a port have had. When a cell is transmitted on a particular class the ClassXCellCnt counters are incremented for all other classes which have missed an opportunity to transmit a cell. Once the ClassXCellCnt for a class reaches a maximum value (as defined by ClassXCellLmt), the class is in starvation. On the next cell transmit opportunity for that port, the starving class will be allowed to transmit one cell. If multiple classes were indicating starvation then the highest priority class would transmit first, then the next class until all starving classes have been serviced. A starving class is only allowed to transmit one cell at a time. This ensures that the higher priority classes do not experience a large amount of CDV caused by the lower priority classes. When a class has an opportunity to transmit (due to starvation avoidance or otherwise), its ClassXCellCnt is reset and the above procedure is repeated. A per-Port parameter, ClassPacket, is provided to support continuous packet transmission. In this packet mode, a VC that is configured for FCQ will retain permission to transmit cells for the length of the entire packet, regardless of the starvation states of the other classes, including class 0. This feature enables traffic to be emitted from the S/UNI APEX packet contiguously and thus minimizing the buffering requirements for an external SAR device. Strict priority must be set whenever packet class scheduling is selected.
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It is possible to mix VCs that have FCQ and WFQ scheduling within the same class, and ClassPacket enabled. Non FCQ VCs and non-user cells (as defined in Table 8) are treated as single cell packets. All counters, control and limit fields for the class scheduler are located in the class scheduler context memory. As stated earlier, memory is only allocated for classes one, two, and three. Class zero does not require any class scheduler context information. 10.9.3.2 Partial Packet Scheduling
A per-Port parameter, ClassFragEn, is provided to support packet fragmentation. In this fragmentation mode, classes are selected on a strict priority basis. Once a class is selected, the packet at the head of the class queue is transmitted up to a programmable length or until the EOM is encountered, whichever comes first. Non FCQ VCs and non-user cells (as defined in Table 8) are treated as single cell packets. When the length/EOM is reached, the classes are evaluated once again in a strict priority. The transmission of the original packet will resume once the original class regains transmission rights. Note that by virtue of the strict priority scheduling, Class0 will always have its packets transmitted in their entirety. 10.9.4 Congestion Control The congestion control decides whether to permit a cell to enter the queue structure. The objective is to provide a minimum reserved buffer allocation to all active VCs and to fairly allocate shared buffer resources to eligible VCs. The algorithm is applied to both frame and non-frame traffic. The objectives of the algorithm are as follows: * * * provide guaranteed resources to all active VCs share available buffer resources to eligible VCs with excess buffering requirements restrict resource allocation on a per-VC, per-Class, per-Port, and perDirection basis to those levels that have exceeded their allotment of resources. avoid global synchronization Provide interrupts and ID of the last maximum threshold discard invoked.
* *
These objectives are achieved by having several thresholds and hierarchical count values, at the per-Device, per-Direction, per-Port, per-Class, and per-VC
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levels. Figure 15 illustrates the relationship between the hierarchical count values and their associated thresholds. Figure 15 - Thresholds and Count Definitions
FreeCnt Per-Device Initial state of FreeCnt max. 256K - 1 cells
DirCnt Per-Direction (1 loop, 1 WAN) DirCLP1Thrsh Per-Port (2K loop, 4 WAN, 1 uP) DirCLP0Thrsh PortCnt
DirMaxThrsh max. 256K -1 cells
PortCLP1Thrsh
PortCLP0Thrsh ClassCnt
PortMaxThrsh max. 256K - 1 cells
Per-Class (4 per port) ClassCLP1Thrsh Per-VC (aggregate max. 64K VC) VcCLP1Thrsh VcCLP0Thrsh VcMaxThrsh max. 8K-1 cells VcCLP0Cnt Per-VC(CLP0) VcCLP0MinThrsh ClassMaxThrsh max. 256K - 1 cells VcCnt = VcQCLP01Cnt + VcClassQCLP01Cnt ClassCLP0Thrsh
Each hierarchical level has three population zones, each with its own discard rules: 1) Plenty of resources available, no discard 2) Some resources available, discard all cells with inbound CLP state = 1 3) Restricted resources available, discard all cells except cells that have inbound CLP state = 0 and have not met their minimum allocation of resources (VcCLP0MinThrsh).
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No equivalent per-Direction count and threshold for uP destined cells, since there is only 1 uP port. All counts represent the number of cells found at the hierarchical level, with the exception of FreeCnt at the per-Device level. The FreeCnt count value represents the number of free buffers remaining in the device. The initial value of FreeCnt is defined by the user. The congestion algorithm has three possible definitions for CLP: 1) cell CLP, the CLP found in each cell's header; 2) BOM CLP, the CLP found in the frame BOM cell's header; 3) OR CLP, the running OR of all received user cell's CLPs since the BOM of a frame. Non-user cells do not affect the state of the running OR CLP. Depending on the VC configuration, anyone of these three definitions can be used to increment a congestion count, or to select a threshold when comparing to a count. When the queue engine receives a cell, the congestion control will apply the discard rules at each hierarchical level. Only when a cell has passed through each hierarchical level without being discarded will it be permitted entry into the queue. Setting the Max threshold to zero on any given hierarchical level will effectively disable congestion discards at that hierarchical level. Exception to this rule is the VcMaxThrsh, which will always have the 8k-1 limit. The xxxCLP0Thrsh thresholds must always be set greater than or equal to the xxxCLP1Thrsh thresholds. There are several error flags set whenever a non-zero maximum threshold is exceeded. Table 9 correlates the interrupts and context record identification parameters to the corresponding maximum threshold. Table 9 Threshold VcMaxThrsh - Congestion Error Flags Interrupt QVcMaxThrshErr (Maskable on per-VC basis) ClassMaxThrsh PortMaxThrsh QClassMaxThrshErr QPortMaxThrshErr ClassMaxThrshErrID ClassMaxThrshErrPortID PortMaxThrshErrID Identification VcMaxThrshErrID
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DirMaxThrsh FreeCnt = 0
QDirMaxThrshErr QFreeCntZeroErr
Check WANCnt or LoopCnt N/A
EFCI marking may be performed on cells as they are transmitted out of the queue, based on the state of congestion at the time of transmission. Marking of EFCI is per VC selectable to occur at either the CLP1 thresholds or the CLP0 thresholds. A cell will be marked if hierarchical count values exceed one of the CLP1 thresholds (VcCLP1Thrsh, ClassCLP1Thrsh, PortCLP1Thrsh, DirCLP1Thrsh) or one of the CLP0 thresholds (VcCLP0Thrsh, ClassCLP0Thrsh, PortCLP0Thrsh, DirCLP0Thrsh), and the third bit of the PTI field in the cell is zero (PTI = 0xx). There are three unique congestion discard rules. The selection of the rule to be applied is based on the cell type (user or non-user), the queuing mechanism, and finally the congestion type. If it is a non-user cell, the congestion mode is always cell discard. If shaping is not enabled for the destination port/class, the discard rule is selected on a per-VC basis, and is a function of the queue mechanism selected (VcQueue), as well as a per-VC congestion context parameter (VcCongMode). If the port/class is shaped, only two of the three rules is available, and is selectable on a per-VC basis. Table 10 below illustrates how the congestion discard rule is selected. Table 10 Cell User User User User User Non-user - Congestion Discard Rules Selection Shaped No No No Yes Yes x VcQueue 0 (WFQ) 0 (WFQ) 1 (FCQ) x x x VcCongMode 0 1 x 0 1 x Congestion Mode EPD/PPD discard Cell discard FCQ discard EPD/PPD discard Cell discard Cell discard
OAM cells that are redirected to the microprocessor are subject to cell discard rules applied to the uP congestion counts at the per-port and per-class levels. There is no congestion control at the VC level for these redirected OAM cells.
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10.9.4.1
EPD/PPD Discard - EPD/PPD Congestion Discard Rules
Figure 16
When FreeCnt = 0 invoke EPD on BOM invoke PPD on COM/EOM Per-Device Initial state of FreeCnt invoke EPD on BOM invoke PPD on COM/EOM when DirCnt >= DirMaxThrsh DirCLP1Thrsh DirCLP0Thrsh DirMaxThrsh invoke EPD on BOM invoke PPD on COM/EOM when PortCnt >= PortMaxThrsh PortCLP1Thrsh PortCLP0Thrsh PortMaxThrsh invoke EPD on BOM invoke PPD on COM/EOM when ClassCnt >= ClassMaxThrsh ClassCLP1Thrsh ClassCLP0Thrsh ClassMaxThrsh invoke EPD on BOM invoke PPD on COM/EOM when VcCnt >= VcMaxThrsh VcCLP1Thrsh VcCLP0Thrsh VcMaxThrsh Invoke EPD on CLP1 frame when xxCnt >= xxCLP1Thrsh
Per-Direction
Per-Port
Per-Class
Per-VC
No discard
Invoke EPD on CLP0, CLP1 frame when xxCnt >= xxCLP0Thrsh EXCEPT CLP0 frame having VcCLP0Cnt < VcCLP0MinThrsh
Invoke EPD on CLP0, CLP1 frame when VcCnt >= VcCLP0Thrsh
When EPD/PPD discard is selected, the discard mechanism uses the AAL5 EOM PTI field indicator to delineate frame boundaries EPD discard is evaluated only when the BOM is received, and is based on the BOM CLP state. The VcCLP0Cnt increments when a received cell passes congestion and the inbound CLP state is zero. The VcCLP0Cnt decrements when the outbound CLP state is zero. The in/outbound CLP state is defined by the per-VC context parameter, VcGFRMode. When VcGFRMode = 0, the in/outbound CLP is
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defined by the receiving/transmitting cell CLP state, respectively. When VcGFRMode = 1, the in/outbound CLP is defined by the receiving/transmitting frame's BOM CLP state, respectively. If a PPD discard is invoked, the EOM will not be discarded unless one or more of the hierarchical count values is greater than or equal to the Dir/Port/Class/Vc MaxThrsh at the time the EOM is received. If the EOM is discarded, the following frames will be discarded and the congestion status will remain in PPD until an EOM is accepted. In the case when VcGFRMode = 1, the BOM CLP state of the first frame will be used to define the CLP state of the following discarded frames. 10.9.4.2 Cell Discard Cell Congestion Discard Rules
Figure 17
Discard cell when FreeCnt = 0 Per-Device Initial state of FreeCnt Discard cell when DirCnt >= DirMaxThrsh DirCLP1Thrsh DirCLP0Thrsh DirMaxThrsh Discard cell when PortCnt >= PortMaxThrsh PortCLP1Thrsh PortCLP0Thrsh PortMaxThrsh Discard cell when ClassCnt >= ClassMaxThrsh ClassCLP1Thrsh ClassCLP0Thrsh ClassMaxThrsh
Per-Direction
Per-Port
Per-Class
Per-VC VcCLP1Thrsh VcCLP0Thrsh
Discard cell when VcCnt >= VcCLP0Thrsh
No discard
Discard CLP1 cell when xxCnt >= xxCLP1Thrsh
Discard CLP0, CLP1 cell when xxCnt >= xxCLP0Thrsh EXCEPT CLP0 frame having VcCLP0Cnt < VcCLP0MinThrsh
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When in cell discard mode, the CLP state is defined by each cell, and the decision to discard is evaluated upon receiving each cell. The minimum resource counter VcCLP0Cnt increments/decrements based on the cell CLP received/transmitted. Non-user cells always have cell discard congestion rules applied, regardless of the original VC's congestion setting. Non-user cells do not have per-VC congestion as the VcQCLP01Cnt is not active when a non-user cell is encountered. 10.9.4.3 FCQ Discard FCQ Discard Rules
Figure 18
invoke frame discard when FreeCnt = 0 Per-Device Initial state of FreeCnt invoke frame discard when DirCnt >= DirMaxThrsh DirCLP1Thrsh DirCLP0Thrsh DirMaxThrsh invoke frame discard when PortCnt >= PortMaxThrsh PortCLP1Thrsh PortCLP0Thrsh PortMaxThrsh invoke frame discard when ClassCnt >= ClassMaxThrsh ClassCLP1Thrsh ClassCLP0Thrsh ClassMaxThrsh
Per-Direction
Per-Port
Per-Class
Per-VC VcCLP1Thrsh
invoke frame discard when VcCnt >= VcCLP0Thrsh VcCLP0Thrsh Invoke frame discard on CLP1 frame when xxCnt >= xxCLP1Thrsh
No discard
Invoke frame discard on CLP0, CLP1 frame when xxCnt >= xxCLP0Thrsh EXCEPT CLP0 frame having VcCLP0Cnt < VcCLP0MinThrsh
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When FCQ discard is selected, the discard mechanism uses the AAL5 EOM PTI field indicator to delineate frame boundaries. Frame discard is evaluated after receiving each cell. The per-VC context parameter, VcGFRMode, dictate how frame discard is evaluated. When VcGFRMode = 0, frame discard is based on the OR CLP. When VcGFRMode = 1, frame discard is based on the BOM CLP. The minimum resource counter is incremented/decremented after receiving/transmitting a cell that has the BOM CLP = 0. When frame discard is invoked, the minimum resource count value will be reduced by the number of cells found in the VC queue if the BOM CLP = 0. 10.9.5 Statistics There are two transmit counts, and three discard counts. All counts are 32-bits wide. The sum of all counts equals the total number of cells received by the S/UNI APEX. Table 11 gives a summary of the statistical counts. Table 11 Count VcCLP0TxCnt - Statistical Counts Scope Per- VC Description Per-VC count of all cells transmitted that had an outbound CLP state of zero. OAM cells re-directed to the uP will not be represented by this count. Per-VC count of all cells transmitted that had an outbound CLP state of one. OAM cells re-directed to the uP will not be represented by this count. Global count of all inbound CLP0 cells discarded due to congestion, re-assembly maximum length limit, or zero length check. There is an associated register that holds the last ICI that caused this count to increment. CLP1DiscardCnt Global Global count of all inbound CLP1 cells discarded due to congestion, re-assembly maximum length limit, or zero length check. There is an associated register that holds the last ICI that caused this count to increment. DiscardCnt Global Global count of all discards that are not due to congestion. These include cells discarded due reassembly time outs, cells received on VCs that were not
VcCLP1TxCnt
Per- VC
CLP0DiscardCnt
Global
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Count
Scope
Description enabled, execution of a VC queue or a class queue tear down.
The definition of the in/out bound CLP state is a function of the congestion discard mode, and the per-VC parameter VcGFRMode. Table 12 illustrates the definition of in/out bound CLP state. Table 12 - In/out Bound CLP State For Statistical Counts VcGFRMode X 0 1 FCQ Discard 0 1 Inbound CLP Cell CLP Cell CLP BOM CLP OR CLP BOM CLP Outbound CLP Cell CLP Cell CLP Cell CLP Cell CLP Cell CLP
Congestion Mode Cell Discard EPD/PPD Discard
The table below give a brief summary of the rules applied for discard, and CLP definition for incrementing various counts as a function of the discard mode and the specific cell encountered. Table 13 - Congestion Rule & Count Summary cell x x EPD/PPD x x 0 1 FCQ x x 0 1
Condition Discard Mode VcGFRMode Cell Type
pass redir user user pass redir user user thru ect thru ect OAM OAM OAM OAM cell cell cell cell cell cell n/a cell BOM BOM cell BOM BOM cell cell cell BOM cell cell cell cell cell n/a cell cell OR cell cell BOM cell
Rules for when discard cell discard decision is made CLP def'n CLP VcCLP0Cnt definition VcCLP0TxCnt for various or counts VcCLP1TxCnt cell cell cell
BOM BOM
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Condition Discard Mode VcGFRMode Cell Type
cell x x
EPD/PPD x x 0 1
FCQ x x 0 1
pass redir user user pass redir user user thru ect thru ect OAM OAM OAM OAM cell cell cell BOM cell cell OR BOM
CLP0DiscardCnt cell or CLP1DiscardCnt
One reads the table vertically. Take the last column. A user cell arrives in a connection configured for FCQ, VcGFRMode = 1, will have -its discard decision made on a cell by cell basis; -the CLP is defined by the BOM for discard purposes; -the minimum CLP0 count will be incremented based on the BOM, if the frame is not discarded; -either VcCLP0TxCnt or VcCLP1TxCnt will be incremented based on the CLP of the cell, if the frame is not discarded; --either CLP0DiscardCnt or CLP1DiscardCnt will be incremented based on the CLP of the BOM, if the frame is discarded. 10.9.6 Microprocessor Queue Buffer Re-allocation/Tear Down The microprocessor has the option of engaging one of two macros that provide a fast mechanism to tear down either a VC queue or a Class queue for nonshaped port class. Specified and initiated through registers, the macro will go to the specified queue, reclaim the buffers in the queue, and reset the appropriate congestion counters. The number of cells that were in the queue are added to the general discard count. The VC queue or Class queue remain enabled after the re-allocation. Invoking of these functions may reduce general throughput of the device. 10.10 Context Memory SSRAM Interface The context memory SSRAM interface stores and retrieves context data from one of two SSRAM devices: pipelined ZBT or register to register late write. Up to 4 banks and 4 SSRAM devices are supported, with 1M addressing capability for a total of 4MB data capacity. 2 parity bits are provided to protect the 34-bit data bus. If a parity error occurs, an interrupt is sent to the microprocessor.
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The clock source drawn in Figure 19, Figure 20, Figure 21, Figure 22, Figure 23, must all be skew aligned at between S/UNI APEX, SDRAM & SSRAM clock input pins. Figure 19 - 1 Bank Configuration for 1MB of ZBT SSRAM
clock source SYSCLK CMD[16:0] CMP[0] CMRWB CMCEB CMA[17:0] to SDRAM Addr/Ctrl Data[17:0] 256Kx18 CLK CE2# CE2 Addr/Ctrl CMD[33:17] CMP[1] Data[17:0] 256Kx18 CLK CE2# CE2 0 1
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Figure 20
- 1 Bank Configuration for 1MB of Late Write SSRAM
clock source SYSCLK CMD[16:0] CMP[0] CMRWB CMA[17:0] to SDRAM Addr/Ctrl Data[17:0] 256Kx18 CLK SS# Addr/Ctrl CMD[33:17] CMP[1] Data[17:0] 256Kx18 CMCEB CLK SS#
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Figure 21
- 2 Bank Configuration for 2MB of ZBT SSRAM
clock source SYSCLK to SDRAM Addr/Ctrl CMD[16:0] CMP[0] CMRWB CMCEB CMA[17:0] Data[17:0] 256Kx18 CLK CE2# CE2 Addr/Ctrl Addr/Ctrl Data[17:0] 256Kx18 CLK CE2# CE2 Addr/Ctrl Data[17:0] 256Kx18 CLK CE2# CE2 0
CMD[33:17] CMP[1]
Data[17:0] 256Kx18 CLK CE2# CE2 1
CMA[18]
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Figure 22
- 2 Bank Configuration for 2MB of Late Write SSRAM
clock source SYSCLK CMD[16:0] CMP[0] CMRWB CMA[18:1] to SDRAM Addr/Ctrl Data[17:0] 256Kx18 CLK SS# Addr/Ctrl Addr/Ctrl Data[17:0] 256Kx18 CLK SS# Addr/Ctrl Data[17:0] 256Kx18 CLK SS#
CMD[33:17] CMP[1] CMA[0] CMCEB CMAB[17] CMAB[18] nc
Data[17:0] 256Kx18 CLK SS#
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Figure 23
- 4 Bank Configuration for 4MB of ZBT SSRAM
clock source SYSCLK CMRWB CMCEB CMA[17:0] Addr/Ctrl CMD[33:0] CMP[1:0] Data[35:0] 256Kx36 CLK CE2# CE2 Addr/Ctrl Data[35:0] 256Kx36 CLK CE2# CE2 Addr/Ctrl Data[35:0] 256Kx36 CLK CE2# CE2 Addr/Ctrl Data[35:0] 256Kx36 CLK CE2# CE2 to SDRAM
CMA[18] CMAB[18] CMA[19]
There are two processes, arbitrated by the SSRAM arbiter, that access the context SSRAM: 1. The queue engine, for reading and writing context information, and for executing the re-assembly watchdog, described in the AAL5 Re-assemble Queuing section; 2. The microprocessor interface, for reading or writing context information, including the option of mask writes. See the Memory Port section for a description of the SSRAM access via the Microprocessor Interface; 10.11 Cell Buffer SDRAM Interface The S/UNI APEX uses the external SDRAM to buffer queued cells. The cell buffer SDRAM interface permits up to 2 devices in parallel, with 4M addressing capability for a total of 16 MB of storage, sufficient for up to 256k cells. It has a 32 bit wide data bus, with CRC-16 checking applied on a per-cell basis. Each cell takes up 64 bytes of memory. The CRC-16 is applied to the first 60 bytes. If an error occurs, an interrupt is sent to the microprocessor.
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The following diagram shows the cell storage map with the 64 byte memory boundary. Figure 24 - Cell Storage Map
Word #
31
16 15 Reserved (0)
0
Bit #
xx_addr[17:0] + 0 1 2 3 ... 13 14 15 31 Header1 Payload1 Payload5
Header2 Payload2 Payload6 ...
Header3 Payload3 Payload7
Header4 Payload4 Payload8
Payload45 Payload46 Payload47 Payload48 Reserved (0) Reserved (0) 24 23 16 15 CRC-16 8 7 0
The clock source drawn in Figure 25, Figure 26, Figure 27 must all be skew aligned at between S/UNI APEX, SDRAM & SSRAMs clock input pins. The following diagrams illustrate the various configurations supported:
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Figure 25
- 4 MB - 64k Cells
clock source SYSCLK CBCSB CBRASB CBCASB CBWEB CBBS[0] CBA[10:0] CBDQM[0] CBDQ[15:0] 1 1 to SSRAM CKE CLK Addr/Ctrl 2 x 2k x 256 x 16 DQM[1:0] DQ[15:0] CKE CLK Addr/Ctrl 2 x 2k x 256 x 16 CBDQM[1] CBDQ[31:16] DQM[1:0] DQ[15:0]
Figure 26
- 8 MB - 128k Cells
clock source SYSCLK CBCSB CBRASB CBCASB CBWEB CBBS[1:0] CBA[10:0] CBDQM[1:0] CBDQ[31:0] 1 to SSRAM CKE CLK Addr/Ctrl 4 x 2k x 256 x 32 DQM[3:0] DQ[31:0]
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Figure 27
- 16 MB - 256k Cells
clock source SYSCLK CBCSB CBRASB CBCASB CBWEB CBBS[1:0] CBA[11:0] CBDQM[0] CBDQ[15:0] 1 1 to SSRAM CKE CLK Addr/Ctrl 4 x 4k x 256 x 16 DQM[1:0] DQ[15:0] CKE CLK Addr/Ctrl 4 x 4k x 256 x 16 CBDQM[1] CBDQ[31:16] DQM[1:0] DQ[15:0]
There are three processes, arbitrated by the SDRAM arbiter, that access the cell buffer SDRAM: 1. The queue engine, for reading and writing cells. The granularity of access by the queue engine is a concatenated 1 cell write - 1 cell read. Either the write or the read may not be performed, depending on the queue engine's requirements; 2. The microprocessor interface, for diagnostic reading or writing of 64 bytes of data. This data is aligned with the cell data. See the Operations section for a description of the data format; 3. The refresh controller, which has a programmable refresh rate. The SDRAM interface will perform the initialization sequence for the SDRAM. This sequence is triggered by the SDRAM enable bit CBEn. The sequence will program the SDRAM with a CAS latency of 3, sequential access, write burst mode, and a burst length of 8. Application should ensure that sufficient time is provided between SDRAM power up and when this enable bit is set.
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The SDRAM interface, under the direction of the queue engine, performs the header remapping function as the cell is read from SDRAM. It also attaches the cell prepends including the Switch Tag, ECI/ICI and Any PHY address prepend. 10.12 JTAG Test Access Port The JTAG Test Access Port block provides JTAG support for boundary scan. The standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions are supported. The S/UNI APEX identification code is 073260CD hexadecimal.
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11
PERFORMANCE
11.1 Throughput The maximum throughput is governed at 3 potential bottlenecks: - Receive interface configuration. - Queue engine mode (shaper on or off). - Transmit interface configuration. The lowest throughput of the 3 bottlenecks will dictate the overall throughput for a given cell datapath. General assumptions: SYSCLK = 80MHz no watch dog recovery in progress SDRAM refresh set to slowest rate BCLK = 66MHz no setup/tear downs/context memory access in progress Any-PHY clocks = 52MHz 16 bit interface for non uP receive and transmit interface ICI in HEC/UDF field for non uP receive interface ECI and Switch Tag disabled for non uP transmit interface Table 14 Port/Configuration Any-PHY Master - Receive Interface Throughput, Mcells/sec Loop 1.67 WAN 1.67 uP n/a Assumptions address polling range optimized, n external port slaves, n >= 1, equal traffic address polling range set to 2, 1 external port slave address polling range optimized, n external port slaves, n >= 2, equal traffic none none
UTOPIA L2 Master
1.44 1.74
1.44 1.74
n/a n/a
UTOPIA L1 Master UTOPIA L2 Slave
1.74 1.74
1.74 1.74
n/a n/a
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Port/Configuration uP full cell insertion uP partial cell (multi-cast) Table 15
Loop n/a n/a
WAN n/a n/a
uP 1.1 1.74
Assumptions SarRxData0->13 written SarRxData0, 13 written
- Queue Engine Throughput, Mcells/sec Assumptions 1.74* 1.42 none none
Configuration Shaper disabled Shaper enabled
* Throughput drops down to 1.63 Mcells/sec if only a single WAN port is transmitting and no cells are being received by either the loop, WAN or uP Rx interfaces. Table 16 Port/Configuration Any-PHY Master - Transmit Interface Throughput, Mcells/sec Loop 0.56* 1.11* 1.0* 1.6* n/a n/a UTOPIA L2 Master 0.61 1.25 1.1 1.6 WAN n/a n/a n/a n/a 1.74 1.68 n/a n/a n/a n/a uP n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a Assumptions limit 1 cell/port in FIFO, 1 external port slave limit 2 cell/port in FIFO, 1 external port slave limit 1 cell/port in FIFO, 2 external port slave limit 2 cell/port in FIFO, 2 external port slave 1 external port slave 2 external port slave, equal traffic limit 1 cell/port in FIFO, 1 external port slave limit 2 cell/port in FIFO, 1 external port slave limit 1 cell/port in FIFO, 2 external port slave limit 2 cell/port in FIFO, 2 external port slave
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Port/Configuration
Loop n/a n/a
WAN 1.44 1.68 1.74 1.74 n/a
uP n/a n/a n/a n/a 1.61
Assumptions 1 external port slave 2 external port slave, equal traffic none none none
UTOPIA L1 Master UTOPIA L2 Slave uP full cell extraction
1.67 1.67 n/a
* Throughput reduced when shaper is enabled. Guarantee minimum 0.4 Mcells/sec per loop port when there are 3 or less active loop ports. 11.2 Latency The latency that a cell assumes an empty queue, SYSCLK = 80MHz, Any-PHY clocks = 52MHz, measure from SOP of the Any-PHY WAN/Loop receive interface to the SOP Any-PHY WAN transmit interface Minimum Latency = 2340ns. 11.3 CDV There are many points in the S/UNI APEX where CDV can be introduced.
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REGISTER Please use the List of Registers as a reference for the register map. Notes on Register Bits: 1. Writing values into unused register bits has no effect. However, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. Reading back unused bits can produce either a logic one or a logic zero; hence, unused register bits should be masked off by software when read. 2. Writable normal mode register bits are cleared to logic zero upon reset unless otherwise noted. 3. Writing into read-only normal mode register bit locations does not affect S/UNI APEX operation unless otherwise noted. 4. Certain register bits are reserved. These bits are associated with megacell functions that are unused in this application. To ensure that the S/UNI APEX operates as intended, reserved register bits must be written with their default value as indicated by the register bit description. 5. S/UNI APEX is addressable on a long-word basis only. Data fields are loaded into S/UNI APEX registers as described in each specific register section. S/UNI APEX does not perform any byte swapping. 6. With the exception of the CBI register port, part of the RAMBIST, and the Reset and Identity register, all registers are inaccessible until the software reset bit in the Reset and Identity register is removed.
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12.1 General Configuration and Status Register 0x00: Reset and Identity Bit 31:8 7 6:4 3:0 ID[3:0] The ID bits can be read to provide a binary number indicating the S/UNI APEX feature version. These bits are incremented only if features are added in a revision of the chip. Type[2:0] The TYPE bits can be read to distinguish the S/UNI APEX from the other members of the DSLAM family of devices. Reset The RESET bit allows the S/UNI APEX to be reset under software control. If the RESET bit is a logic one, the entire S/UNI APEX except for the microprocessor interface is held in reset. This bit is not self-clearing. Therefore, a logic zero must be written to bring the S/UNI APEX out of reset. Holding the S/UNI APEX in a reset state places it into a low power, stand-by mode. A hardware reset sets the RESET bit, thus negating the software reset. Notes: 1) Software should ensure that the DllRun in the CBI register port reads back a 1 before releasing the S/UNI APEX from reset. 2) Software should wait 2 clock periods of the slowest clock (WTCLK, WRCLK, LTCLK, LRCLK, SYSCLK) before attempting to write to any other register. Exception to this rule is the CBI register port. R/W R R Type Function Unused Reset Type[2:0] ID[3:0] Default 0 1 001 0
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Register 0x10: Hi Priority Interrupt Status Register Bit 31 30:15 14 13 12 11 10 9 8 7:5 4 3:2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Type R/W Function Reserved Unused WTCellXfErr WRRuntCellErr WRParErr Unused LTCellXfErr LRRuntCellErr LRParErr Unused QFreeCntZeroEr r Unused SSRAMParErr SDRAMCrcErr 0 0 0 0 0 0 0 0 0 0 0 0 Default 0
Each bit in the register is masked with the high priority interrupt mask register. The results are then NOR'd together to produce the state of INTHIB pin. All bits are cleared when this register is read. All may be set to one by the microprocessor for interrupt testing. Note that if the interrupt condition persists, the associated status bit will be reasserted. SDRAMCrcErr This bit goes high when a CRC-16 error was detected during a transaction on the SDRAM interface. SSRAMParErr This bit goes high when a parity error was detected during a transaction on the SSRAM interface. QFreeCntZeroErr This bit goes high when the entire device is completely congested, and that there is no more memory left to accept one more cell.
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LRParErr Loop receive parity error detected. LRRuntCellErr Loop receive runt cell error detected. A SOP is detected prior to receiving enough bytes for a cell. LTCellXfErr Loop transmit cell transfer error was encountered. This interrupt status is asserted when an external master device selects the Loop transmit interface for a cell transfer when the FIFO is empty. WRParErr WAN receive parity error detected. WRRuntCellErr WAN receive runt cell error detected. A SOP is detected prior to receiving enough bytes for a cell. WTCellXfErr WAN transmit cell transfer error was encountered. This interrupt status is asserted when an external master device selects the WAN transmit interface for a cell transfer when the FIFO is empty.
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Register 0x14: High Priority Interrupt Mask Bit 31:0 Mask[31:0] These bits mask the High Priority Interrupt Status Register. Type R/W Function Mask[31:0] Default FFFFFFFF
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Register 0x18: Low Priority Interrupt Error Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15:0 R/W R/W R/W Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Function Reserved QShp3IctrErr Reserved QShp2IctrErr Reserved QShp1IctrErr Reserved QShp0IctrErr QDirMaxThrshErr QPortMaxThrshErr QClassMaxThrshErr QVcMaxThrshErr Unused QCellRxErr QVcReasLenErr QVcReasTimeErr Unused Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Each bit in the register is masked with the low priority interrupt mask register. The results are then NOR'd together with the other low priority interrupt register to produce the state of INTLOB pin. All parameters are cleared when this register is read. All parameters may be set to one by the microprocessor for interrupt testing. QVcReasTimeErr Watch Dog found a re-assembled VC that timed out. The Misc Error Context Structure VcReasLenErrICI parameter has been updated to indicate the ICI of the frame that encountered this error. All cells in the re-assembly queue have been re-allocated. The next cell to arrive will be considered the BOM.
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QVcReasLenErr Maximum length in the re-assembly queue has been encountered. The Misc Error Context Structure VcReasLenErrICI parameter has been updated to indicate the ICI of the frame that encountered this error. All cells in the reassembly queue have been re-allocated. PPD has been invoked on the VC. QCellRxErr Status bit indicating that a cell was received on a VC that was not enabled. Caused when either VcEn, ClassEn or PortEn are not set in the context record. The Misc Error Context Structure CellRxErrICI parameter has been updated to indicate the ICI of the cell that encountered this error. QVcMaxThrshErr Status bit indicating that a VC has reached the VC maximum threshold of VcMaxThrsh. The Maximum Congestion ID Misc Context Structure VcMaxThrshErrICI parameter has been updated to indicate the ICI of the cell that encountered this error. QClassMaxThrshErr Status bit indicating that a class queue has reached the class maximum threshold ClassMaxThrsh. The Maximum Congestion ID Misc Context ClassMaxThrshErrID & ClassMaxThrshErrPortID parameters have been updated to indicate the Port and class of the cell that encountered this error. QPortMaxThrshErr Status bit indicating that a port queue has reached the port maximum threshold PortMaxThrsh. The Maximum Congestion ID Misc Context Structure PortMaxThrsh parameter has been updated to indicate the PortID of the cell that encountered this error. QDirMaxThrshErr Status bit indicating that the per-direction maximum congestion threshold has be encountered. Check LoopCnt and WANCnt in the Overall Count Misc Context to determine whether it was the loop or the WAN ports that reached this threshold. QShpNIctrErr, N = 0..3 Status bit indicating that the ingress counter has saturated.
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Register 0x1C: Low Priority Interrupt Error Mask Bit 31:0 Mask[31:0] These bits mask the Low Priority Interrupt Status Register. Type R/W Function Mask[31:0] Default FFFFFFFF
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Register 0x20: Low Priority Interrupt Status Register Bit 31:7 6 5 4 3:0 R R R R Type Function Unused MPIdleStatus SarRxEmptyStatus SarRxRdyStatus SarTxRdyStatus[3:0] Default 0 1 1 1 0
Each bit in the register is masked with the low priority interrupt status mask register. The results are then NOR'd together with the other low priority interrupt register to produce the state of INTLOB pin. SarTxRdyStatus[3:0] Status bit indicating that one of four SAR read buffers contains a least one cell for reading. Warning: Software should not attempt to read this status or clear the associated interrupt mask immediately after extracting a cell from the S/UNI APEX. There is a latency of 3 BCLKs + 2 SYSCLKs between the last word of a cell read out and this signal going inactive. Removing the mask prematurely may generate an unintentional interrupt. SarRxRdyStatus Status bit indicating that SAR receive buffer is ready to accept the next cell. SarRxEmptyStatus Status bit indicating that SAR receive buffer is empty. Typically used for diagnostic writes. Warning: Software should not attempt to read this status or clear the associated interrupt mask immediately after injecting a cell into the S/UNI APEX. There is a latency of 5 SYSCLKs between the last word of a cell written out and this signal going inactive. Removing the mask prematurely will generate an unintentional interrupt. MPIdleStatus Status bit indicating the memory port is idle and ready to accept a new command. This signal is the inverse of MPBusy found in the Memory Port Control Register.
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Register 0x24: Low Priority Interrupt Status Mask Bit 31:0 Mask[31:0] These bits mask the Low Priority Interrupt Status Register. Type R/W Function Mask[31:0] Default FFFFFFFF
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12.2 Loop Cell Interface Register 0x100: Loop Cell Rx Interface Configuration Bit 31:18 17:16 15:13 12:8 7 6 5 4 3 2:1 0 R/W R/W R/W R/W R/W R/W R/W R/W Type Function Unused LoopRxICISel[1:0] Unused LoopRxPollAddr[4:0] LoopRxParPolarity LoopRx8bitEn LoopRxHecDis Unused LoopRxICIPreEn LoopRxMode[1:0] LoopRxEn Default 0 0 0 0 0 0 0 0 1 0 0
All parameters in this register should only be set once at the same time the interface is enabled. Once the interface is set, none of these parameters may be changed. LoopRxEn The LoopRxEn enables the loop receive interface. When set to one, the loop receive Any-PHY interface operates normally. Once set, this bit should not be reset to zero. LoopRxMode[1:0] Selects the receive interface mode LoopRxMode[1:0] 00 01 10 11 Operation UTOPIA L2 master, supports 32 PHYs UTOPIA L1 master, supports 1 PHY Any-PHY master mode inband port notification via the address prepend. Supports 32 PHYs. UTOPIA L2 slave
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LoopRxICIPreEn: When set to one, the default, an ICI prepend (Word 1 in Figure 3, Byte 1&2 in Figure 4) is expected on this interface. When reset to zero an ICI prepend is not expected on this interface. When in 8 bit mode, this bit must be set to 1. LoopRxHecDis When reset to zero, the HEC/UDF field (Word 4 in Figure 3, Byte 7 in Figure 4) is expected on this interface. When set to a one an HEC/UDF field is not expected on this interface. LoopRx8bitEn When reset to zero, this bit sets the interface bus width to 16 bits. When set to one, this bit sets the interface bus width to 8 bit. LoopRxParPolarity When reset to zero, the loop receive parity is odd. When set to one, the loop receive parity is even. LoopRxPollAddr[4:0] In UTOPIA L2 slave mode: The five bit UTOPIA Address to which the slave will respond. In Any-PHY and UTOPIA L2 master mode: These bits represents the polling address range. LoopRxPollAddr[4:0] 0-2 3 ... Polling range Not valid Address 3->0 ...
31 Address 31->0 In UTOPIA L1 master mode: These bits are reserved. LoopRxICISel[1:0] Indicates which part of the incoming cell, the internal ICI is selected from: LoopICISel[1:0] 00 01 Source User Prepend (Note: LoopRxICIPreEn must be set). VPI/VCI fields: if VPI < "FFF" then
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ICI = "0" & VPI; else ICI = VCI; end if; 10 HEC/UDF fields (Note: Both LoopRxHecDis and LoopRx8bitEn must be clear, and not valid for 8-bit mode). Unused
11
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Register 0x104: Loop Cell Tx Interface Configuration Bit 31 30:29 28:24 23:22 21 20 19:13 12:8 7 6 5 4 3 2:1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Type R Function LoopTxPfFullStatus Unused LoopTxPfThres Unused LoopTxTwoCellEn LoopTxSchEn Unused LoopTxSlaveAddr[4:0] LoopTxParPolarity LoopTx8bitEn LoopTxHecDis LoopTxSwitchPreEn LoopTxECIPreEn LoopTxMode[1:0] LoopTxEn Default 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
All parameters in this register should only be set once at the same time the interface is enabled. Once the interface is set, none of these parameters may be changed. LoopTxEn The LoopTxEn enables the loop transmit interface. When set to one, the loop transmit Any-PHY interface operates normally. Once set, this bit should not be reset to zero. LoopTxMode[1:0] Selects the transmit interface mode. LoopTxMode[1:0] 00 01 Operation UTOPIA L2 master mode, supports 32 PHYs UTOPIA L1 master mode, supports 1 PHY
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LoopTxMode[1:0] 10 11
Operation Any-PHY master mode inband port selection, via the address prepend. Supports 2048 PHYs. UTOPIA L2 slave
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LoopTxECIPreEn: When reset to zero, a ECI prepend (Word 2 in Figure 5, Byte 3&4 in Figure 6) is not present on this interface. When set to one a ECI prepend is present on this interface. LoopTxSwitchPreEn When reset to zero, a switch tag prepend (Word 1 in Figure 5, Byte 1&2 in Figure 6) is not present for this interface. When set to a one a switch tag is present for this interface. LoopTxHecDis When reset to zero, the ECI is generated on the HEC/UDF field (Word 5 in Figure 5, Byte 9 in Figure 6) in this interface. When set to a one an HEC/UDF field is not generated on this interface. LoopTx8bitEn When reset to zero, this bit sets the interface bus width to 16 bits. When set to one, this bit sets the interface bus width to 8 bit. LoopTxParPolarity When reset to zero, the loop transmit parity is odd. When set to one, the loop transmit parity is even. LoopTxSlaveAddr[4:0] The five bit UTOPIA Address to which the slave will respond. Used only when the loop Tx interface is configured for UTOPIA L2 slave. LoopTxSchEn The LoopTxSchEn enables the loop port scheduler for normal operation. The LoopTxSchEn enable should be set to a `1' for normal operation after the initialization of the loop's class not empty context memory. LoopTxTwoCellEn When set to 0, the loop port scheduler will allow a maximum one cell per port in the transmit pipeline for each LTPA. When set to 1, the loop port scheduler will allow a maximum of two cells per port in the transmit pipeline for each LTPA. LoopTxPfThres[4:0] Controls the depth of the poll request FIFO, offset by 1. A value of 0 represents poll depth of 1. Recommended value is 0x1f.
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LoopTxPfFullStatus Read only bit. When read high, it indicates that the polling FIFO has reached the LoopTxPfThres value. Reading this bit will reset the value to zero. Used for diagnostics. 12.3 WAN Cell Interface Register 0x200: WAN Cell Rx Interface Configuration Bit 31:18 17:16 15:13 12:10 9:8 7 6 5 4 3 2:1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Type Function Unused WANRxICISel[1:0] Unused Reserved WANRxPollAddr[1:0] WANRxParPolarity WANRx8bitEn WANRxHecDis Unused WANRxICIPreEn WANRxMode[1:0] WANRxEn Default 0 0 0 0 0 0 0 0 0 1 0 0
All parameters in this register should only be set once at the same time the interface is enabled. Once the interface is set, none of these parameters may be changed. WANRxEn The WANRxEn enables the WAN receive interface. When set to one, the WAN receive Any-PHY interface operates normally. Once set, this bit should not be reset to zero. WANRxMode[1:0] Controls the port selection mode. WANRxMode[1:0] 00 Operation UTOPIA L2 master, supports 4 PHYs
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WANRxMode[1:0] 01 10 11 WANRxICIPreEn
Operation UTOPIA L1 master, supports 1 PHY Any-PHY master mode inband port notification via the address prepend. Supports 4 PHYs. UTOPIA L2 slave
When set to one, the default, an ICI prepend (Word 1 in Figure 3, Byte 1&2 in Figure 4) is expected on this interface. When reset to zero an ICI prepend is not expected on this interface. When in 8-bit mode, this bit must be set to 1. WANRxHecDis When reset to zero, the HEC/UDF field (Word 4 in Figure 3, Byte 7 in Figure 4) is expected on this interface. When set to a one an HEC/UDF field is not expected on this interface. WANRx8bitEn When reset to zero, this bit sets the interface bus width to 16 bits. When set to one, this bit sets the interface bus width to 8 bit. WANRxParPolarity When reset to zero, the WAN receive parity is odd. When set to one, the WAN receive parity is even. WANRxPollAddr[1:0] In UTOPIA L2 slave mode: The two bit UTOPIA Address to which the slave will respond. In Any-PHY and UTOPIA L2 master mode: These bits represents the polling address range. WANRxPollAddr[1:0] 0-2 Polling range Not valid
3 Address 3->0 In UTOPIA L1 master mode: These bits are reserved. WANRxICISel[1:0] Indicates which part of the incoming cell, the internal ICI is selected from:
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WANRxICISel[1:0] 00 01
Source User Prepend (Note: WANRxICIPreEn must be set). VPI/VCI fields: if VPI < "FFF" then ICI = "0" & VPI; else ICI = VCI; end if;
10
HEC/UDF fields (Note: Both WANRxHecDis and WANRx8bitEn must be clear, and not valid for 8-bit mode). Unused
11
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Register 0x204: WAN Cell Tx Interface Configuration Bit 31:30 29:28 27:26 25:24 23:21 20 19:10 9:8 7 6 5 4 3 2:1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Type R/W R/W R/W R/W Function WANTx3PortID[1:0] WANTx2PortID[1:0] WANTx1PortID[1:0] WANTx0PortID[1:0] Unused WANTxSchEn Unused WANTxSlaveAddr[1:0] WANTxParPolarity WANTx8bitEn WANTxHecDis WANTxSwitchPreEn WANTxECIPreEn WANTxMode[1:0] WANTxEn Default 3 2 1 0 0 0 0 0 0 0 0 0 1 0 0
All parameters in this register should only be set once at the same time the interface is enabled. With the exception of the WANTxXPortID and WANTxSlaveAddr bits, once the interface is set, none of these parameters may be changed. WANTxEn The WANTxEn enables the WAN transmit interface. When set to one, the WAN transmit Any-PHY interface operates normally. Once set, this bit should not be reset to zero. WANTxMode[1:0] Controls the port selection mode. WANTxMode[1:0] 00 01 Operation UTOPIA L2 master, supports 4 PHYs UTOPIA L1 master , supports 1 PHY
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WANTxMode[1:0] 10 11 WANTxECIPreEn
Operation Any-PHY master mode inband port notification via the address prepend. Supports 4 PHYs. UTOPIA L2 slave
When reset to zero, an ECI prepend (Word 2 in Figure 5, Byte 3&4 in Figure 6)is not generated on this interface. When set to one an ECI prepend is generated on this interface. WANTxSwitchPreEn When reset to zero, a switch tag prepend (Word 1 in Figure 5, Byte 1&2 in Figure 6) is not generated for this interface. When set to a one a switch tag prepend is generated for this interface. WANTxHecDis When reset to zero, the ECI is generated on the HEC/UDF field (Word 5 in Figure 5, Byte 9 in Figure 6) in this interface. When set to a one an HEC/UDF field is not generated on this interface. WANTx8bitEn When reset to zero, this bit sets the interface bus width to 16 bits. When set to one, this bit sets the interface bus width to 8 bit. WANTxParPolarity When reset to zero, the WAN transmit parity is odd. When set to one, the WAN transmit parity is even. WANTxSlaveAddr[1:0] In UTOPIA L2 slave mode : The two bit UTOPIA address to which the slave will respond. In UTOPIA L1 master mode: The two bit UTOPIA address that is presented during the address selection phase. Permits an external UTOPIA L2 slave to be connected when interface is in UTOPIA L1 master mode. WANTxSchEn The WANTxSchEn enables the WAN port scheduler for normal operation. The WANTxSchEn enable should be set to a `1' for normal operation after the initialization of the WAN's class not empty context memory.
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WANTxXPortID[1:0], X = 0..3 representing channel #. The value in these register are the alias mapping of the internal WAN PortID to the physical port ID as presented by the Any-PHY/UTOPIA master mode interface. By default, the internal matches the external port IDs. In slave mode, the WAN port scheduler only operates on Port 0; therefore, the following relationship must always be true: WANTx0PortID = WANTxSlaveAddr Warning: the values programmed into these four registers must always be unique. Two or more internally active PortID must never point to the same active physical port ID.
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12.4 Memory Port See section on Memory Port Mapping for specific context parameter definitions. Register 0x300: Memory Port Control Bit 31 30:29 28 27:24 23:22 21:18 17:0 R/W R/W R/W Type R/W R/W Function MPBusy MPCommand[1:0] Unused MPLWordEn[3:0] MPMemSelect[1:0] Unused MPQuadAddr[17:0] 0 0 0 0 Default 0 0
Writes to this register will place the microprocessor interface in wait state until the MPBusy bit in the control register is clear. MPQuadAddr[17:0] Indicates the beginning quad long word address for the operation in memory. Up to 4 megabytes of memory is supported in each aperture by this address (or 256k 16-byte regions). MPMemSelect[1:0] Selects the memory aperture. The aperture is chosen according to the following table. MPMemSelect[1:0] 00 01 10 11 MPLWordEn[3:0] Indicates which long words of data will be written to or read from memory. This register is used to resolve the quad long word address MPQuadAddr down to long word resolution. Aperture Selected External Queue Context Internal Queue Context Internal WAN Port Context Internal Loop Port Scheduler Context
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For masked writes, only one bit should be set, identifying the long word address. If more than one bit in this parameter is set then the least significant active bit will be used to indicate the long word address to be modified. For normal read/write access, the number of active bits permitted is unrestricted with the exception of the internal WAN port scheduler context memory map and internal loop port scheduler context memory map. These 2 memory maps are restricted to having only 1 active bit per access. MPCommand[1:0] Selects the type of access. If a masked write is indicated, a 34-bit mask will be used to determine which bits within one long word will be written. MPCommand[1:0] 00 01 10 11 MPBusy When set to a one by the microprocessor, the command will be executed. When the command is complete, this bit will be cleared to zero. This signal is the inverse of MPIdleStatus found in the Interrupt Status Register. Command Selected Reserved Write Read Masked Write
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Register 0x340-0x34C: Memory Write Data (Burstable) Bit 31:0 Type R/W Function MPWrDataN[31:0], N = 0..3 Default 0
Writes to this register will be delayed until the MPBusy bit in the control register is clear. MPWrDataN[31:0], N = 0..3 The least significant 32 bits of write data to be directed to the address and aperture as specified in the memory port control register. For normal write operations, MPWrDataN corresponds to MPLWordEn[N]. For masked writes, MPWrData0 contains the data, MPWrData1 contains the mask bits: only bits set to a one in this vector will be overwritten with MPWrData0 in memory.
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Register 0x350: Memory Write Data Overflow (Burstable) Bit 31:8 7:6 5:4 3:2 1:0 R/W R/W R/W R/W Type Function Unused MPWrData3[33:32] MPWrData2[33:32] MPWrData1[33:32 MPWrData0[33:32] Default 0 0 0 0 0
Writes to this register will be delayed until the MPBusy bit in the control register is clear. This register is only used for writes to the external queue context. MPWrData0[33:32] The most significant 2 bits of MPWrData0. See Memory Write Data array for a more detailed description. MPWrData1[33:32] The most significant 2 bits of MPWrData1. See Memory Write Data array for a more detailed description. MPWrData2[33:32] The most significant 2 bits of MPWrData2. See Memory Write Data array for a more detailed description. MPWrData3[33:32] The most significant 2 bits of MPWrData3. See Memory Write Data array for a more detailed description.
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Register 0x380-0x38C: Memory Read Data (Burstable) Bit 31:0 Type R Function MPRdDataN[31:0] , N = 0..3 Default 0
Reads from this register will be delayed until the MPBusy bit in the control register is clear. MPRdDataN[31:0], N = 0..3 The least significant 32 bits of read data from the address and aperture as specified in the memory port control register. MPRdDataN corresponds to MPLWordEn[N].
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Register 0x390: Memory Read Data Overflow (Burstable) Bit 31:8 7:6 5:4 3:2 1:0 R R R R Type Function Unused MPRdData3[33:32] MPRdData2[33:32] MPRdData1[33:32] MPRdData0[33:32] Default 0 0 0 0 0
Reads from this register will be delayed until the MPBusy bit in the control register is cleared. This register is only used for reads from external queue context. MPRdData0[33:32] Indicates the most significant 2 bits of the first word of read data from memory. See Memory Read Data array for a more detailed description. MPRdData0[33:32] Indicates the most significant 2 bits of the first word of read data from memory. See Memory Read Data for a more detailed description. MPRdData1[33:32] Indicates the most significant 2 bits of the second word of read data from memory. See Memory Read Data for a more detailed description. MPRdData2[33:32] Indicates the most significant 2 bits of the third word of read data from memory. See Memory Read Data for a more detailed description. MPRdData3[33:32] Indicates the most significant 2 bits of the fourth word of read data from memory. See Memory Read Data for a more detailed description.
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12.5 SAR 12.5.1 Receive In normal SAR operation, writing to any SAR receive data register when SarRxRdyStatus = 0 (in the low priority interrupt status register) will cause the microprocessor bus to be held in wait state. Data transfer is initiated when SarRxData13 is written. When in diagnostic write mode, writing to any SAR receive data register when SarRxEmptyStatus = 0 (in the low priority interrupt status register) will cause the microprocessor bus to be held in wait state. Data transfer is initiated when SarRxData15 is written. Register 0x400-0x43C: SAR Receive Data (Burstable) Bit 31:0 Type W Function SarRxDataN[31:0], N = 0..15 Default X
SarRxData0[15:0]: ICI In normal SAR operation, this is the Ingress Connection Identifier that identifies the connection in which the cell belongs. In diagnostic write mode, this is simply a write data register. SarRxData0[17:16]: CRC Trailer In normal SAR operation, these bits define whether the next cell received should be over written with a trailer. SarRxData0[17:16] 00 01 10 Function Do not overwrite the end of the current cell with a trailer Write the current cell with CRC-32 trailer. Write the current cell with CRC-10 trailer.
Unused 11 In diagnostic write mode, this is simply a write data register. SarRxData0[18]: CRC-32 Init In normal SAR operation, when set, this bit will set the internal CRC32 to 0xFFFFFFFF. Required when the current cell received is the BOM of an
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AAL5 packet. This bit must be reset if the current cell received is not the BOM of an AAL5 packet. In diagnostic write mode, this is simply a write data register. SarRxData0[31:19] In normal SAR operation, these bits are not used. In diagnostic write modes, this is simply a write data register. SarRxDataN[31:0], N=1..15: In normal SAR operation, these registers contain the header and payload. Data stored in SarRxData14 & SarRxData15 are not used. Transfer is initiated when SarRxData13 is written. In diagnostic write mode, this is simply a write data register. Transfer is initiated when SarRxData15 is written.
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12.5.2 Transmit Reading from any registers within the transmit SAR when SarTxRdyStatus = 0(in the Low Priority Interrupt Status register), or when SarDiagRdBusy = 1 (in the Cell Buffer Diagnostic Control register) will cause the microprocessor bus to be held in wait state. All registers in the transmit SAR are read-only; the registers may not be initialized by the microprocessor directly. All 16 registers in the class 3 transmit SAR buffer are used to report read data when cell buffer diagnostic mode is enabled. In this mode, the entire block of data is cleared from the buffer once the last word is read. Register 0x500-0x53C: SAR Transmit Data, Class 0 (Burstable) Register 0x540-0x57C: SAR Transmit Data, Class 1 (Burstable) Register 0x580-0x5BC: SAR Transmit Data, Class 2 (Burstable) Register 0x5C0-0x5FC: SAR Transmit Data, Class 3 (Burstable) Bit 31:0 Type R Function SarTxDataN[31:0], N = 0..15 Default X
SarTxData0[15:0]: ECI In normal SAR operation. This is the Egress Connection Identifier of the cell received. In diagnostic read mode, class 3, this is the read data. SarTxData0[16]: CRC32 Status In normal SAR operation, when high, this bit indicates that the AAL5 CRC32 polynomial check failed. This bit is only valid for cells that belong to an AAL5 packet (as indicated by the cell header). Within AAL5 packets, this status will return the actual CRC32 status with the EOM, and all other cells will be accompanied by a status of 0. This status should be ignored for all other cell types. In diagnostic read mode, class 3, this is the read data.
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SarTxData0[17]: CRC10Stat In normal SAR operation, when high, this bit indicates that the CRC10 polynomial check failed. This status is only valid when the cell in the buffer is an OAM cell (as indicated by the cell header). This status should be ignored for all other cell types. In diagnostic read mode, class 3, this is the read data. SarTxData0[31:18]: Unused In normal SAR operation, not used. In diagnostic read mode, class 3, this is the read data. SarTxDataN[31:0], N=1..15: In normal SAR operation, these registers contain the header and payload. For Data stored in SarTxData14 & SarTxData15 are reserved and are not used. A new transfer is initiated when SarTxData13 is read. In diagnostic read mode, class 3, these registers are the read data. A new transfer is initiated when SarTxData15 is read. 12.5.3 Cell Buffer Diagnostic Access Register 0x600: Cell Buffer Diagnostic Control Bit 31 30 29 28 27:18 17:0 R/W Type R/W R/W R R/W Function SarDiagRdBusy SarDiagRdModeEn SarDiagRdModeLock SarDiagWrModeEn Unused SarDiagAddr[17:0] Default 0 0 0 0 0 0
SarDiagAddr[17:0] Indicates the beginning 16-long word address for the operation in cell buffer. Up to 16 megabytes of memory is supported by this address (or 256k 64-byte regions).
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SarDiagWrModeEn When enabled, the SAR receive staging buffer will be used as a port to write data directly to the cell buffer (SDRAM). Receiving of normal cells into the traffic stream is no longer possible while this parameter is enabled. This bit should only be set when SarRxEmptyStatus = 1 in the low interrupt status register. SarDiagRdModeLock Read only. Indicates that the SAR is ready to perform a diagnostic reads. A lock will only occur when SarDiagRdModeEn = 1, and all non-diagnostic cells remaining in the class 3 Tx staging buffers have been read by the microprocessor. SarDiagRdModeEn When enabled, normal loading of cells into all 4 classes of the SAR Tx staging buffers are withheld. A cell that is in the process of being loaded into a Tx staging buffer when this bit is set will be allowed to complete. SarDiagRdBusy Setting this register to one will initiate a diagnostic read from the cell buffer (SDRAM). When the command is complete, this bit will be cleared to zero. This bit should not be set to one until SarDiagRdModeEn = 1, SarDiagRdModeLock = 1, and SarTxRdyStatus = 0. 12.6 Queue Engine Register 0x700: Queue Context Configuration Bit 31 30 29 28:27 26 25 24 23:16 15:8 R/W R/W R/W R/W Type R/W R R/W Function QEngEn QBusy QSglStep Unused QRxTxArbSel Unused QNumVCSel QCellStartAdr[7: 0] QLClassStartAdr Default 0 0 0 0 0 0 0 0 0
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Bit 7:0
Type R/W
Function [7:0] QShpStartAdr[7: 0]
Default 0
QShpStartAdr[7:0] Defines the memory port starting 4 long word address for traffic shaping records in the SSRAM context memory. Units in K values. Warning: This value must not change while the queue engine is enabled. QLClassStartAdr[7:0] Defines the memory port starting 4 long word address for loop class records in the SSRAM context memory. Units in K values. Warning: This value must not change while the queue engine is enabled. QCellStartAdr[7:0] Defines the memory port starting 4 long word address for cell records in the SSRAM context memory. Units in K values Warning: This value must not change while the queue engine is enabled. QNumVCSel Selects the maximum number of VCs. When QNumVCSel = 0, a maximum of 64K VCs is supported. When QNumVCSel = 1, a maximum of 16K VCs is supported Warning: This value must not change while the queue engine is enabled. Warning: When only 16K VCs are enabled, only the first 14 LSB of the ICI is used to identify the cells. The remaining 2 MSB are ignored. QRxTxArbSel Selects between 2 arbitration schemes. When QRxTxArbSel = 0, RR is used to select between WAN, Loop and SAR. When QRxTxArbSel = 1, RR is used to select between WAN and Loop, and SAR having low priority. QSglStep Forces the queue engine to process the winner of the service arbitration and then halt. When invoked, the register QEngEn will be set to one. When
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QBusy returns a one, both QEngEn and QSglStep will be reset back to zero. To be used only for diagnostics. QBusy Status signal indicating that the queue engine is currently active. QEngEn The QEngEn enables the queue engine for normal operation. When QEngEn = 0 and QBusy = 0, all queue engine operations are disabled. The QEngEn should be set to a `1' for normal operation after the initialization of the S/UNI APEX and the S/UNI APEX's Context Memory. This register will reset to zero if QSglStep is invoked.
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Register 0x704: Receive and Transmit Control Bit 31:14 13 12 11:10 9 8 7:5 4 3:1 0 QWANTxDis When setting this bit to one, all cell request by the WAN transmit interface will be ignored. QLoopTxDis When setting this bit to one, all cell request by the Loop transmit interface will be ignored. QWANRxDis When setting this bit to one, all cell request by the WAN receive interface will be ignored. QWANRxFilter When setting this bit to one, only uP destined cells received via the WAN receive interface will be serviced. Cells destined for the WAN or Loop will be discarded and the general discard count incremented. Used when the device is in redundent mode QLoopRxDis When setting this bit to one, all cell request by the Loop receive interface will be ignored. R/W R/W R/W R/W R/W R/W Type Function Unused QLoopRxFilter QLoopRxDis Unused QWANRxFilter QWANRxDis Unused QLoopTxDis Unused QWANTxDis Default 0 0 0 0 0 0 0 0 0 0
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QLoopRxFilter When setting this bit to one, only uP destined cells received via the Loop receive interface will be serviced. Cells destined for the WAN or Loop will be discarded and the general discard count incremented. Used when the device is in redundent mode
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Register 0x710: Max Direction Congestion Thresholds Bit 31:24 23:16 15:8 7:0 R/W R/W Type Function Unused QLoopMaxThrsh [7:0] Unused QWANMaxThrsh [7:0] Default 0 0 0 0
This register contains all the maximum per-Direction congestion threshold values for the WAN and Loop ports. Please refer to section 14.2 for a complete definition of m bit logarithmic, n bit fractional. QWANMaxThrsh[7:0] Sets the maximum threshold for cells destined for all 4 WANs combined. 4 bit logarithmic, 4 bit fractional. QLoopMaxThrsh[7:0] Sets the maximum threshold for cells destined for all 2K Loops combined. 4 bit logarithmic, 4 bit fractional.
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Register 0x714: CLP0 Direction Congestion Thresholds Bit 31:27 23:16 15:8 7:0 R/W R/W Type Function Unused QLoopCLP0Thrs h [7:0] Unused QWANCLP0Thr sh [7:0] Default 0 0 0 0
This register contains all the CLP0 per-Direction congestion threshold values for the WAN and Loop ports. Please refer to section 14.2 for a complete definition of m bit logarithmic, n bit fractional. QWANCLP0Thrsh[7:0] Sets the EPD threshold for CLP0 cells destined for all 4 WANs combined. 4 bit logarithmic, 4 bit fractional. QLoopCLP0Thrsh[7:0] Sets the EPD threshold for CLP0 cells destined for all 2K Loops combined. 4 bit logarithmic, 4 bit fractional.
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Register 0x718: CLP1 Direction Congestion Thresholds Bit 31:27 23:16 15:11 7:0 R/W R/W Type Function Unused QLoopCLP1Thrs h [7:0] Unused QWANCLP1Thr sh [7:0] Default 0 0 0 0
This register contains all the CLP1 per-Direction congestion threshold values for the WAN and Loop ports. Please refer to section 14.2 for a complete definition of m bit logarithmic, n bit fractional. QWANCLP1Thrsh[7:0] Sets the EPD threshold for CLP1 cells destined for all 4 WANs combined. 4 bit logarithmic, 4 bit fractional. QLoopCLP1Thrsh[7:0] Sets the EPD threshold for CLP1 cells destined for all 2K Loops combined. 4 bit logarithmic, 4 bit fractional.
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Register 0x71C: Re-assembly Maximum Length Bit 31:10 9:0 R/W Type Function Unused QReasMaxLen[9 :0] Default 0 0
QReasMaxLen[9:0] Defines the alternate re-assembly maximum length, in cells. When a VC has frame continuous queuing, the VC context parameter VcReasMaxSize = 1, and the VC's frame length exceeds this register, an EPD will be invoked.
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Register 0x720: Watch Dog ICI Patrol Range Bit 31:16 15:0 Type R/W R/W Function QWdEndICI[15: 0] QWdStartICI[15: 0] Default 0 0
QWdStartICI[15:0] Identifies the first ICI to be checked for re-assembly time-outs. Warning: This value must not change while a patrol is active. QWdEndICI[15:0] Identifies the last ICI to be checked for re-assembly time-outs. Warning: This value must not change while a patrol is active.
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Register 0x724: Tear Down Queue ID Bit 31:16 15:4 3:2 1:0 R/W Type R/W R/W Function QTdICI[15:0] QTdPortID[11:0] Unused QTdClassID[1:0] Default 0 0 0 0
QTdClassID[3:0] Identifies the class to be torn down from service. Used only when tearing down a class. Warning: This value must not change while a tear down is active. QTdPortID[11:0] Identifies the port id of the class queue that is to be torn down from service. Used only when tearing down a class. See VC Context Record for PortID encoding. Warning: This value must not change while a tear down is active. QTdICI[15:0] Identifies the VC queue that is to be torn down from service. Used only when tearing down a VC. Warning: This value must not change while a tear down is active.
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Register 0x728: Watch Dog / Tear Down Status Bit 31:6 5 4 3:1 0 QWdActive When setting this bit to one, the watch dog will begin its patrol. When the patrol is over, this bit will reset to zero. This bit cannot be reset to zero by the microprocessor. QTdActive When setting this bit to one, the tear down macro, as defined in the QTdMode, will be initiated. When the macro has completed its tear down, this bit will reset to zero. This bit cannot be reset to zero by the microprocessor. QTdMode When setting this bit to zero, a tear down macro will remove a VC queue, as identified in the Tear Down Queue ID register, from service, re-allocate the buffers in the queue, and update the general discard count. When setting this bit to a one, a tear down macro will remove a class queue, as identified in the Tear Down Queue ID register, from service, re-allocate the buffers in the queue, and update the general discard count. Warning: This value must not change while a tear down is active. Warning: 1) Tearing down a class queue should only be done after all the VCs within the class has been torn down first. 2) After performing a VC tear down, do not setup another VC until either the class queue has been torn down or drain the class queue until VcClassQCLP01Cnt = 0. Failure to do this will result in anomalies in the new VC, such as inaccurate VC weights (for WFQ VCs) and premature discard at the per-VC hierarchical level. R/W(1) R/W R/W(1) Type Function Unused QTdMode QTdActive Unused QWdActive Default 0 0 0 0 0
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Register 0x730: Shaper 0 Configuration (N = 0) Register 0x734: Shaper 1 Configuration (N = 1) Register 0x738: Shaper 2 Configuration (N = 2) Register 0x73C: Shaper 3 Configuration (N = 3) Bit 31 30:29 28:20 R/W Type R Function QShpNExpCong unused QShpNRTRate[8: 0], N = 0..3 Unused R/W QShpNRedFact[1 :0] , N = 0..3 QShpNThrshVal[ 3:0] , N = 0..3 QShpNMeasInt[3: 0] , N = 0..3 QShpNClass[1:0] , N = 0..3 QShpNPort[1:0] , N = 0..3 Unused R/W R/W QShpNThrshEn, N = 0..3 QShpNSlowDow nEn, N = 0..3 QShpNEn, 0 Default 0
19:18 17:16
0 0
15:12
R/W
0
11:8
R/W
0
7:6
R/W
0
5:4 3 2 1
R/W
0 0 0 0
0
R/W
0
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Bit
Type
Function N = 0..3
Default
There are four shapers, N = 0..3. Each shaper can be assigned to the same port, or can be assigned to different ports. Only one shaper may be assigned to any one port/class combination. Only WAN ports may be shaped. If a port/class combination is to be shaped, the VcQueue parameter defined in the VC context record structure will be overridden. Note: If one or more shaper is enabled, then all 4 registers must be programmed with unique port/class combinations. QShpNEn, N=0..3 Enable for shaper N. Warning: This register can only be modified during a port/class setup, and when the queue engine is disabled. QShpNSlowDownEn, N=0..3 Enables the slow down of the time reference clock used by shaper N to calculate transmission events. Enabling this feature will provide fair shaping to high speed VCs QShpNThrshEn, N=0..3 Defines how congestion is to be declared for shaper N. When set to zero, the declaration is based on the comparison between the current class queue length and the number of cells leaving the class queue over the previous measurement period. When set to one, the declaration is based on the comparison between the current class queue length and the QShpThrshVal. This register has no effect if QShpNSlowDownEn = 0. QShpNPort[1:0]; N=0..3 WAN Port that shaper N is linked to. Warning: This register can only be modified during a port/class setup, and when the queue engine is disabled.
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QShpNClass[1:0], N=0..3 Class that shaper N is associated with. Warning: This register can only be modified during a port/class setup, and when the queue engine is disabled. QShpNMeasInt[3:0], N=0..3 Encoded value defining the number of clock cycles over which to measure congestion levels for shaper N. The period defined is not affected by the slow down factor. Encoding formula is 64 * 2^m. This register has no effect if QShpNSlowDownEn = 0. QShpNThrshVal[3:0], N=0..3 Defines a value for the class queue length threshold value. Used to select whether to speed up or slow down the shaper N. Effective value = 2(T+1) - 1, where T = QShpNThrshVal[3:0] This register has no effect if QShpNSlowDownEn = 0 or QShpNThrshEn = 0. QShpNRedFact[1:0], N=0..3 Encoded value for the slow down rate reduction factor. Controls how quickly the shaper N speeds up. Low values will produce better fairness at the cost of utilization. QShpNRedFact[1:0] 0 1 2 3 Effective Value 2 4 8 16
This register has no effect if QShpNSlowDownEn = 0. QShpNRTRate[8:0], N=0..3 Real time rate for shaper N. Represents the maximum shaped data rate, calculated in the number of clock cycles per timeslot. The sum of all active real time rate must be less than the link rate of 1.42Mcells/s. The table below provides the decimal setting for various configurations:
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SYSCLK (MHz) 80 80 40
Max. Shaped Rate 1.42 Mcells/s 355 Kcells/s 355 Kcells/s
QShpNRTRate (decimal) 57 227 114
Max. Active Shapers 1 4 2
where QShpNRTRate = ROUNDUP(SYSCLK (MHz) / Effective Data Rate). QShpNExpCong, N = 0..3 Status bit indicating shaper N has experienced congestion, and that the time slot counter was slowed down. This bit is cleared when this register is read. 12.7 Memory Interface Register 0x800: SDRAM/SSRAM Configuration Bit 31:17 16 15 14:8 7:1 0 CBEn The CBEn enables the SDRAM Interface. A transition from 0 to 1 initiates the SDRAM initialization procedures. This enable is provided to ensure that the power-up time before the initialization sequence is applied to the SDRAM is met. When CBEn = `0', no SDRAM accesses will take place and the chip will not operate properly. CBRefDivide[6:0] Defines the SYSCLK divide down factor to determine the SDRAM refresh rate. Actual divide down value is the value stored in the register multiplied by 16 decimal, plus 1. For example, a value of 78 decimal will produce a refresh cycle every 78*16 + 1 = 1249 SYSCLKs. A zero value is not permitted. R/W R/W R/W Type Function Unused CMLateWrite Unused CBRefDivide[6:0 ] Unused CBEn Default 0 0 0 0 0 0
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CMLateWrite The CMLateWrite selects the type of SSRAM connected. When set to zero, pipelined ZBT SSRAM is configured. When set to one, register to register late write SSRAM is configured. When late write is selected, pins CMAB[18] & CMAB[17] change functionality and become the chip enable bar for odd and even addresses, respectively. 12.8 Test Interface The following registers are for production test only. They should not be invoked while in service. Register 0x900: BIST_OK Bit 31:8 7 6 5 4 3 2 1 0 XXBistOK A high value indicates that the test is complete and that no error has been encountered. For typical BIST operation, sequence of write should be as follows: XXBistEnb = 1, BistMode = 0x4 XXBistEnb = 0, BistMode = 0x2 Wait 16*depth SYSCLKs, where depth is the address space of the deepest RAM under test. This register requires an active SYSCLK to access. R R R R R R R R Type Function Unused McLRBistOK McLTBistOK McWRBistOK McWTBistOK McCRBistOK McCTBistOK ALBistOK QEBistOK Default 0 0 0 0 0 0 0 0 0
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Register 0x904: BIST_Mode Bit 31 30:28 27 26 25 24 23 22 21 20 19:16 15:8 7:3 2:0 BistSide For dual port RAMs, selects the side that is to be tested. When set to 0, PortA will be tested. When set to 1, PortB will be tested. XXBistEnb When set to 0, enables the internal RAMBIST for the RAMs within the specific block. BistTest[7:0] Seed test pattern bus that is replicated over the RAM data bus BistMode Defines the Bist mode of operation. R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Type R/W Function BistSide Unused McLRBistEnb McLTBistEnb McWRBistEnb McWTBistEnb McCRBistEnb McCTBistEnb ALBistEnb QEBistEnb Unused BistTest[7:0] Unused BistMode[2:0] Default 0 0 1 1 1 1 1 1 1 1 0 0 0 0
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Register 0x908: BIST_Results A Bit 31:21 20 19 18:9 8:7 6 5 4:1 0 XXBistResult When BISTEnb is enabled for the specific block, a high value indicates that no errors have been encountered. XXBistEnd A high value indicates the end of the BIST test. XXBistError A high value indicates that the current clock cycle of the RAM undertest has encountered an error. R R R R R R Type Function Unused ALBistResult ALBistEnd ALBistError[9:0] Unused QEBistResult QEBistEnd QEBistError[3:0] Unused Default 0 1 0 0 0 1 0 0 0
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Register 0x90C: BIST_Results B Bit 31:24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 See register BIST_Result A. R R R R R R R R R R R R R R R R R R Type Function Unused McLRBistResult McLRBistEnd McLRBistError Unused McLTBistResult McLTBistEnd McLTBistError Unused McWRBistResult McWRBistEnd McWRBistError Unused McWTBistResult McWTBistEnd McWTBistError Unused McCRBistResult McCRBistEnd McCRBistError Unused McCTBistResult McCTBistEnd McCTBistError Unused Default 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0
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12.9 CBI Interface Register 0xA00: CBI Register Port Bit 31 30 29:16 15:14 13 12 11 10:8 7:0 R/W R/W R/W R/W Type R/W R/W Function CBIBusy CBIRdWrb Unused CBIAddr[1:0] CBITrsb Unused CBITstb Unused CBIData[7:0] Default 0 0 0 0 0 0 1 0 0
Writes to this register will place the microprocessor interface in wait state until the CBIBusy bit is clear. CBIData[7:0] Data value used to write into the CBI port or read from the CBI port. Address specified by CBIAddr[2:0] CBITstb Active low signal used during production testing. Normally set high. CBIAddr[1:0] Address bus used to select the CBI register. CBITrsb Test select bit. Should always be set to 1 during normal mode access. CBIRdWrb Defines whether a read or write to the CBI register is to be performed. When set to 0, a write command is defined. When set to 1 a read command is defined. Command invoked when CBIBusy is set to 1.
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CBIBusy When set to a one, the CBIRdWrb command will be executed. When the command is complete, this bit will be cleared to zero.
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13
CBI REGISTER PORT MAPPING CBI Register 0x00: Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W Type Function Unused Unused Reserved OVERRIDE Unused ERRORE VERN_EN LOCK Default X X 0 0 X X 0 0
The DLL Configuration Register controls the basic operation of the DLL. LOCK: The LOCK register is used to force the DLL to ignore phase offsets indicated by the phase detector after phase lock has been achieved. When LOCK is set to logic zero, the DLL will track phase offsets measured by the phase detector between the SYSCLK and the REFCLK inputs. When LOCK is set to logic one, the DLL will not change the tap after the phase detector indicates of zero phase offset between the SYSCLK and the REFCLK inputs for the first time. VERN_EN: The vernier enable register (VERN_EN) forces the DLL to ignore the phase detector and use the tap number specified by the VERNIER[7:0] register bits. When VERN_EN is set to logic zero, the DLL operates normally adjusting the phase offset based on the phase detector. When VERN_EN is set to logic one, the delay line uses the tap specified by the VERNIER[7:0] register bits. Used only for diagnostics. ERRORE: The ERROR interrupt enable (ERRORE) bit enables the error indication interrupt. When ERRORE is set high, an interrupt is generated upon assertion event of the ERR output and ERROR register. When ERRORE is set low, changes in the ERROR and ERR status do not generate an interrupt.
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OVERRIDE: The override control (OVERRIDE) disables the DLL operation. When OVERRIDE is set low, the DLL generates the DLLCLK by delaying the SYSCLK until the rising edge of REFCLK occurs at the same time as the rising edge of SYSCLK. When OVERRIDE is set high, the DLLCLK output is a buffered version of the SYSCLK input. Used only for diagnostics.
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CBI Register 0x01: Vernier Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function VERNIER[7] VERNIER[6] VERNIER[5] VERNIER[4] VERNIER[3] VERNIER[2] VERNIER[1] VERNIER[0] Default 0 0 0 0 0 0 0 0
The Vernier Control Register provides the delay line tap control when using the vernier option. Used only for diagnostics. VERNIER[7:0]: The vernier tap register bits (VERNIER[7:0]) specifies the phase delay through the DLL when using the vernier feature. When VERN_EN is set high, the VERNIER[7:0] registers specify the delay tap used. When VERN_EN is set low, the VERNIER[7:0] register is ignored. A VERNIER[7:0] value of all zeros specifies the delay tap with the minimum delay through the delay line. A VERNIER[7:0] value of 255 specifies the delay tap with the maximum delay through the delay line.
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CBI Register 0x02: Delay Tap Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function TAP[7] TAP[6] TAP[5] TAP[4] TAP[3] TAP[2] TAP[1] TAP[0] Default X X X X X X X X
The DLL Delay Tap Status Register indicates the delay tap used by the DLL to generate the outgoing clock. Writing to this register performs a software reset of the DLL. A software reset requires a maximum of 24*256 SYSCLK cycles for the DLL to regain lock. During this time the DLLCLK phase is adjusting from its current position to delay tap 0 and back to a lock position. Used only for diagnostics. TAP[7:0]: The tap status register bits (TAP[7:0]) specifies the delay line tap the DLL is using to generate the outgoing clock DLLCLK. When TAP[7:0] is logic zero, the DLL is using the delay line tap with minimum phase delay. When TAP[7:0] is equal to 255, the DLL is using the delay line tap with maximum phase delay. TAP[7:0] is invalid when vernier enable VERN_EN is set to one.
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CBI Register 0x03: Control Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R Type R R R R Function SYSCLKI REFCLKI ERRORI CHANGEI Unused ERROR CHANGE RUN Default X X X X X X 0 0
The DLL Control Status Register provides information of the DLL operation. Used only for diagnostics. RUN: The DLL lock status register bit (RUN) indicates the DLL found a delay line tap in which the phase difference between the rising edge of REFCLK and the rising edge of SYSCLK is zero. After system reset, RUN is logic zero until the phase detector indicates an initial lock condition. When the phase detector indicates lock, RUN is set to logic 1. Maximum time for a DLL lock from reset with a stable clock should be under 12 * 256 / f(SYSCLK). The RUN register bit is cleared only by a system reset (CBI[12]) or a software reset (writing to register 2). CHANGE: The delay line tap change register bit (CHANGE) indicates the DLL has moved to a new delay line tap. CHANGE is set high for eight SYSCLK cycles when the DLL moves to a new delay line tap. ERROR: The delay line error register bit (ERROR) indicates the DLL has run out of dynamic range. When the DLL attempts to move beyond the end of the delay line, ERROR is set high. When ERROR is high, the DLL cannot generate a DLLCLK phase that causes the rising edge of REFCLK to be aligned to the rising edge of SYSCLK. ERROR is set low, when the DLL captures lock again.
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CHANGEI: The delay line tap change event register bit (CHANGEI) indicates the CHANGE register bit has changed value. When the CHANGE register changes from a logic zero to a logic one, the CHANGEI register bit is set to logic one. The CHANGEI register bit is cleared immediately after it is read, thus acknowledging the event has been recorded. ERRORI: The delay line error event register bit (ERRORI) indicates the ERROR register bit has gone high. When the ERROR register changes from a logic zero to a logic one, the ERRORI register bit is set to logic one. The ERRORI register bit is cleared immediately after it is read, thus acknowledging the event has been recorded. If the ERRORE interrupt enable is high, the INT output is also asserted when ERRORI asserts. REFCLKI: The reference clock event register bit REFCLKI provides a method to monitor activity on the reference clock. When the REFCLK primary input changes from a logic zero to a logic one, the REFCLKI register bit is set to logic one. The REFCLKI register bit is cleared immediately after it is read, thus acknowledging the event has been recorded. SYSCLKI: The system clock event register bit SYSLCKI provides a method to monitor activity on the system clock. When the SYSCLK primary input changes from a logic zero to a logic one, the SYSCLKI register bit is set to logic one. The SYSCLKI register bit is cleared immediately after it is read, thus acknowledging the event has been recorded.
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14
MEMORY PORT MAPPING
14.1 Context Size and Location The context records for S/UNI APEX are stored in 4 different areas. The majority of the context information is stored in an external SSRAM, the context memory. For performance reasons, some context information is stored in internal memories. There are three internal memories, the Queue context, the WAN Port scheduler context, and the Loop Port scheduler context Figure 28
Memory Port Aperture Select
- Context Location
External Queue Context Internal Queue Context Internal WAN Port Scheduler Context Internal Loop Port Scheduler Context
Address 0 VC Context VC Statistic VC Address Map Loop Class0 Loop Class1 Loop Class2 Loop Class3 QShpStartAdr Shape0 TxSlot Shape1 TxSlot Shape2 TxSlot Shape3 TxSlot Shape Rate QCellStartAdr Cell Loop Class Scheduler Loop Port Threshold Loop Port Count WAN Class0 WAN Class1 WAN Class2 WAN Class3 WAN Class Scheduler WAN Port Threshold WAN Port Count uP Class Scheduler uP Port Threshold uP Port Count uP Class0 uP Class1 uP Class2 uP Class3 Free Count Overall Count Congestion Discard Max Congestion ID Misc Error WAN Poll Weight WAN Class Status Loop Poll Sequence Loop Poll Weight Loop Class Status
QLClassStartAdr
The records for the external context memory are partitioned into four groups: VC, Loop Ports, Shape and Cells. Three registers define the starting physical address of each of the Loop class, Shape and Cell groups, with the VC group always starting at address zero. The starting address, or offset, may be of any order, and may, under certain restriction, overlap one another. For example, if the VC Address Map will never be enabled for a given application, then the loop class offset may be set to the
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starting location of the VC Address Map. Should the shaping not be required, then cell offset may follow immediately after the loop class records. All the Port context records and all the class context records for the WAN and microprocessor are located internally, and are accessed via the appropriate aperture in the context memory port. Table 17 - External Queue Context Memory Map MPQuadAddr 16K VC 0..16383 16384..24575 24576..28671 64K VC 0..65535 65536..98303 98304..114687 VC Context VC Statistic VC Address Map Loop Class0 Context Record
QLClassStartAdr * 1024 + {0..2047}
QLClassStartAdr * 1024 + {2048..4095} Loop Class1 QLClassStartAdr * 1024 + {4096..6143} Loop Class2 QLClassStartAdr * 1024 + {6144..8191} Loop Class3 QShpStartAdr * 1024 + {0..2047} QShpStartAdr * 1024 + {2048..4095} QShpStartAdr * 1024 + {4096..6143} QShpStartAdr * 1024 + {6144..8191} QShpStartAdr * 1024 + {8192..40959} QCellStartAdr * 1024 + {0..65535} Table 18 Shape0 TxSlot Shape1 TxSlot Shape2 TxSlot Shape3 TxSlot Shape Rate Cell Record
- Internal Queue Context Memory Map Record Loop Class Scheduler Loop Port Threshold Loop Port Count WAN Class0 WAN Class1
MPQuadAddr 0..511 512..1023 1024..1535 1536..1539 1540..1543
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MPQuadAddr 1544..1547 1548..1551 1552 1553 1554 1555 WAN Class2 WAN Class3
Record
WAN Class Scheduler WAN Port Threshold WAN Port Count uP Class Scheduler uP Port Threshold uP Port Count
1556 1557 1558 1559 2048 2049 2050 2051 2052 Table 19
uP Class0 uP Class1 uP Class2 uP Class3 Free Count Overall Count Congestion Discard Maximum Congestion ID Misc Error - Internal WAN Port Scheduler Context Memory Map Record WAN Poll Weight, WAN Class Status - Internal Loop Port Scheduler Context Memory Map Record Loop Poll Sequence Loop Poll Weight Loop Class Status
MPQuadAddr 0 Table 20
MPQuadAddr 0..127 128..191 192..255
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Writing values into unused parameter bits has no effect. However, to ensure software compatibility with future, feature-enhanced versions of the product, unused parameter bits must be written with logic zero. Reading back unused bits can produce either a logic one or a logic zero; hence, unused parameter bits should be masked off by software when read. 14.2 Queue Context Definition Many of the context parameters make references to m bit logarithmic, n bit fractional, where m is the MSB of the parameter field, and n is the LSB of the parameter field. The tables below provide quick references. Table 21 2 bits log - 2 Bit Logarithmic, 2 Bit Fractional 3 3 7 14 28
0 1 2 3
2 bits fractional 0 1 2 0 1 2 4 5 6 8 10 12 16 20 24 Table 22 0
- 4 Bit Logarithmic, 2 Bit Fractional 3 3 7 14 28 56 112 224 448 896 1792 3584 7168
0 1 2 3 4 5 6 7 8 9 10 11 12
2 bits fractional 1 2 0 1 2 4 5 6 8 10 12 16 20 24 32 40 48 64 80 96 128 160 192 256 320 384 512 640 768 1024 1280 1536 2048 2560 3072 4096 5120 6144 8191
4 bits log
Table 23
0 4 0 0 1 1
- 4 Bit Logarithmic, 4 Bit Fractional
4 bits fractional 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16 32 64 128 256 512 1024 2048 4096 8192 16384 32768 65536 131072 262143
17 34 68 136 272 544 1088 2176 4352 8704 17408 34816 69632 139264
18 36 72 144 288 576 1152 2304 4608 9216 18432 36864 73728 147456
19 38 76 152 304 608 1216 2432 4864 9728 19456 38912 77824 155648
20 40 80 160 320 640 1280 2560 5120 10240 20480 40960 81920 163840
21 42 84 168 336 672 1344 2688 5376 10752 21504 43008 86016 172032
22 44 88 176 352 704 1408 2816 5632 11264 22528 45056 90112 180224
23 46 92 184 368 736 1472 2944 5888 11776 23552 47104 94208 188416
24 48 96 192 384 768 1536 3072 6144 12288 24576 49152 98304 196608
25 50 100 200 400 800 1600 3200 6400 12800 25600 51200 102400 204800
26 52 104 208 416 832 1664 3328 6656 13312 26624 53248 106496 212992
27 54 108 216 432 864 1728 3456 6912 13824 27648 55296 110592 221184
28 56 112 224 448 896 1792 3584 7168 14336 28672 57344 114688 229376
29 58 116 232 464 928 1856 3712 7424 14848 29696 59392 118784 237568
30 60 120 240 480 960 1920 3840 7680 15360 30720 61440 122880 245760
31 62 124 248 496 992 1984 3968 7936 15872 31744 63488 126976 253952
14.2.1 VC Context Records 14.2.1.1 VC Context Record
MPMemSelect = External Queue Context MPQuadAddr = ICI Table 24 MPLWord Bits En (bit #) 0 33:32 31 - VC Context Record Structure Parameter Unused VcEn Description Reserved Enables the VC. When VcEn = 0, incoming cells of this VC will be discarded, CellRxErrICI updated, DiscardCnt incremented, and the maskable interrupt QCellRxErr will be generated. Any cells remaining in the queue will be transmitted, if possible. Disables any maskable interrupts that this VC may generate, including QCellRxErr, QVcReasLenErr, QVcMaxThrshErr.
30
VcIntDis
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MPLWord Bits En (bit #) 29
Parameter VcSegOam
Description Segment OAM re-direct. When VcSegOam = 1, any segment OAM encountered in this VC will be redirected to the uP. Warning: This bit must be never be set to one if the VC is destined for the uP class 0 port.
28
VcEEOam
End to end OAM re-direct. When VcEEOam = 1, any end to end OAM encountered in this VC will be redirected to the uP. Warning: This bit must be never be set to one if the VC is destined for the uP class 0 port.
27
VcVPC
When VcVPC = 1, identifies this VC as VPC. When VcVPC = 0, identifies this VC as a VCC. Required for OAM re-direction.
26:24
VcCLP0MinThr Minimum number of CLP0 cells guaranteed to be sh allowed on a per-VC basis. Values are encoded as follows: 000: 001: 010: 011: 100: 101: 110: 111: 0 24 32 48 64 96 128 256
23:18
VcMaxThrsh
PPD maximum threshold for cells on a per-VC basis. 4 bits logarithmic/linear, 2 bits fractional. A zero value will effectively disable congestion at the VC level for this VC; however, the 8K-1 maximum limit still remains active.
17:12 11:6
VcCLP0Thrsh EPD maximum threshold for CLP0 cells on a per-VC basis. 4 bits logarithmic/linear, 2 bits fractional. VcCLP1Thrsh EPD maximum threshold for CLP1 cells on a per-VC basis. 4 bits logarithmic/linear, 2 bits fractional.
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MPLWord Bits En (bit #) 5:4
Parameter VcEFCIMode
Description Defines EFCI marking. 00: 01: 10: 11: No marking Reserved Mark on active CLP0 thresholds Mark on active CLP1 thresholds
Note: active thresholds is defined as the hierarchical maximum threshold set to a non-zero value. 3:2 VcReMapMod 00: ECI=ICI. No VPI/VCI remapping. SwTag e available. 01: Provide an ECI that is different from the ICI. No VPI/VCI remapping. SwTag available. 10: ECI=ICI. VPI header remapping. SwTag available. 11: ECI=ICI. VPI/VCI header remapping. SwTag not available 1 VcCongMode Defines congestion mode when FCQ is not selected. 0: EPD/PPD. Congestion control is set to discard using EPD/PPD. 1: Congestion control operates on a cell by cell basis. When FCQ is selected, this bit is reserved. Warning: This bit must only be set during a VC setup. This bit must be set to 1 if the underlying traffic is not AAL5. 0 VcGFRMode Selects between I.363 standard definition of a frame's CLP, and the emerging GFR standard definition of a frame's CLP. Zero selects the I.363 standard, a value of one selects the emerging GFR standard. This bit is reserved when cell discard congestion rules is selected.
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MPLWord Bits En (bit #) 1 33:27
Parameter
Description
VcCLP0Cnt[12 Last 7 bits of a 13-bit count of CLP0 cells in both VC :6] and Class. Used for congestion control for minimum resource monitoring. VC tear down and watch dog re-allocation will reduce this count by VcQCLP01Cnt if the VcRxBOMClp = 0 and VcQueue = 1 (FCQ).
26:15
VcPortID
VcPortID[11] = 0. VC destined for a Loop port. VcPortID[10:0]: Identifies 1 of 2K loop ports as the destination. If the loop port is configured for Any-PHY, all 11 bits are valid. If the loop transmit port is configured for UTOPIA L2 master, only the first 5 bits (ports 31->0) are valid. Cells received in VCs with VcPortID > 31 will never be transmitted. If the loop transmit port is configured for UTOPIA L1 master or UTOPIA L2 slave, VcPortID[10:0] must be set to 0. Cells received in VCs with VcPortID != 0 will never be transmitted. VcPortID[11:10] = 10. VC destined for a WAN ports VcPortID[9:2]: Reserved, Must be initialized to zero. VcPortID[1:0]: Identifies 1 of 4 WAN ports as the destination. If the WAN port is configured for UTOPIA L1 master or UTOPIA L2 slave, VcPortID[10:0] must be set to 0. Cells received in VCs with VcPortID != 0 will never be transmitted. VcPortID[11:10] = 11. Identifies the uP port as the VC's destination VcPortID[9:0]: Reserved, Must be initialized to zero.
14:13 12
VcClass
Assigns class to this VC
Destination Port Class is not shaped
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MPLWord Bits En (bit #)
Parameter VcQueue
Description Defines the queue mechanism to be used. 0: 1: Weighted Fair Queuing (WFQ) Frame Continuous Queuing (FCQ)
Warning: This bit must only be set during a VC setup. Destination Port Class is shaped Unused 11:6 11:6 VcWght Reserved Class queuing weight. Linear encoding, multiple of 2 with zero taking a special value of 1. (eg. 1, 2, 4, 6 ... 124, 126) Warning: This bit must only be set during a VC setup. VcQueue = 1 (FCQ), and destination Port Class is not shaped 11 VcReasPark Park state bit for re-assembly watch dog. Non-user cells have no effect on this bit. VcQueue = 0 (WFQ), and destination Port Class is not shaped
10 Indication that there is at least one cell in the queue. VcReasActive VC tear down and watch dog re-allocation will set this parameter to zero (empty). 9 Defines one of two maximum frame sizes. When this VcReasMaxSiz parameter is zero, frames exceeding 1366 cells will e have EPD invoked. When this parameter is one, frames exceeding the value programmed in the Reassembly Maximum Length register will have EPD invoked. EPDs will trigger a maskable interrupt to the microprocessor. 8 VcWDEn 7 Unused Marks this VC as one for the watch dog to patrol for re-assembly time outs. Reserved
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DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
MPLWord Bits En (bit #)
Parameter 6 VcLenChkEn
Description Enables the checking of the AAL5 trailer's length field. 0: No length checking. 1: If the length field is zero, EPD will be invoked.
Destination Port Class is shaped 11:6 Unused 5:0 5 VcTxStatus 4 VcTxBOMClp Reserved
VcCongMode = 0 (EPD/PPD Congestion) EOM indication. When VcTxStatus = 0, the next cell transmitted is considered the BOM. Used to indicate when VcTxBOMClp should be re-evaluated. State of the BOM's CLP bit during transmit. Used to maintain VcCLP0Cnt during FCQ congestion and also during EPD/PPD congestion when GFR Mode = 1. 00: Next cell queued is considered the BOM. 01: Next cell queued is considered a COM or EOM. 10: Early packet discard. All cells up to and including the EOM will be discarded. 11: Partial packet discard. All cells but the EOM will be discarded VC tear down and watch dog re-allocation will set this parameter to zero. 1 State of the BOM's CLP bit during receive. Used to VcRxBOMClp maintain VcCLP0Cnt during FCQ congestion and also during EPD/PPD congestion when GFR Mode = 1. 0 VcRxORClp VcQueue = 1 (FCQ), VcGFRMode = 0, Port Class not shaped: This is a running OR of all the CLPs that have been received since the BOM. Used by congestion control to invoke EPD discard Reserved in all other cases.
3:2 VcRxStatus
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DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
MPLWord Bits En (bit #)
Parameter
Description
VcCongMode = 1 (Cell by Cell Congestion) 5:0 Unused 2 33:16 VcQHeadPtr Reserved Points to the first cell in the VC queue. A value of zero indicates that the queue is empty. VC tear down and watch dog re-allocation will set this parameter to zero. 15:13 12:0 VcCLP0Cnt[5: Second 3 bits of a 13-bit count of CLP0 cells in both 3] VC and Class. See MSB for description. VcQCLP01Cnt Count of CLP01 cells in the VC queue. Used for congestion control. VC tear down and watch dog re-allocation will set this parameter to zero. 3 33:16 15:13 12:0 VcQTailPtr Points to the last cell in the VC queue VcCLP0Cnt[2: First 3 bits of a 13-bit count of CLP0 cells in both VC 0] and Class. See MSB for description. VcClassQCLP Count of CLP01 cells in the Class queue for WFQ & 01Cnt FCQ. Count of CLP01 cells in the Class queue & TxSlot table combined for SFQ. Used for congestion control for all queuing mechanisms. Note that during SFQ, the maximum value this parameter can be is 1.
Note Parameters in italics are active context information. Microprocessor must mask these bits out during in-service context modification. During VC setup, these italicized parameters should be reset to zero. 14.2.1.2 VC Statistics Record
MPMemSelect = External Queue Context MPQuadAddr = 65536 + ICI/2, if QNumVCSel = 0 MPQuadAddr = 16384 + ICI/2, if QNumVCSel = 1 The statistic record for even numbered ICI's are located in long words 0 & 1. Odd numbered ICI's are located in long words 2 & 3.
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OAM cells redirected to the uP are not represented by these counts. Table 25 MPLWord Bits En (bit #) 0/2 33:32 31:0 1/3 33:32 31:0 Note Parameters in italics are active context information. Microprocessor must mask these bits out during in-service context modification. During VC setup, these italicized parameters should be reset to zero. 14.2.1.3 VC Address Map Record - VC Statistics Record Structure Parameter Unused Description Reserved
VcCLP0TxCnt Free running count of all CLP0 cells that have been transmitted. Unused Reserved VcCLP1TxCnt Free running count of all CLP1 cells that have been transmitted.
MPMemSelect = External Queue Context MPQuadAddr = 98304 + ICI/4, if QNumVCSel = 0 MPQuadAddr = 24576 + ICI/4, if QNumVCSel = 1 The address map records are packed together. ICI = 0 would have the address map record located in long word 0. ICI = 3 would have the address map record located in long word 3 etc. Table 26 MPLWord Bits En (bit #) 0/1/2/3 33:32 31:0 - VC Address Map Record Structure Parameter Unused 31:16 SwTag 15:0 Unused Description Reserved Option to provide Switch Tag for the WAN and LOOP Tx Interfaces. Prepend of the Switch Tag is determined on a port by port basis. Reserved
VcReMapMode = 00
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MPLWord Bits En (bit #)
Parameter
Description
VcReMapMode = 01 31:16 SwTag 15:0 ECI 31:16 SwTag 15:12 Unused 11:0 VPI 31:16 VCI 15:12 Unused 11:0 VPI 14.2.2 Port Context Records 14.2.2.1 Port Threshold Context Record Option to provide Switch Tag for the WAN and LOOP Tx Interfaces. Prepend of the Switch Tag is determined on a port by port basis. ECI value that is applied to the cells upon emission.
VcReMapMode = 10 Option to provide Switch Tag for the WAN and LOOP Tx Interfaces. Prepend of the Switch Tag is determined on a port by port basis. Reserved VPI remap
VcReMapMode = 11 VCI remap Reserved VPI remap
For Loop Ports: MPMemSelect = Internal Queue Context MPQuadAddr = 512 + Loop#/4 For WAN Ports: MPMemSelect = Internal Queue Context MPQuadAddr = 1553
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DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
For Microprocessor Port: MPMemSelect = Internal Queue Context MPQuadAddr = 1555, MPLWordEn[1] = 1. The port context records are packed together. Loop/WAN = 0 would have the port context record located in long word 0. Loop/WAN = 3 would have the port context record located in long word 3 etc. The microprocessor port would be located in long word 1. Table 27 MPLWord Bits En (bit #) 0/1/2/3 33:16 15:8 - Port Threshold Context Record Structure Parameter Unused Description Reserved
PortCLP0Thrs Per-Port EPD maximum threshold for CLP0 cells that h have met their minimum allocation. 4 bit logarithmic, 4 bit fractional encoding. PortCLP1Thrs EPD maximum threshold for CLP1 cells on a per-Port h basis. 4 bit logarithmic, 4 bit fractional encoding.
7:0 14.2.2.2
Port Count Context Record
For Loop Ports: MPMemSelect = Internal Queue Context MPQuadAddr = 1024 + Loop#/4 For WAN Ports: MPMemSelect = Internal Queue Context MPQuadAddr = 1554 For Microprocessor Port: MPMemSelect = Internal Queue Context MPQuadAddr = 1555, MPLWordEn[2] = 1. The port context records are packed together. Loop/WAN = 0 would have the port context record located in long word 0. Loop/WAN = 3 would have the port
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DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
context record located in long word 3 etc. The microprocessor port would be located in long word 2. Table 28 MPLWord Bits En (bit #) 0/1/2/3 33:32 31 - Port Count Context Record Structure Parameter Unused PortEn Description Reserved Enables the port. When PortEn = 1, it permits cells to be received and transmitted if the class and VCs are setup. The PortEn should be set to zero 0 only after the class and VC have been torn down. If the PortEn is set to zero prior to tearing down a VC, then incoming cells will increment either the DiscardCnt or CLPxDiscardCnt. Cells that exist in the queues when the port is disabled may be transmitted. Details are listed below. If PortEn changes from 1->0, the first cell at the head of each class queue shall be transmitted. Any cells remaining in the queues will not be transmitted. Exception to this case is if the port contains a shaped class, where the transmission of cells in the queues will continue until there is one cell per VC remaining. When PortEn = 0, all incoming cells to this port will be discarded, CellRxErrICI updated, and the maskable interrupt QCellRxErr will be sent. For non FCQ VCs in cell discard mode, the DiscardCnt is incremented when a cell is received. For non FCQ VCs in EPD/PPD discard mode, the DiscardCnt is incremented when the first cell is received, and CLPxDiscardCnt is incremented when subsequent cells are received. For FCQ VCs, the CLPxDiscardCnt is incremented when a cell is received. If a frame is in the process of being re-assembled when PortEn = 1->0, the CLPxDiscardCnt will be incremented by the length of the re-assembly queue plus 1 (cell that arrived). 30:28 Unused Reserved
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MPLWord Bits En (bit #) 27:20
Parameter
Description
PortMaxThrsh Maximum threshold for cells on a per-Port basis. 4 bit logarithmic, 4 bit fractional encoding. A zero value will effectively disable congestion at the Port level for this port. Unused PortCnt Reserved Total count of all cells queued for this port. Used for congestion control. VC tear down and watch dog re-allocation will reduce this count by VcQCLP01Cnt. Class tear down will reduce this count by ClassCnt.
19:18 17:0
Note Parameters in italics are active context information. Microprocessor must mask these bits out during in-service context modification. During port setup, these italicized parameters should be reset to zero.
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14.2.3 Class Context Records 14.2.3.1 Class Scheduler Context Record
For Loop Ports: MPMemSelect = Internal Queue Context MPQuadAddr = Loop#/4 For WAN Ports: MPMemSelect = Internal Queue Context MPQuadAddr = 1552 For Microprocessor Port: MPMemSelect = Internal Queue Context MPQuadAddr = 1555, MPLWordEn[0] = 1. The port context records are packed together. Loop/WAN = 0 would have the port context record located in long word 0. Loop/WAN = 3 would have the port context record located in long word 3 etc. The microprocessor port would be located in long word 0. Table 29 MPLWord Bits En (bit #) 0/1/2/3 33:32 31:20 - Class Scheduler Record Structure Parameter Unused Description Reserved
ClassFragEn = 0 31:28 Number of cells that can be transmitted from another Class1CellLmt class while Class1 is waiting for a transmission opportunity before Class1 enters the starvation condition. 2 bit logarithmic, 2 bit fractional encoding. When ClassPacket = 1, this parameter should be set to 0 to force strict priority.
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MPLWord Bits En (bit #)
Parameter
Description
27:24 Number of cells that can be transmitted from another Class2CellLmt class while Class2 is waiting for a transmission opportunity before Class2 enters the starvation condition. 2 bit logarithmic, 2 bit fractional encoding. When ClassPacket = 1, this parameter should be set to 0 to force strict priority. 23:20 Number of cells that can be transmitted from another Class3CellLmt class while Class3 is waiting for a transmission opportunity before Class3 enters the starvation condition. 2 bit logarithmic, 2 bit fractional encoding. When ClassPacket = 1, this parameter should be set to 0 to force strict priority. ClassFragEn = 1 31 Unused Reserved
30:20 Maximum number of cells that can be transmitted ClassCellLmt from a class before the class scheduler selects another class to transmit from. A value of zero is functionally equivalent to a value of one. 19 18 ClassFragEn ClassPacket Enable packet fragmentation class scheduling. Places the Class scheduler into a packet or frame continuous mode. In packet mode, if a VC set to FCQ is at the head of the class queue, the class scheduler will send out the entire packet prior to servicing a different class. When set, ClassNCellLmt must be set to zero to ensure strict priority scheduling. Warning: This bit must only be set during a Class setup. This must be set to 1 when ClassFragEn = 1. 17:15 ClassPacket = 0 Unused 17 ClassStatus Reserved When ClassStatus = 0, indicates that the next cell transmitted is considered the BOM of a packet. ClassPacket = 1
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MPLWord Bits En (bit #)
Parameter
Description
16:15 Indicates the class that is currently being serviced. ClassServiced 14:0 ClassFragEn = 0 14:10 Current number of cells that have been transmitted Class1CellCnt while Class1 has remained unserviced. 9:5 Current number of cells that have been transmitted Class2CellCnt while Class2 has remained unserviced. 4:0 Current number of cells that have been transmitted Class3CellCnt while Class3 has remained unserviced. ClassFragEn = 1 14:11 Unused 10:0 ClassCellCnt Note Parameters in italics are active context information. Microprocessor must mask these bits out during in-service context modification. During class setup, these italicized parameters should be reset to zero. 14.2.3.2 Class 0 through 3 Context Record Reserved Current number of cells that have been transmitted from the class indicated by ClassServiced.
For Loop Ports: MPMemSelect = External Queue Context MPQuadAddr = QLClassStartAdr * 1024 + Class * 2048 + Loop# For WAN Ports: MPMemSelect = Internal Queue Context MPQuadAddr = 1536 + Class * 4 + WAN#, Class = 0,1,2,3 For Microprocessor Ports: MPMemSelect = Internal Queue Context
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DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
MPQuadAddr = 1556 + Class * 4, Class = 0,1,2,3 Table 30 MPLWord Bits En (bit #) 0 33:32 31 - Class Context Record Structure Parameter Unused ClassEn Description Reserved Enable the class queue. When ClassEn = 1, it permits cells to be received and transmitted if the port and VCs are setup. The ClassEn should be set to zero 0 only after the VC has been torn down. If the ClassEn is set to zero prior to tearing down a VC, then incoming cells will increment either the DiscardCnt or CLPxDiscardCnt. Details are listed below. When ClassEn = 0, all incoming cells to this class will be discarded, CellRxErrICI updated, and the maskable interrupt QCellRxErr will be sent. For non FCQ VCs, any cells remaining in the queue will be transmitted, if possible. If the VC is in cell discard mode, cells received will cause the DiscardCnt to increment. If the VC is in EPD/PPD discard mode, the DiscardCnt is incremented when the first cell is received, and CLPxDiscardCnt is incremented when subsequent cells are received. For FCQ VCs, the CLPxDiscardCnt is incremented when a cell is received. If a frame is in the process of being re-assembled when ClassEn = 1->0, the CLPxDiscardCnt will be incremented by the length of the re-assembly queue plus 1 (cell that arrived). 30:24 23:16 Unused Reserved ClassMaxThrs Maximum threshold for cells on a per-Class basis. 4 h bit logarithmic, 4 bit fractional encoding. A zero value will effectively disable congestion at the class level for this class. ClassCLP0Thr Per- Class EPD threshold for CLP0 cells that have sh met their minimum buffer allocation. 4 bit logarithmic, 4 bit fractional encoding.
15:8
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MPLWord Bits En (bit #) 7:0
Parameter
Description
ClassCLP1Thr EPD maximum threshold for CLP1 cells on a persh Class basis. 4 bit logarithmic, 4 bit fractional encoding. Unused Reserved ClassCnt[17:1 Last 6 bits of an 18 bit count of all cells in both class, 2] TxSlot (SFQ only) & VC queue. Used for congestion control. VC tear down and watch dog re-allocation will reduce this count by VcQCLP01Cnt Class tear down will set this parameters to zero.
1
33:26 25:20
19:18 17:0
Unused
Reserved
ClassHeadPtr Points to first Cell in linked list of Cell Records for Class queue. A value of zero indicates that the queue is empty; however, during shaping or VcMerge, it does not indicate that the class is empty. Class tear down will set this parameters to zero. Unused Reserved
2
33:32 31:20 19:18 17:0
ClassCnt[11:0] First 12 bits of an 18 bit count of all cells in both class & VC queue. See MSB for description. Unused ClassTailPtr Reserved Points to last Cell in linked list of Cell Records for Class queue. Class tear down will set this parameters to zero. Reserved
3 Note
33:0
Unused
Parameters in italics are active context information. Microprocessor must mask these bits out during in-service context modification. During class setup, these italicized parameters should be reset to zero.
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14.2.4 Shaping Context Records 14.2.4.1 Shape TxSlot Context Record
MPMemSelect = External Queue Context MPQuadAddr = QShpStartAdr * 1024 + Shape# * 2048 + TxSlot/2, TxSlot = 0..4095 The TxSlot record for even numbered TxSlots are located in long words 0 & 1. Odd numbered TxSlots are located in long words 2 & 3. Table 31 MPLWord Bits En (bit #) 0/2 33:16 - Shape TxSlot Context Record Structure Parameter Description
ShpTxQHeadP Head pointer for the traffic shaped transmission tr queue. A value of zero indicates that the queue is empty. Unused ShpTxQCnt Reserved Number of cells en-queued on this time slot. ShpTxQTailPtr Tail pointer for the traffic shaped transmission queue.
15:0 1/3 Note 33:16 15:0
Parameters in italics are active context information. Microprocessor must mask these bits out during in-service context modification. During VC setup, these italicized parameters should be reset to zero. 14.2.4.2 Shape Rate Context Record
MPMemSelect = External Queue Context MPQuadAddr = QShpStartAdr * 1024 + 8192 + ICI/2 The shape rate record for even numbered ICI's are located in long words 0 & 1. Odd numbered ICI's are located in long words 2 & 3.
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Table 32 MPLWord Bits En (bit #) 0/2 33:32 31:28
- Shape Rate Context Record Structure Parameter Unused ShpLateBits Description Reserved Number of bits used to represent ShpTxSlotsLate, the "late counter". In unit of timeslots, MBS = 2 ^ ShpLateBits. Cell Delay Variance Tolerance for the connection. Format is in integer number of timeslots. It must be less than ShpIncr, and ShpCdvt < 2 ^ ShpLateBits. Relative to the ATMF 4.1 specification terminology, this value is equivalent to T - Ts, where T = 1/PCR, Ts = 1/SCR. This parameter must be set to zero if ShpPrescale = 0.
27:16
ShpCdvt
15:13 12 11:0
Unused ShpPrescale ShpIncr
Reserved Determines the resolution of the Incr field Increment field for SCR-GCRA. . Format is in integer number of timeslots if Prescale = 1 or in integer + 1/64 fractional timeslots xxxxxx.xxxxxx (6 bit integer part w/ 6-bit fractional part) if ShpPrescale = 0. The ShpIncr must always be greater than or equal to 1.0.
1/3
33:30 29:18
Unused
Reserved
ShpTxSlotsLat Indicates the accumulated number of late time slots e that the previous cells for this connection were output. ShpLateBits specifies the number of least significant bits used to represent this value. ShpRem ShpTxSlot Indicates the remainder when scheduling at fractional timeslots. Indicates the last time slot that this connection was scheduled
17:12 11:0 Note
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Parameters in italics are active context information. Microprocessor must mask these bits out during in-service context modification. During VC setup, these italicized parameters should be reset to zero. 14.2.5 Cell Context Record MPMemSelect = External Queue Context MPQuadAddr = QCellStartAdr * 1024 + CellPtr/4 The cell records are packed together. CellPtr = 0 would have the cell record located in long word 0. CellPtr = 3 would have the cell record located in long word 3 etc. Table 33 MPLWord Bits En (bit #) 0/1/2/3 Note Parameters in italics are active context information. Microprocessor must mask these bits out during in-service context modification. During freelist setup, CellICI should be reset to zero. 14.2.6 Misc Context Note: 1) Masked writes are not permitted for any of the Misc. context records. 2) Parameters in italics are active context information. During chip setup, these italicized parameters should be reset to zero unless otherwise stated. MPMemSelect = Internal Queue Context MPQuadAddr = 2048 33:16 15:0 - Cell Context Record Structure Parameter CellNextPtr CellICI Description Points to the next cell in the linked list VC Identifier
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Table 34 MPLWord Bits En (bit #) 0 33:18 17:0
- Free Count Context Structure Parameter Unused FreeCnt Description Reserved Total count of all cells available for buffering. This parameter must be initialized to the cell buffer size minus 1. VC tear down and watch dog re-allocation will increase this count by VcQCLP01Cnt. Class tear down will increase this count by ClassCnt.
1
33:18 17:0
Unused FreeHeadPtr
Reserved Points to the first cell context record of the linked list that holds all the cell records that are free for cell buffering. Reserved Points to the last cell context record of the linked list that holds all the cell records that are free for cell buffering. Reserved
2
33:18 17:0
Unused FreeTailPtr
3
33:0
Unused
MPQuadAddr = 2049 Table 35 MPLWord Bits En (bit #) 0 33:18 17:0 - Overall Count Context Structure Parameter Unused LoopCnt Description Reserved Total count of all cells queued for all loop ports. This is the "DirCnt" for cells destined to a loop port. VC tear down and watch dog re-allocation will reduce this count by VcQCLP01Cnt if VC is destined for the Loop. Class tear down will reduce this count by ClassCnt if class is destined for the Loop. 1 33:18 Unused Reserved
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MPLWord Bits En (bit #) 17:0
Parameter WANCnt
Description Total count of all cells queued for all WAN ports. This is the "DirCnt" for cells destined to a WAN port. VC tear down and watch dog re-allocation will reduce this count by VcQCLP01Cnt if VC is destined for the WAN. Class tear down will reduce this count by ClassCnt if class is destined for the WAN.
2 3
33:0 33:0
Unused Unused
Reserved Reserved
MPQuadAddr = 2050 Table 36 MPLWord Bits En (bit #) 0 33:32 31:0 - Congestion Discard Context Structure Parameter Unused Description Reserved
CLP0DiscardC Free running count of all inbound CLP0 cells that have nt been discarded due to congestion, re-assembly maximum length limit, disabled class/port, or zero length check. Unused Reserved CLP0DiscardI These bits contain the ICI of the last time a CLP0 cell CI was discarded due to congestion. Unused Reserved CLP1DiscardC Free running count of all inbound CLP1 cells that have nt been discarded due to congestion, re-assembly maximum length limit, disabled class/port, or zero length check. Unused Reserved CLP1DiscardI These bits contain the ICI of the last time a CLP1 cell CI was discarded due to congestion.
1
33:16 15:0
2
33:32 31:0
3
33:0 15:0
MPQuadAddr = 2051
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Table 37 MPLWord Bits En (bit #) 0 33:16 15:0 1 33:14 13:12 11:0
- Maximum Congestion ID Context Structure Parameter Unused Description Reserved
VcMaxThrshEr These bits contain the ICI of the last VC queue that rICI has reached the congestion limit of VcMaxThrsh. Unused Reserved ClassMaxThrs These bits identify which class of the last class queue hErrID that has reached the ClassMaxThrsh limit. ClassMaxThrs These bits contain the Port ID of the last class queue hErrPortID that has reached the ClassMaxThrsh limit. See VC Context Record for PortID encoding. Unused Reserved PortMaxThrsh These bits contain the Port ID of the last port queue ErrPortID that has reached the PortMaxThrsh limit. See VC Context Record for PortID encoding. Unused Reserved
2
33:12 11:0
3
33:0
MPQuadAddr = 2052 Table 38 MPLWord Bits En (bit #) 0 33:32 31:0 - Misc Error Context Structure Parameter Unused DiscardCnt Description Reserved Free running general discard count of all the cells that have been discarded due to reasons other than congestion. Possible causes include re-assembly time out, cell encountered on a disable VC/Class/Port, tear down of a VC or class queue.. Reserved These bits contain the ICI of the last cell that was destined for a VC that was not enabled. This could be caused when any of the following enables are not set to 1: VcEn, ClassEn, PortEn. Reserved
1
33:16 15:0
Unused CellRxErrICI
2
33:16
Unused
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MPLWord Bits En (bit #) 15:0 3 33:16 15:0
Parameter
Description
VcReasLenErr These bits contain the ICI of the last VC that violated ICI the maximum permitted re-assembly length. Unused Reserved VcReasTimeE These bits contain the ICI of the last timed out VC rrICI discovered by the watch dog.
14.3 WAN Port Scheduler Context 14.3.1 WAN Transmit Port Polling Weight Record MPMemSelect = WAN Port Scheduler Internal Context MPQuadAddr = 0 The WAN Transmit Port Polling Weight records are packed together NOTE: Only single long word accesses are permitted at any one time. Table 39 MPLWord Bits En (bit #) 0 31:14 13:12 11:10 9:8 7:6 5:4 3:2 1:0 - WAN Transmit Port Polling Weight Parameter Unused Description Reserved
WANPollWght WAN polling weight for port 3 3 Unused Reserved WANPollWght WAN polling weight for port 2 2 Unused Reserved WANPollWght WAN polling weight for port 1 1 Unused Reserved WANPollWght WAN polling weight for port 0 0
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The polling weight determines how frequently the WAN port scheduler will evaluate whether the corresponding WAN port should be polled for transmit packet available. The weights are logarithmic. The weight determines how many of the total polling cycles a port participates in. A weight should be set according to the following table: Table 40 - WAN Poll Weight Format Weight ratio 1 1/2 1/4 1/8
WANPollWght[1:0] 00 01 10 11
14.3.2 WAN Transmit Class Status Record MPMemSelect = WAN Port Scheduler Internal Context MPQuadAddr = 0 NOTE: Only single long word accesses are permitted at any one time. Table 41 MPLWord Bits En (bit #) 1 31:16 15:12 11:8 7:4 3:0 - WAN Class Status Parameter Unused Description Reserved
WANClassStat WAN class status for port 3 3 WANClassStat WAN class status for port 2 2 WANClassStat WAN class status for port 1 1 WANClassStat WAN class status for port 0 0
The bits in each WAN class status indicates whether a cell destined for the given WAN is currently in the queue waiting for transmission. Bit 0 represents class 0, bit 1 represents class 1 etc.
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Warning: Masking should always be applied over active classes during writes. 14.4 Loop Port Scheduler Context 14.4.1 Loop Transmit Port Polling Sequence Record MPMemSelect = Loop Port Scheduler Internal Context MPQuadAddr = Loop#/16 The Loop Transmit Port Polling Sequence records are packed. Each long word contains sequence numbers for four ports. Each quad word contains entries for 16 ports. There are a total of 128 quad words in the table for a total of 2K loop ports. Long word 0 contains weight for ports 0-3, long word 1 contains weight for ports 4-7 etc. NOTE: Only single long word accesses are permitted at any one time. Table 42 MPLWord Bits En (bit #) 0/1/2/3 31 30:24 23 22:16 15 15:8 7 6:0 - Loop Transmit Port Polling Sequence Parameter Unused Description Reserved
LoopPollSeq3 Loop polling sequence for port ((MPLWordEn bit *4) + 3) Unused Reserved LoopPollSeq2 Loop polling sequence for port ((MPLWordEn bit *4) + 2) Unused Reserved LoopPollSeq1 Loop polling sequence for port ((MPLWordEn bit *4) + 1) Unused Reserved LoopPollSeq0 Loop polling sequence for port ((MPLWordEn bit *4) + 0)
The polling sequence determines when within a loop port scheduler weight polling cycle this port will be evaluated to be polled. This allows software to evenly distribute the polling of ports of the same weight. The loop port scheduler will compare the n LSB's of the LoopPollSeq with the current scheduler poll sequence to decide if that port should be polled (n is equal to the port's
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LoopPollWght). When these 2 values match and that port has transmit data to be sent, that port is scheduled to be polled. 14.4.2 Loop Transmit Port Polling Weight Record MPMemSelect = Loop Port Scheduler Internal Context MPQuadAddr = 128 + Loop#/32 The Loop Transmit Port Polling Weight records are packed together. Each long word contains weights for 8 loop ports. There are a total of 64 quad words in the table for a total of 2K loop ports. Long word 0 contains weight for ports 0-7, long word 1 contains weight for ports 8-15 etc. NOTE: Only single long word accesses are permitted at any one time. Table 43 MPLWord Bits En (bit #) 0/1/2/3 31 30:28 27 26:24 23 22:20 19 18:16 15 14:12 11 10:8 - Loop Transmit Port Polling Weight Parameter Unused Description Reserved
LoopPollWght Loop polling weight for port ((MPLWordEn bit *8) + 7) 7 Unused Reserved LoopPollWght Loop polling weight for port ((MPLWordEn bit *8) + 6) 6 Unused Reserved LoopPollWght Loop polling weight for port ((MPLWordEn bit *8) + 5) 5 Unused Reserved LoopPollWght Loop polling weight for port ((MPLWordEn bit *8) + 4) 4 Unused Reserved LoopPollWght Loop polling weight for port ((MPLWordEn bit *8) + 3) 3 Unused Reserved LoopPollWght Loop polling weight for port ((MPLWordEn bit *8) + 2) 2
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MPLWord Bits En (bit #) 7 6:4 3 2:0
Parameter Unused
Description Reserved
LoopPollWght Loop polling weight for port ((MPLWordEn bit *8) + 1) 1 Unused Reserved LoopPollWght Loop polling weight for port ((MPLWordEn bit *8) + 0) 0
The polling weight determines how frequently the loop port scheduler will evaluate whether the corresponding loop port should be polled for transmit packet available. 14.4.3 Loop Transmit Class Status Record MPMemSelect = Loop Port Scheduler Internal Context MPQuadAddr = 192 + Loop#/32 The Loop Class Status records are packed together. Each long word contains status for 8 loop ports. There are a total of 64 quad words in the table for a total of 2K loop ports. Long word 0 contains weight for ports 0-7, long word 1 contains weight for ports 8-15 etc. NOTE: Only single long word accesses are permitted at any one time. Table 44 MPLWord Bits En (bit #) 0/1/2/3 31:28 27:24 23:20 19:16 - Loop Class Status Parameter Description
LoopClassStat Loop class status for port ((MPLWordEn bit *8) + 7) 7 LoopClassStat Loop class status for port ((MPLWordEn bit *8) + 6) 6 LoopClassStat Loop class status for port ((MPLWordEn bit *8) + 5) 5 LoopClassStat Loop class status for port ((MPLWordEn bit *8) + 4) 4
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MPLWord Bits En (bit #) 15:12 11:8 7:4 3:0
Parameter
Description
LoopClassStat Loop class status for port ((MPLWordEn bit *8) + 3) 3 LoopClassStat Loop class status for port ((MPLWordEn bit *8) + 2) 2 LoopClassStat Loop class status for port ((MPLWordEn bit *8) +1) 1 LoopClassStat Loop class status for port ((MPLWordEn bit *8) + 0) 0
The bits in each loop class status indicates whether a cell destined for the given loop is currently in the queue waiting for transmission. Bit 0 represents class 0, bit 1 represents class 1 etc. Warning: Masking should always be applied over active classes during writes.
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15
TEST FEATURES DESCRIPTION
15.1 JTAG Test Port The S/UNI APEX JTAG Test Access Port (TAP) allows access to the TAP controller and the 4 TAP registers: instruction, bypass, device identification and boundary scan. Using the TAP, device input logic levels can be read, device outputs can be forced, the device can be identified and the device scan path can be bypassed. Table 45 - Instruction Register
Length - 3 bits Instructions EXTEST IDCODE SAMPLE BYPASS BYPASS STCTEST BYPASS BYPASS Table 46 Length Version number Part Number Manufacturer's identification code Device identification Table 47 - Boundary Scan Register Selected Register Boundary Scan Identification Boundary Scan Bypass Bypass Boundary Scan Bypass Bypass - Identification Register 32 bits 0H 7326H 0CDH 073260CDH Instruction Codes, IR[2:0] 000 001 010 011 100 101 110 111
Please see file "APEX JTAG Scan Register.xls"
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Boundary Scan Cells In the following diagrams, CLOCK-DR is equal to TCK when the current controller state is SHIFT-DR or CAPTURE-DR, and unchanging otherwise. The multiplexer in the centre of the diagram selects one of four inputs, depending on the status of select lines G1 and G2. The ID Code bit is as listed in the Boundary Scan Register table located above. Figure 29
IDCODE
- Input Observation Cell (IN_CELL)
Scan Chain Out INPUT to internal logic
Input Pad
G1 G2 SHIFT-DR
I.D. Code bit CLOCK-DR
12 1 2 MUX 12 12
Scan Chain In
D C
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Figure 30
- Output Cell (OUT_CELL)
Scan Chain Out
EXTEST Output or Enable from system logic IDOODE SHIFT-DR
G1 1 G1 G2 1 1 1 1 2 2 MUX 2 2 1
OUTPUT or Enable
MUX
D C
D C
I.D. code bit CLOCK-DR UPDATE-DR
Scan Chain In
Figure 31
- Bi-directional Cell (IO_CELL)
Scan Chain Out
EXTEST OUTPUT from internal logic IDCODE SHIFT-DR INPUT from pin I.D. code bit CLOCK-DR UPDATE-DR Scan Chain In
G1 1 G1 G2 12 1 2 MUX 12 12 1
INPUT to internal logic
MUX
OUTPUT to pin
D C
D C
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Figure 32
- Layout of Output Enable and Bidirectional Cells Scan Chain Out
OUTPUT ENABLE from internal logic (0 = drive) INPUT to internal logic OUTPUT from internal logic
OUT_CELL
IO_CELL
I/O PAD
Scan Chain In
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16
OPERATION
Please refer to the document "S/UNI APEX H/W Programmer's Guide", PMC991454
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17
FUNCTIONAL TIMING
17.1 Microprocessor Interface The following diagrams illustrate the various handshaking required for microprocessor reads and writes. Figure 33 shows a single read and write operation with bus polarity set to 1. On the first cycle, BURSTB is sampled inactive; therefore, it is expected that the cycle be a single data transfer, and the BLAST signal is of no significance. The subsequent 2 cycles have BURSTB sampled active hence the transfer cycle Is terminated when both BLAST and READYB are asserted. Note that between each transfer, there is a turn around cycle provided by the external interface to ensure that there is no bus contention on back to back transfers on the AD bus. Figure 33
1 BCLK BUSPOL CSB ADSB AD(31:0) WR BURSTB BLAST READYB BTERMB A D A D A D 2
- Single Word Read and Write
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Read, 3 wait cycles
Write, 1 wait cycle
Read, 4 wait cycles
Figure 34 shows a burst read and write operation with bus polarity set to 0. The first and third access illustrate transfers that are terminated by the S/UNI APEX via the assertion of BTERMB. The second and fourth access illustrate transfers that are terminated by the external interface via the assertion of BLAST. Note that between each transfer, there is no turn around cycle. Care must be taken to examine the AC timing to ensure that there is no bus contention on the AD bus between a read followed by a write transfer.
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Figure 34
1 2 3
- Burst Read and Write
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Burst Read, 3 wait cycles, BTERMB issued Burst Read, 4 wait cycles, no BTERMB Burst Write, 1 wait cycles, BTE
BCLK BUSPOL CSB ADSB AD(31:0) WR BURSTB BLAST READYB BTERMB A D A D A D A D D
Figure 35 shows consecutive write operations using the WRDONEB signal without the READYB. Write operations may only begin when WRDONEB is sampled low by the external interface. On the first data transfer, the cycle is terminated normally. Subsequent access does not begin until WRDONEB is sampled low by the external interface. This interface is used when the external processor is incapable of dealing with wait states during write operations.
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Figure 35
1 BCLK BUSPOL CSB ADSB AD(31:0) WR BURSTB BLAST WRDONEB
- Consecutive Write Accesses Using WRDONEB
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
A
D0
A
D0
D1 D2 D3
17.2 SDRAM Interface The following three diagrams depict the timing for signals destined for the pins of the SDRAM during the Activate-Read (with Auto-precharge), Activate-Write (with Auto-precharge), and Auto-refresh command sequences. The cbcmd signal is not an actual signal; it merely represents the memory access command formed by the combination of the individual SDRAM control signals (cbcsb_o, cbrasb_o, etc.). Another note is that reads/writes are always done in bursts of eight words; the first involves the even banks and the second burst involves the odd banks in SDRAM.
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Figure 36
1 sysclk tRCD cbcmd cbcsb cbrasb cbcasb cbweb cbdqm[1:0] cbbs[1:0] cba[11, 9:0] cba[10] even row even row act0 desel/nop 2 3 4
- Read Timing
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
tRCD rd0 desel/nop act1 desel/nop rd1 desel/nop
even bank even col prea
odd bank odd row odd row odd col prea
00
cbdq[31:0]
d0
d1
d2
d3
d4
d5
d6
d7
d8
d9
d10
d11
d12
d13
d14
d15
Figure 37
1 sysclk tRCD cbcmd cbcsb cbrasb cbcasb cbweb cbdqm[1:0] cbbs[1:0] cba[11, 9:0] cba[10] even row even row act0 desel/nop 2 3
- Write Timing
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
tRCD wr0 desel/nop act1 desel/nop wr1 desel/nop
even bank even col prea odd row odd row
odd bank odd col prea
00
cbdq[31:0]
d0
d1
d2
d3
d4
d5
d6
d7
d8
d9
d10
d11
d12
d13
d14
d15
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Figure 38
1 sysclk 2
- Refresh
3 4 5 6 7 8 9 10 11 12
cbcmd cbcsb cbrasb cbcasb cbweb cbdqm[1:0] cbbs[1:0] cba[11:0] cbdq[31:0]
refa
tRC desel/nop
act
desel/nop
00 400h
Figure 39
1 sysclk Vcc 2 3 4
- Power Up and Initialization Sequence
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
CBRI performs first arbitration on cycle following MRS SDRAM Initialization Sequence (78 cyc) bucb_cben REFA & tRC (9 cyc) sequence must be repeated 8 times, prior to MRS tRP (3cyc) cbcmd cbcsb cbrasb cbcasb cbweb cbdqm[1:0] cbbs[1:0] cba[11:0] cbdq[31:0] 400h 00 033h NOP PREA NOP REFA NOP REFA tRC (9cyc) NOP MRS
17.3 ZBT SSRAM Interface The following diagram depicts the timing for signals destined for the pins of the pipelined ZBT SSRAM during a read followed by a write cycle. The cmcmd
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signal is not an actual signal; it merely represents the memory access command formed by the combination of the individual SSRAM control. Figure 40
1 sysclk cmcmd cmceb cmrwb cma[19:0] cmab[18:17] a1 a1 a2 a2 rd desel wr desel
- Read followed by Write Timing
2 3 4 5 6 7 8 9
cmd[33:0] cmp[1:0]
r1 r1
w2 w2
17.4 Late Write SSRAM Interface The following diagram depicts the timing for signals destined for the pins of the register to register Late Write SSRAM during a read followed by a write cycle. The cmcmd signal is not an actual signal; it merely represents the memory access command formed by the combination of the individual SSRAM control.
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Figure 41
1 sysclk cmcmd cmceb cmrwb cma[19:0] cmab[18:17] a1 a1 rd
- Read followed by Write Timing
2 3 4 5 6 7 8 9
desel
wr
desel
a2 a2 2cyc 1cyc r1 r1 w2 w2
cmd[33:0] cmp[1:0]
17.5 Any-PHY/UTOPIA Interfaces While the following diagrams present representative waveforms, they are not an attempt to unambiguously describe the interfaces. The Pin Description section is intended to present the detailed pin behavior and constraints on use. The following parameters apply to all Any-PHY/UTOPIA interface figures: n = 2 for WAN, 5 for Loop m = 7 for 8 bit mode, 15 for 16 bit mode k = function of 8/16 bit mode, and number of prepends selected. 17.5.1 Receive Master/Transmit Slave Interfaces Figure 42 gives an example of the functional timing of the receive interface when configured as a UTOPIA Level 2 compliant transmit slave. The interface responds to the polling of address "APEX" (which matches the address defined by the register {Loop/WAN}RxSlaveAddr[n:0]) by asserting RPA when it is capable of accepting a complete cell. As a result, the master selects the S/UNIAPEX by presenting "APEX" again during the last cycle RENB is high. Had not the device been selected, RSOP, RDAT[n:0] and RPRTY would have remained high-impedance.
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Figure 42 illustrates that a cell transfer may be paused by deasserting RENB. The device is reselected by presenting address "APEX" the last cycle RENB is high to resume the transfer. Figure 42
RCLK RADR [n:0]
APEX APEX DEV 2
- UTOPIA L2 Transmit Slave (Loop & WAN)
1 RCLK RPA RDAT[m:0], RPRTY RENB RSOP
Data K-2 Data K-1 Data K Data 0 Data 1 Data 2
Figure 43 gives an example of the functional timing of the receive interface when configured as a UTOPIA Level 1 compliant receive master. When S/UNI APEX is capable of accepting at least one more cell, and it samples RPA high, a transfer cycle is initiated. If the S/UNI APEX is capable of receiving an additional cell and RPA is sampled high, it will de-assert RENB first before initiating the next transfer. Once transfer is initiated, RENB will remain asserted until the last data is received. Figure 43
RCLK RADR [n:0] RPA RDAT[m:0], RPRTY RENB RSOP
Data 0 Data 1 Data K-1 Data K
- UTOPIA L1 Receive Master (Loop & WAN)
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Figure 44 gives an example of the functional timing of the receive interface when configured as a UTOPIA Level 2 compliant receive master. When S/UNI APEX is capable of accepting at least one more cell, the interface polls addresses until it receives an asserted RPA. As a result, the master re-selects the same RADR again during the last cycle RENB is high to initiate a transfer. If the S/UNI APEX is capable of receiving an additional cell, it will continue to poll for the next available port. Once transfer is initiated, RENB will remain asserted until the last data is received. Figure 44
RCLK RADR [n:0]
DEV 0 DEV x DEV n
- UTOPIA L2 Receive Master (Loop & WAN)
1 RCLK RPA RDAT [m:0], RPRTY RENB RSOP
DEV 0 Data 0 Data 1 Data 2 Data K-1 Data K DEV n Data 0
Figure 45 gives an example of the functional timing of the receive interface when configured as a Any-PHY compliant receive master. When S/UNI APEX is capable of accepting at least one more cell, the interface polls addresses until it receives an asserted RPA. As a result, the master re-selects the same RADR again during the last cycle RENB is high to initiate a transfer. If the S/UNI APEX is capable of receiving an additional cell, it will continue to poll for the next available port. Once transfer is initiated, RENB will remain asserted until the last data is received.
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Figure 45
RCLK RADR [n:0]
- Any-PHY Receive Master (Loop & WAN)
DEV 0
DEV x 2 RCLK
DEV n
RPA RDAT [m:0], RPRTY RENB RSX RSOP
DEV 0 DEV 0 Adr Pre Data 1 Data K-1 Data K
DEV n D
17.5.2 Transmit Master/Receive Slave Interfaces Figure 46 gives an example of the functional timing of the transmit interface when configured as a UTOPIA Level 2 compliant receive slave. The interface responds to the polling of address "APEX" (which matches the address defined by the register {Loop/WAN}TxSlaveAddr[n:0]) by asserting TPA when it is capable of transmitting a complete cell. As a result, the master selects the S/UNI-APEX by presenting "APEX" again during the last cycle TENB is high. Had not the device been selected, TSOP, TDAT[n:0] and TPRTY would have remained high-impedance. Figure 46 illustrates that a cell transfer may be paused by deasserting TENB. The device is reselected by presenting address "APEX" the last cycle TENB is high to resume the transfer.
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Figure 46
TCLK TADR [n:0]
- UTOPIA L2 Receive Slave (Loop & WAN)
APEX
APEX
DEV 2
1 TCLK TPA TDAT[m:0], TPRTY TENB TSOP
Data K-3 Data K-2 Data K-1 Data K Data 0 Data 1
Figure 47 gives an example of the functional timing of the WAN transmit interface when configured as a UTOPIA L1 compliant transmit master. The address presented on the WTADR bus comes from the WANTxSlaveAddr register. When the S/UNI APEX samples WTPA as high and there is a complete cell is available for transfer, a transfer is initiated. If WTPA remains high at the end of the first transfer, and if a cell is available for transfer, another transfer is initiated. Transfers complete without pausing. Figure 47
WTCLK WTADR [2:0] WTPA WTDAT[m:0], WTPRTY WTENB TSOP
Data 0 Data 1 Data K Data 0 Data 1
- WAN UTOPIA L1 Transmit Master
register WANTxSlaveAddr
Figure 48 gives an example of the functional timing of the loop transmit interface when configured as a UTOPIA L1 compliant transmit master. It is nearly identical to the WAN UTOPIA L1 transmit master, with the exception that the address on the LTADR bus is indeterminate and should not be used.
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
Figure 48
LTCLK LTADR [11:0] LTPA LTDAT [m:0], LTPRTY LTENB LTSOP
- Loop UTOPIA L1 Transmit Master
Data 0
Data 1
Data 2
Data K-1
Data K
Data 0
Figure 49 gives an example of the functional timing of the WAN transmit interface when configured as a UTOPIA L2 compliant transmit master. The S/UNI APEX polls ports that it has a complete cell available for transfer. The receiving device responds by driving WTPA. When the first port asserts WTPA, the S/UNI APEX will stop polling, and drives WTADR with the port's address until the transfer is initiated. Once the transfer is initiated, as indicated by the assertion of WTENB, polling recommences and continues until the next port asserts WTPA. If the port in transfer is polled at the same time, WTPA is considered valid only for the last 4 clocks from the end of the transfer. The second transfer will not begin until the first transfer is complete. Transfers complete without pausing. Figure 49
WTCLK WTADR [2:0]
DEV 0 DEV x DEV n
- WAN UTOPIA L2 Transmit Master
1 TCLK WTPA WTDAT[m:0], WTPRTY WTENB WTSOP
DEV 0 Dev 0, Data 0 Data 1 DEV x Data 2 Data K DEV n Dev n, Data 0 ata 1 D Data 2
Figure 50 gives an example of the functional timing of the loop transmit interface when configured as a UTOPIA L2 compliant transmit master. It is nearly identical to the WAN UTOPIA L2 transmit master, with the exception of the polling behaviour. Unlike the WAN, the loop interface will assert a NULL address once a
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
LTPA is sampled high. The NULL address remains on the LTADR bus until the port selection marking the start of the next transfer. Transfers complete without pausing. Figure 50
LTCLK LTADR [5:0]
PHY 0 PHY x PHY 1 PHY 1
- Loop UTOPIA L2 Transmit Master
1 TCLK LTPA LTDAT [m:0], LTPRTY LTENB TSOP
PHY 0 Dev 0,Data 1 Data 2 PHY x Data K-1 PHY 1 Data K PHY 1 Dev 1, Data 1
Figure 51 gives an example of the functional timing of the WAN transmit interface when configured as a Any-PHY compliant transmit master. The S/UNI APEX polls ports that it has a complete cell available for transfer. The receiving device responds by driving WTPA. When the first port asserts WTPA, the S/UNI APEX will stop polling, and drives WTADR with the port's address until the transfer is initiated. Once the transfer is initiated, as indicated by the assertion of WTENB & WTSX, polling recommences and continues until the next port asserts WTPA. Transfers complete without pausing. Figure 51
WTCLK WTADR [2:0]
DEV 0 DEV x DEV 1
- WAN Any-PHY Transmit Master
2 TCLK WTPA WTDAT[m:0], WTPRTY WTENB WTSX TSOP
DEV 0 Adr Pre, Dev 0 Data 0 Data 1 Data K DEV 1 Adr Pre, Dev 1 Data 0
Figure 52 gives an example of the functional timing of the loop transmit interface when configured as a Any-PHY compliant transmit master. The S/UNI APEX
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
polls ports that it has a complete cell available for transfer. The receiving device responds by driving LTPA. Positive responses are recorded, and will eventually result in a data transfer. Polling continues independent of the data transfer state. Data transfers are initiated with the assertion of LTENB & LTSX, and complete without pausing. Figure 52
LTCLK LTADR [11:0]
PHY 0 PHY 7 PHY 1 PHY 0
- Loop Any-PHY Transmit Master
2 TCLK LTPA
PHY 0 PHY 1
LTDAT [m:0], LTPRTY LTENB LTSX LTSOP
Adr Pre, PHY 8
Data 1
Data 2
Data 3
Data K-1
Data K
AdrPre, PHY2
Data 1
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208
PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
18
ABSOLUTE MAXIMUM RATINGS Maximum rating are the worst case limits that the device can withstand without sustaining permanent damage. They are not indicative of normal mode operation conditions. Table 48 Parameter Storage Temperature Supply Voltage Voltage on Any Pin Static Discharge Voltage Latch-Up Current DC Input Current Lead Temperature Junction Temperature TJ IIN - Absolute Maximum Ratings Symbol TST VDD VIN Value -40C to +125C -0.3V to +4.6V 0V to VDDO+0.5V 1000 V 100 mA 10 mA +230C +150C
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209
PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
19
D.C. CHARACTERISTICS TA = -40C to +85C, VVDD = 3.3 V 0.3V, VPCH = 2.5 V 8% (Typical Conditions: TA = 25C, VVDD = 3.3 V, VPCH = 2.5 V ) Table 49
Symbol
- D.C. Characteristics
Parameter Min Typ Max Unit s Conditions
VDD
Pin Power Supply
3.0
3.3
3.6
Volts
PCH
Core Power Supply
2.3
2.5
2.7
Volts
VIL
Input Low Voltage
-0.3
0.8
Volts
VIH
Input High Voltage
2.0
5.5V
Volts
VOL
Output or Bidirectional Low Voltage
0.4
Volts
VDD = min, IOL = 2 mA, VI = VIL
VOH
Output or Bidirectional High Voltage
2.4
Volts
VDD = min, IOH = -2 mA, VI = VIH
VT+
Schmitt Input High Threshold Voltage
1.39
1.82
2.06
Volts
For pins RSTB & TRSTB
VT-
Schmitt Input Low Threshold Voltage
0.8
1.24
1.46
Volts
For pins RSTB & TRSTB
VTH
Schmitt Input Hysteresis Voltage
0.51
Volts
For pins RSTB & TRSTB
IILPU
Input Low Leak Current
+10
+100
A
VIL = GND. Notes 1, 3
IIHPU
Input High Leak Current
-10
+10
A
VIH = VDDO. Notes 1, 3
IIL
Input Low Leak Current
-10
+10
A
VIL = GND. Notes 2, 3
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
Symbol
Parameter
Min
Typ
Max
Unit s
Conditions
IIH
Input High Current
-10
+10
A
VIH = VDDO. Notes 2, 3
CIN
Input Capacitance
6
pF
Excluding Package, Package Typically 1 pF
COUT
Output Capacitance
6
pF
Excluding Package, Package Typically 1 pF
CIO
Bidirectional Capacitance
6
pF
Excluding Package, Package Typically 1 pF
IDDOP
Operating Current
513 (core) 99 (I/O unload ed) 410 (I/O loaded )
mA
TA = 85 degC VDD = VDD (max),, PCH = PCH (max) SYSCLK = 80MHz, BCLK = 66MHz WRCLK, WTCLK, LRCLK, LTCLK = 52MHz, all Any-PHY I/F in master modes 1.66Mcells/s Aggregate throughput I/O loaded: 80pF on Loop Any-PHY I/F 40pF on WAN Any-PHY I/F, SSRAM I/F 20pF on SDRAM I/F 50pF on uP I/F
Notes on D.C. Characteristics: 1. Input pin or bi-directional pin with internal pull-up resistor. 2. Input pin or bi-directional pin without internal pull-up resistor 3. Negative currents flow into the device (sinking), positive currents flow out of the device (sourcing).
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211
PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
20
A.C. TIMING CHARACTERISTICS (TA = -40C to +85C, VVDD = 3.3 V 0.3V, VPCH = 2.5 V 8%) Notes on Input Timing: 1. When a set-up time is specified between an input and a clock, the set-up time is measured from the 50% point of the input to the 50% point of the clock. 2. When a hold time is specified between a clock and an input, the hold time is measured from the 50% point of the clock to the 50% point of the input. Notes on Output Timing: 1. Output time is measured between the 50% point of the clock to the 50% point of the output. Figure 53 - RSTB Timing tV RSTB RSTB
Table 50 Symbol tVRSTB
- RTSB Timing Description RSTB Pulse Width Min 100 Max Units ns
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212
PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
Figure 54
CLK
- Synchronous I/O Timing
Ts Input
Th
Tp Tz Output Tzb
Table 51 Symbol fCLK DCLK Table 52 Symbol Ts Th Tp Tz Tzb
- SYSCLK Timing Description Frequency, SYSCLK Duty Cycle,SYSCLK - Cell Buffer SDRAM Interface Description Input Set-up time to SYSCLK Input Hold time to SYSCLK SYSCLK High to Output Valid SYSCLK High to Output High-Impedance SYSCLK High to Output Driven Min 2.4 0.7 1.25 1.25 1.25 7.0 8.0 Max Units ns ns ns ns ns Min 40 40 Max 80 60 Units MHz %
Maximum output propagation delays are measured with a 20pF load on the outputs. Minimum output propagation delays are measured with a 10 pF load on the outputs. Table 53 Symbol Ts - Context Memory ZBT & Late Write SSRAM Interface Description Input Set-up time to SYSCLK Min 2.4 Max Units ns
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213
PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
Symbol Th Tp Tz Tzb
Description Input Hold time to SYSCLK SYSCLK High to Output Valid SYSCLK High to Output High-Impedance SYSCLK High to Output Driven
Min 0.7 1.5 1.25 1.5
Max 8.25 8.25
Units ns ns ns ns
Maximum output propagation delays are measured with a 40pF load on the outputs. Minimum output propagation delays are measured with a 0 pF load on the outputs. Table 54 Symbol fCLK DCLK Ts Th Tp Tz Tzb - Microprocessor Interface Description Frequency, BCLK Duty Cycle, BCLK Input Set-up time to BCLK Input Hold time to BCLK BCLK High to Output Valid BCLK High to Output High-Impedance BCLK High to Output Driven Min 0 40 3.0 0.1 2.0 2.0 2.0 8.0 11.0 Max 66 60 Units MHz % ns ns ns ns ns
Maximum output propagation delays are measured with a 50pF load on the outputs. Minimum output propagation delays are measured with a 0 pF load on the outputs. Table 55 Symbol fCLK DCLK Ts Th - Loop Any-PHY Transmit Interface Description LTCLK Frequency LTCLK Duty Cycle Input Set-up time to LTCLK Input Hold time to LTCLK Min 5 40 4.0 0.0 Max 52 60 % ns ns Units
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
Symbol Tp Tz Tzb
Description LTCLK High to Output Valid LTCLK High to Output High-Impedance LTCLK High to Output Driven
Min 1.75 1.75 1.75
Max 10.0 12.0
Units ns ns ns
Maximum output propagation delays are measured with an 80pF load on the loop outputs. Minimum output propagation delays are measured with a 0 pF load on the outputs. Table 56 Symbol fCLK DCLK Ts Th Tp Tz Tzb - WAN Any-PHY Transmit Interface Description WTCLK Frequency WTCLK Duty Cycle Input Set-up time to WTCLK Input Hold time to WTCLK WTCLK High to Output Valid WTCLK High to Output High-Impedance WTCLK High to Output Driven Min 0 40 3.5 0.0 1.75 1.75 1.75 8.0 12.0 Max 52 60 % ns ns ns ns ns Units
Maximum output propagation delays are measured with a 40pF load on the WAN outputs. Minimum output propagation delays are measured with a 0 pF load on the outputs. Table 57 Symbol fCLK DCLK Ts Th Tp - Loop Any-PHY Receive Interface Description LRCLK Frequency LRCLK Duty Cycle Input Set-up time to LRCLK Input Hold time to LRCLK LRCLK High to Output Valid Min 0 40 3.0 0.25 1.75 9.0 Max 52 60 Units MHz % ns ns ns
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215
PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
Symbol Tz Tzb
Description LRCLK High to Output High-Impedance LRCLK High to Output Driven
Min 1.75 1.75
Max 12.0
Units ns ns
Maximum output propagation delays are measured with an 50pF load on the loop outputs. Minimum output propagation delays are measured with a 0 pF load on the outputs. Table 58 Symbol fCLK DCLK Ts Th Tp Tz Tzb - WAN Any-PHY Receive Interface Description WRCLK Frequency WRCLK Duty Cycle Input Set-up time to WRCLK Input Hold time to WRCLK WRCLK High to Output Valid WRCLK High to Output High-Impedance WRCLK High to Output Driven Min 0 40 2.0 0.35 1.75 1.75 1.75 9.0 12.0 Max 52 60 Units MHz % ns ns ns ns ns
Maximum output propagation delays are measured with a 40pF load on the WAN outputs. Minimum output propagation delays are measured with a 0 pF load on the outputs.
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216
PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
20.1 JTAG INTERFACE Figure 55 - JTAG Port Interface Timing
TCK tS TMS TMS tS TDI TDI tH TDI tH TMS
TCK tP TDO TDO
tV TRSTB TRSTB
Table 59 Symbol
- JTAG Port Interface Description Min Max Units
TCK Frequency
5
MHz
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217
PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
Symbol
Description
Min
Max
Units
TCK Duty Cycle tSTMS tHTMS tSTDI tHTDI tPTDO TMS Setup time to TCK TMS Hold time to TCK TDI Setup time to TCK TDI Hold time to TCK TCK Low to TDO Valid
40 50 50 50 50 2 100
60
% ns ns ns ns
50
ns ns
tVTRSTB TRSTB Pulse Width
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
21
ORDERING AND THERMAL INFORMATION Part No. Description
PM7326-BI
352 Ball Grid Array Package (SBGA)
Theta JC < 1 degC/W
Theta JA degC/W @ 2.86W Conv
18.5 13.0
Forced Air (Linear Feet per Minute) 100
16.4 12.0
200
15.1 11.3
300
14.2 10.8
400
13.8 10.3
500
13.7 9.7
Dense Board JEDEC Board Notes:
1. DENSE Board is defined as a 3S3P board and consists of a 3x3 array of device PM7326 located as close to each other as board design rules allow. All PM7326 devices are assumed to be dissipating 2.86 Watts. JA listed is for the device in the middle of the array. 2. JEDEC Board JA is the measured value for a single thermal device in the same package on a 2S2P board following EIA/JESD 51-3
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219
PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
22
MECHANICAL INFORMATION Figure 56 - Mechanical Drawing 352 Pin Ball Grid Array (SBGA)
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220
PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
NOTES
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PM7326 S/UNI APEX
DATA SHEET PMC-1981224 ISSUE 6 ATM/PACKET TRAFFIC MANAGER AND SWITCH
CONTACTING PMC-SIERRA, INC.
PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com (604) 415-4533 http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 2000 PMC-Sierra, Inc. PMC-981224 (P6) ref PMC-970790 (R5) Issue date: April 2000
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