 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Order Number: MPC750EC/D Rev. 2.3, 9/2001 Semiconductor Products Sector Technical Data MPC750A RISC Microprocessor Hardware Specifications This document is primarily concerned with the MPC750, however, unless otherwise noted, all information here applies also to the MPC740. The MPC750 and MPC740 are implementations of the PowerPCTM family of reduced instruction set computing (RISC) microprocessors. This document describes pertinent physical characteristics of the MPC750. For functional characteristics of the processor, refer to the MPC750 RISC Microprocessor User's Manual. The MPC750 (and MPC740) is implemented in several semiconductor fabrication processes. Different processes may require different supply voltages and may have other electrical differences but will have the same functionality. As a designator to distinguish between MPC750 implementations in various processes, a suffix is added to the MPC750 part number as shown below: Table 1. MPC750 Microprocessors from Motorola Part Number MPC750A, MPC740A XPC750P, XPC740P Process 0.29 m CMOS, 5LM 0.25 m CMOS, 5LM Core Voltage 2.6 V 1.9 V I/O Voltage 3.3 V 3.3 V 5-Volt Tolerant No No This document will describe only the MPC750A implementation. The XPC750P is described in a separate document. This document contains information on a new product under development by Motorola. Motorola reserves the right to change or discontinue this product without notice. (c) Motorola, Inc., 2001. All rights reserved. This document contains the following topics: Topic Page Section 1.1, "Overview" Section 1.2, "Features" Section 1.3, "General Parameters" Section 1.4, "Electrical and Thermal Characteristics" Section 1.4.1, "DC Electrical Characteristics" Section 1.4.2, "AC Electrical Characteristics" Section 1.4.2.1, "Clock AC Specifications" Section 1.4.2.2, "60x Bus Input AC Specifications" Section 1.4.2.3, "60x Bus Output AC Specifications" Section 1.4.2.4, "L2 Clock AC Specifications" Section 1.4.2.5, "L2 Bus Input AC Specifications" Section 1.4.2.6, "L2 Bus Output AC Specifications" Section 1.5, "Pin Assignments" Section 1.6, "Pinout Listings" Section 1.7, "Package Description" Section 1.8, "System Design Information" Section 1.9, "Document Revision History To locate any published errata or updates for this document, refer to the website at http://www.mot.com/PowerPC/. 3 4 6 6 6 10 10 12 14 15 18 19 23 25 29 31 42 2 MPC750A RISC Microprocessor Hardware Specifications Overview 1.1 Overview The MPC750 is targeted for low-cost, low-power systems and supports the following power management features--doze, nap, sleep, and dynamic power management. The MPC750 consists of a processor core and an internal L2 Tag combined with a dedicated L2 cache interface and a 60x bus. Figure 1 shows a block diagram of the MPC750. Control Unit Instruction Fetch Branch Unit Completion 32K ICache System Unit Dispatch BHT/BTIC GPRs FXU1 FXU2 Rename Buffers LSU FPRs Rename Buffers FPU L2 Cache 32K DCache L2 Tags BIU 60x BIU Figure 1. MPC750 Block Diagram MPC750A RISC Microprocessor Hardware Specifications 3 Features 1.2 Features This section summarizes features of the MPC750's implementation of the PowerPC architecture. Major features of the MPC750 are as follows: * Branch processing unit -- Four instructions fetched per clock -- One branch processed per cycle (plus resolving 2 speculations) -- Up to 1 speculative stream in execution, 1 additional speculative stream in fetch -- 512-entry branch history table (BHT) for dynamic prediction -- 64-entry, 4-way set associative branch target instruction cache (BTIC) for eliminating branch delay slots Dispatch unit -- Full hardware detection of dependencies (resolved in the execution units) -- Dispatch two instructions to six independent units (system, branch, load/store, fixed-point unit 1, fixed-point unit 2, or floating-point) -- Serialization control (predispatch, postdispatch, execution serialization) Decode -- Register file access -- Forwarding control -- Partial instruction decode Load/store unit -- One cycle load or store cache access (byte, half-word, word, double-word) -- Effective address generation -- Hits under misses (one outstanding miss) -- Single-cycle misaligned access within double word boundary -- Alignment, zero padding, sign extend for integer register file -- Floating-point internal format conversion (alignment, normalization) -- Sequencing for load/store multiples and string operations -- Store gathering -- Cache and TLB instructions -- Big- and little-endian byte addressing supported -- Misaligned little-endian support in hardware Fixed-point units -- Fixed-point unit 1 (FXU1)--multiply, divide, shift, rotate, arithmetic, logical -- Fixed-point unit 2 (FXU2)--shift, rotate, arithmetic, logical -- Single-cycle arithmetic, shift, rotate, logical -- Multiply and divide support (multi-cycle) -- Early out multiply Floating-point unit -- Support for IEEE-754 standard single- and double-precision floating-point arithmetic -- 3 cycle latency, 1 cycle throughput, single-precision multiply-add * * * * * 4 MPC750A RISC Microprocessor Hardware Specifications Features * * * * * * -- 3 cycle latency, 1 cycle throughput, double-precision add -- 4 cycle latency, 2 cycle throughput, double-precision multiply-add -- Hardware support for divide -- Hardware support for denormalized numbers -- Time deterministic non-IEEE mode System unit -- Executes CR logical instructions and miscellaneous system instructions -- Special register transfer instructions Cache structure -- 32K, 32-byte line, 8-way set associative instruction cache -- 32K, 32-byte line, 8-way set associative data cache -- Single-cycle cache access -- Pseudo-LRU replacement -- Copy-back or write-through data cache (on a page per page basis) -- Supports all PowerPC memory coherency modes -- Non-blocking instruction and data cache (one outstanding miss under hits) -- No snooping of instruction cache Memory management unit -- 128 entry, 2-way set associative instruction TLB -- 128 entry, 2-way set associative data TLB -- Hardware reload for TLBs -- 4 instruction BATs and 4 data BATs -- Virtual memory support for up to 4 exabytes (252) of virtual memory -- Real memory support for up to 4 gigabytes (232) of physical memory Level 2 (L2) cache interface (not implemented on MPC740) -- Internal L2 cache controller and 4K-entry tags; external data SRAMs -- 256K, 512K, and 1 Mbyte 2-way set associative L2 cache support -- Copy-back or write-through data cache (on a page basis, or for all L2) -- 64-byte (256K/512K) and 128-byte (1-Mbyte) sectored line size -- Supports flow-through (reg-buf) synchronous burst SRAMs, pipelined (reg-reg) synchronous burst SRAMs, and pipelined (reg-reg) late-write synchronous burst SRAMs -- Core-to-L2 frequency divisors of /1, /1.5, /2, /2.5, and /3 supported Bus interface -- Compatible with 60x processor interface -- 32-bit address bus -- 64-bit data bus -- Bus-to-core frequency multipliers of 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x supported Integrated power management -- Low-power 2.6/3.3-volt design -- Three static power saving modes: doze, nap, and sleep MPC750A RISC Microprocessor Hardware Specifications 5 General Parameters * * * -- Automatic dynamic power reduction when internal functional units are idle Integrated Thermal Management Assist Unit -- On-chip thermal sensor and control logic -- Thermal Management Interrupt for software regulation of junction temperature. Testability -- LSSD scan design -- JTAG interface Reliability and serviceability--Parity checking on 60x and L2 cache buses 1.3 General Parameters The following list provides a summary of the general parameters of the MPC750: Technology: Die size: Transistor count Logic design Packages 0.29 m CMOS, five-layer metal 7.56 mm x 8.79 mm (67 mm2) 6.35 million Fully-static MPC740: Surface mount 255 ceramic ball grid array (CBGA) without L2 interface MPC750: Surface mount 360 ceramic ball grid array (CBGA) with L2 interface Core power supply: I/O power supply 2.6V 100 mV 3.3V 5% V dc 1.4 Electrical and Thermal Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC750. 1.4.1 DC Electrical Characteristics The tables in this section describe the MPC750 DC electrical characteristics. Table 2 provides the absolute maximum ratings. Table 2. Absolute Maximum Ratings Characteristic Core supply voltage PLL supply voltage L2 DLL supply voltage 60x bus supply voltage Symbol Vdd AVdd L2AVdd OVdd MPC750A Value -0.3 to 2.75 -0.3 to 2.75 -0.3 to 2.75 -0.3 to 3.6 Unit V V V V Notes 4 4 4 3,5 6 MPC750A RISC Microprocessor Hardware Specifications Electrical and Thermal Characteristics Table 2. Absolute Maximum Ratings (Continued) Characteristic L2 bus supply voltage Input voltage Storage temperature range Notes: 1. Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: Vin must not exceed OVdd/L2OVdd by more than 0.3V at any time including during power-on reset. 3. Caution: OVdd/L2OVdd must not exceed Vdd/AVdd by more than 1.2V at any time including during power-on reset. 4. Caution: Vdd/AVdd/L2AVdd must not exceed OVdd/L2OVdd by more than 0.4V at any time including during power-on reset. 5. Vin may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2 Symbol L2OVdd Vin Tstg MPC750A Value -0.3 to 3.6 -0.3 to 3.6 -55 to 150 Unit V V C Notes 3,5 2 Figure 2 shows the allowable undershoot and overshoot voltage on the MPC750. 4V (L2)OVdd + 5% (L2)OVdd VIH VIL Gnd Gnd - .3V Gnd - 1.0V Not to exceed 10% of tSYSCLK Figure 2. Overshoot/Undershoot Voltage Table 3 provides the recommended operating conditions for the MPC750. Table 3. Recommended Operating Conditions Characteristic Core supply voltage PLL supply voltage L2 DLL supply voltage 60x bus supply voltage Vdd AVdd L2AVdd OVdd Symbol MPC750A Value Unit V V V V Notes 2.6 100mv 2.6 100mv 2.6 100mv 3.135 to 3.465 MPC750A RISC Microprocessor Hardware Specifications 7 Electrical and Thermal Characteristics Table 3. Recommended Operating Conditions (Continued) Characteristic L2 bus supply voltage Input voltage Die-junction temperature Symbol L2OVdd Vin Tj Tj MPC750A Value 2.5 to 3.465 GND to OVdd 0 to 105 -40 to 105 Unit V V C C 1 Notes Note: These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. 1. For extended temperature parts marked MPC750ARXnnnTH or MPC740ARXnnnTH only (where nnn is the operating frequency from Table 8. Table 4 provides the package thermal characteristics for the MPC750. Table 4. Package Thermal Characteristics Characteristic CBGA package thermal resistance, junction-to-case thermal resistance (typical) CBGA package thermal resistance, die junction-to-lead thermal resistance (typical) Symbol JC JB Value 0.03 3.8 Rating C/W C/W Note: Refer to Section 1.8, "System Design Information," for more details about thermal management. The MPC750 incorporates a thermal management assist unit (TAU) composed of a thermal sensor, digital-to-analog converter, comparator, control logic, and dedicated special-purpose registers (SPRs). See the MPC750 RISC Microprocessor User's Manual for more information on the use of this feature. Specifications for the thermal sensor portion of the TAU are found in Table 5. Table 5. Thermal Sensor Specifications At recommended operating conditions (See Table 3) Num 1 2 3 Characteristic Temperature range Comparator settling time Resolution Min 0 20 4 Max 127 -- -- Unit C s C Notes 1 2 3 Notes: 1. The temperature is the junction temperature of the die. The thermal assist unit's raw output does not indicate an absolute temperature, but it must be interpreted by software to derive the absolute junction temperature. For information about the use and calibration of the TAU, see Motorola Application Note AN1800/D, "Programming the Thermal Assist Unit in the MPC750 Microprocessor". 2. The comparator settling time value must be converted into the number of CPU clocks that need to be written into the THRM3 SPR. 3. Guaranteed by design and characterization. 8 MPC750A RISC Microprocessor Hardware Specifications Electrical and Thermal Characteristics Table 6 provides the DC electrical characteristics for the MPC750. Table 6. DC Electrical Specifications At recommended operating conditions (See Table 3) Characteristic Input high voltage (all inputs except SYSCLK) Symbol VIH VIH Min 1.7 2 -0.3 -0.3 2.4 -0.3 -- -- 1.8 2.4 -- -- Max L2OVdd + 0.3 OVdd + 0.3 0.2 * L2OVdd 0.8 OVdd + 0.3 0.4 30 30 -- -- 0.4 5.0 Unit V V V V V V A A V V V pF Notes 2,3,4 2,3, 4 Input low voltage (all inputs except SYSCLK) VIL VIL SYSCLK input high voltage SYSCLK input low voltage Input leakage current, Vin = OVdd Hi-Z (off-state) leakage current, Vin = OVdd Output high voltage, IOH = -6 mA CVIH CVIL Iin ITSI VOH VOH 2 2,3 2,3,6 Output low voltage, IOL = 6 mA Capacitance, Vin = 0 V, f = 1 MHz VOL Cin 3,5 Notes: 1. Nominal voltages; See Table 3 for recommended operating conditions. 2. For 60x bus signals, the reference is OVdd while L2OVdd is the reference for the L2 bus signals. 3. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK) and IEEE 1149.1 boundary scan (JTAG) signals. 4. Applicable to L2 bus interface only 5. Capacitance is periodically sampled rather than 100% tested. 6. The leakage is measured for nominal OVdd and Vdd, or both OVdd and Vdd must vary in the same direction (for example, both OVdd and Vdd vary by either +5% or -5%). Table 7 provides the power consumption for the MPC750. Table 7. Power Consumption for MPC750 Processor (CPU) Frequency Unit 200 MHz Full-On Mode Typical Maximum Doze Mode Maximum Nap Mode Maximum Sleep Mode Maximum 300 300 300 mW 1, 2 250 250 250 mW 1, 2 1.6 1.8 2.1 W 1, 2 4.2 6.0 5.0 7.0 5.7 7.9 W W 1, 3, 4 1, 2, 4 233 MHz 266 MHz Notes MPC750A RISC Microprocessor Hardware Specifications 9 Electrical and Thermal Characteristics Table 7. Power Consumption for MPC750 (Continued) Processor (CPU) Frequency Unit 200 MHz Sleep Mode--PLL and DLL Disabled Typical Maximum 30 60 50 100 50 100 mW mW 1, 3 1, 2 233 MHz 266 MHz Notes Notes: 1. These values apply for all valid 60x bus and L2 bus ratios. The values do not include I/O Supply Power (OVdd and L2OVdd) or PLL/DLL supply power (AVdd and L2AVdd). OVdd and L2OVdd power is system dependent, but is typically <10% of Vdd power. Worst case power consumption for AVdd = 15 mW and L2AVdd = 15 mW. 2. Maximum power is measured at Vdd = 2.7V. 3. Typical power is an average value measured at Vdd = AVdd = L2AVdd = 2.6V, OVdd = L2OVdd = 3.3V in a system executing typical applications and benchmark sequences. 4. Full-On mode is measured using worst-case instruction sequence. 1.4.2 AC Electrical Characteristics This section provides the AC electrical characteristics for the MPC750. After fabrication, parts are sorted by maximum processor core frequency as shown in Section 1.4.2.1, "Clock AC Specifications," and tested for conformance to the AC specifications for that frequency. The processor core frequency is determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[0-3] signals. Parts are sold by maximum processor core frequency; see Section 1.10, "Ordering Information". 1.4.2.1 Clock AC Specifications Table 8 provides the clock AC timing specifications as defined in Figure 3. Table 8. Clock AC Timing Specifications At recommended operating conditions (See Table 3) 200 MHz Num Characteristic Min Processor frequency 150 VCO frequency SYSCLK frequency 1 2, 3 SYSCLK cycle time 300 25 12 Max 200 400 83.3 40 2 233 MHz Min 150 300 25 12 -- Max 233 466 83.3 40 2 266 MHz Unit Min 150 300 25 12 -- Max 266 533 83.3 40 2 MHz MHz MHz ns ns 2 1 Notes SYSCLK rise and fall -- time 10 MPC750A RISC Microprocessor Hardware Specifications Electrical and Thermal Characteristics Table 8. Clock AC Timing Specifications (Continued) At recommended operating conditions (See Table 3) 200 MHz Num 4 Characteristic Min SYSCLK duty cycle measured at 1.4V SYSCLK jitter Internal PLL relock time 40 -- -- Max 60 150 100 233 MHz Min 40 -- -- Max 60 150 100 266 MHz Unit Min 40 -- -- Max 60 150 100 % ps s 3 4 5 Notes Notes: 1. Caution: The SYSCLK frequency and PLL_CFG[0-3] settings must be chosen such that the resulting SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0-3] signal description in Section 1.8.1, "PLL Configuration," for valid PLL_CFG[0-3] settings 2. Rise and fall times for the SYSCLK input are measured from 0.4 to 2.4V. 3. Timing is guaranteed by design and characterization. 4. The total input jitter (short term and long term combined) must be under 150 ps. 5. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for PLL lock after a stable Vdd and SYSCLK are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence. Figure 3 provides the SYSCLK input timing diagram. 1 4 4 CVIH 2 3 SYSCLK VM VM VM CVIL VM = Midpoint Voltage (1.4V) Figure 3. SYSCLK Input Timing Diagram MPC750A RISC Microprocessor Hardware Specifications 11 Electrical and Thermal Characteristics 1.4.2.2 60x Bus Input AC Specifications Table 9 provides the 60x bus input AC timing specifications for the MPC750 as defined in Figure 4 and Figure 5. Input timing specifications for the L2 bus are provided in Section 1.4.2.5, "L2 Bus Input AC Specifications. Table 9. 60x Bus Input AC Timing Specifications1 At recommended operating conditions (See Table 3) 200, 233, 266 MHz Num 10a 10b 10c 11a 11b 11c Characteristic Min Address/Data/Transfer Attribute Inputs Valid 2.5 to SYSCLK (Input Setup) All Other Inputs Valid to SYSCLK (Input Setup) Mode select input setup to HRESET (DRTRY, TLBISYNC) 3.0 8 -- -- -- -- -- -- Max ns ns 2 3 Unit Notes tsysclk 4,5,6,7 ns ns ns 2 3 4,6,7 SYSCLK to Address/Data/Transfer Attribute 0 Inputs Invalid (Input Hold) SYSCLK to All Other Inputs Invalid (Input Hold) 0 HRESET to mode select input hold (DRTRY, 0 TLBISYNC) Notes: 1. All input specifications are measured from the TTL level (0.8 to 2.0V) of the signal in question to the 1.4V of the rising edge of the input SYSCLK. Input and output timings are measured at the pin. 2. Address/Data/Transfer Attribute inputs are composed of the following--A[0-31], AP[0-3], TT[0-4], TBST, TSIZ[0-2], GBL, DH[0-31], DL[0-31], DP[0-7]. 3. All other signal inputs are composed of the following--TS, ABB, DBB, ARTRY, BG, AACK, DBG, DBWO, TA, DRTRY, TEA, DBDIS, HRESET, SRESET, INT, SMI, MCP, TBEN, QACK, TLBISYNC. 4. The setup and hold time is with respect to the rising edge of HRESET (see Figure 5). 5. tsysclk is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question. 6. Guaranteed by design and characterization. 7. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a minimum of 255 bus clocks after the PLL re-lock time during the power-on reset sequence. 12 MPC750A RISC Microprocessor Hardware Specifications Electrical and Thermal Characteristics Figure 4 provides the input timing diagram for the MPC750. SYSCLK 10a 10b VM 11a 11b ALL INPUTS VM = Midpoint Voltage (1.4V) Figure 4. Input Timing Diagram Figure 5 provides the mode select input timing diagram for the MPC750. HRESET 10c VIH 11c MODE PINS VIH = 2.0V Figure 5. Mode Select Input Timing Diagram MPC750A RISC Microprocessor Hardware Specifications 13 Electrical and Thermal Characteristics 1.4.2.3 60x Bus Output AC Specifications Table 10 provides the 60x bus output AC timing specifications for the MPC750 as defined in Figure 6. Output timing specifications for the L2 bus are provided in Section 1.4.2.6, "L2 Bus Output AC Specifications." Table 10. 60x Bus Output AC Timing Specifications1 At recommended operating conditions (See Table 3), CL = 50 pF2 200, 233, 266 MHz Num 12 13 14 15 16 17 18 19 20 21 Characteristic Min SYSCLK to Output Driven (Output Enable 0.5 Time) SYSCLK to Output Valid (TS, ABB, ARTRY, -- DBB) SYSCLK to all other Outputs Valid (all except TS, ABB, ARTRY, DBB) SYSCLK to Output Invalid (Output Hold) SYSCLK to Output High Impedance (all except ABB, ARTRY, DBB) SYSCLK to ABB, DBB High Impedance after precharge SYSCLK to ARTRY High Impedance before precharge SYSCLK to ARTRY Precharge Enable Maximum Delay to ARTRY Precharge -- 1.0 -- -- -- 0.2*tsysclk +1.0 -- -- 6.5 6.5 -- 6.0 1.0 5.5 -- 1 2 Max ns ns ns ns ns tsysclk ns ns tsysclk tsysclk 5 5 3 8 4,6,8 8 3,4,7 4,7 4,7,8 Unit Notes SYSCLK to ARTRY High Impedance After -- Precharge Notes: 1. All output specifications are measured from the 1.4V of the rising edge of SYSCLK to TTL level (0.8 V or 2.0 V) of the signal in question. Both input and output timing are measured at the pin. 2. All maximum timing specifications assume CL = 50 pF. 3. This minimum parameter assumes CL = 0 pF. 4. tsysclk is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration of the parameter in question. 5. Output signal transitions from GND to 2.0V or OVdd to 0.8V. 6. Nominal precharge width for ABB and DBB is 0.5 tsysclk. 7. Nominal precharge width for ARTRY is 1.0 tsysclk. 8. Guaranteed by design and characterization. 14 MPC750A RISC Microprocessor Hardware Specifications Electrical and Thermal Characteristics Figure 6 provides the output timing diagram for the MPC750. SYSCLK VM VM VM 14 12 15 16 ALL OUTPUTS (Except TS, ABB, ARTRY, DBB) 13 13 15 16 TS 17 ABB, DBB 21 20 19 18 ARTRY VM = Midpoint Voltage (1.4V) Figure 6. Output Timing Diagram 1.4.2.4 L2 Clock AC Specifications Table 11 provides the L2CLK output AC timing specifications as defined in Figure 7. Table 11. L2CLK Output AC Timing Specifications At recommended operating conditions (See Table 3) Num L2CLK frequency 22 23 Characteristic 80 7.5 50 Min Max 133 12.5 Unit MHz ns % Notes 1,4 L2CLK cycle time L2CLK duty cycle 2 MPC750A RISC Microprocessor Hardware Specifications 15 Electrical and Thermal Characteristics Table 11. L2CLK Output AC Timing Specifications (Continued) At recommended operating conditions (See Table 3) Num Characteristic Internal DLL-relock time L2CLKOUT output-to-output skew L2CLKOUT output jitter 640 Min -- 50 Max Unit L2CLK ps ps Notes 3 5 5 150 Notes: 1. L2CLK outputs are L2CLK_OUTA, L2CLK_OUTB and L2SYNC_OUT pins. The L2 cache interface supports higher frequencies when appropriate load conditions have been considered. The L2 I/O drivers have been designed to support a 133 MHz L2 bus loaded with 4 off-the-shelf pipelined synchronous burst SRAMs. Running the L2 bus beyond 133 MHz requires tightly coupled customized SRAMs or a multi-chip module (MCM) implementation. The L2CLK frequency to core frequency settings must be chosen such that the resulting L2CLK frequency and core frequency do not exceed their respective maximum or minimum operating frequencies. L2CLK_OUTA and L2CLK_OUTB must have equal loading. 2. The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage. 3. The DLL re-lock time is specified in terms of L2CLKs. The number in the table must be multiplied by the period of L2CLK to compute the actual time duration in nanoseconds. Re-lock timing is guaranteed by design and characterization. 4. The L2CR[L2SL] bit should be set for L2CLK frequencies less than 110 MHz 5. Guaranteed by design and not tested. 16 MPC750A RISC Microprocessor Hardware Specifications Electrical and Thermal Characteristics The L2CLK_OUT timing diagram is shown in Figure 7. L2 Single-Ended Clock Mode 22 23 VM VM VM L2CLK_OUTA VM VM VM L2CLK_OUTB VM VM VM L2SYNC_OUT VM = Midpoint Voltage (L2OVdd/2) L2 Differential Clock Mode 22 L2OVdd L2CLK_OUTB VM 23 VM VM L2CLK_OUTA GND VM VM VM L2SYNC_OUT VM = Midpoint Voltage (L2OVdd/2) Figure 7. L2CLK_OUT Output Timing Diagram MPC750A RISC Microprocessor Hardware Specifications 17 Electrical and Thermal Characteristics 1.4.2.5 L2 Bus Input AC Specifications The L2 bus input interface AC timing specifications are found in Table 12. Table 12. L2 Bus Input Interface AC Timing Specifications1 At recommended operating conditions (See Table 3) Num Characteristic Processor Frequency 200-266 MHz Min Max 1.0 -- -- ns ns ns Unit Notes 29,30 24 25 L2SYNC_IN rise and fall time Data and parity input setup to L2SYNC_IN L2SYNC_IN to data and parity input hold -- 2.0 0.5 2 Notes: 1. All input specifications are measured from the TTL level (0.8V or 2.0V) of the signal in question to the midpoint voltage of the rising edge of the input L2SYNC_IN. Input timings are measured at the pins (see Figure 8). 2. Rise and fall times for the L2SYNC_IN input are measured from 0.4 to 2.4V. Figure 8 shows the L2 bus input timing diagrams for the MPC750. 29 30 L2SYNC_IN VM 24 25 ALL INPUTS VM = Midpoint Voltage (1.4V) Figure 8. L2 Bus Input Timing Diagrams 18 MPC750A RISC Microprocessor Hardware Specifications Electrical and Thermal Characteristics 1.4.2.6 L2 Bus Output AC Specifications Table 13 provides the L2 bus output interface AC timing specifications for the MPC750 as defined in Figure 9. Table 13. L2 Bus Output Interface AC Timing Specifications1 At recommended operating conditions (See Table 3), CL = 20 pF3 Num Characteristic L2CR[14-15] Core Freq 200-266MHz Min Max 5.0 5.5 5.7 6.0 -- -- -- -- 4.0 4.5 4.7 5.0 26 L2SYNC_IN to output valid 002 01 10 11 -- -- -- -- 0.5 1.0 1.2 1.5 -- -- -- -- 27 L2SYNC_IN to output hold 002 01 10 11 28 L2SYNC_IN to high impedance 002 01 10 11 Notes: 1. All outputs are measured from the midpoint voltage of the rising edge of L2SYNC_IN to the TTL level (0.8V or 2.0V) of the signal in question. The output timings are measured at the pins. 2.The outputs are valid for both single-ended and differential L2CLK modes. For flow-thru and pipelined reg-reg synchronous burst RAMs, L2CR[14-15] = 00 is recommended. For pipelined delay-write synchronous burst SRAMs, L2CR[14-15] = 01 is recommended. 3. All maximum timing specifications assume CL =20 pF. 4. This measurement assumes CL = 5 pF. Figure 9 shows the L2 bus output timing diagrams for the MPC750. MPC750A RISC Microprocessor Hardware Specifications 19 Electrical and Thermal Characteristics VM VM L2SYNC_IN 26 27 ALL OUTPUTS 28 L2DATA BUS VM = Midpoint Voltage (1.4V) Figure 9. L2 Bus Output Timing Diagrams 1.4.3 IEEE 1149.1 AC Timing Specifications Table 14 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 10, Figure 11, Figure 12, and Figure 13. Table 14. JTAG AC Timing Specifications (Independent of SYSCLK) At recommended operating conditions (See Table 3), CL = 50 pF Num Characteristic TCK frequency of operation 0 30 15 0 Min Max 33.3 -- -- 2 Unit MHz ns ns ns Notes 1 2 3 4 5 6 7 8 9 10 TCK cycle time TCK clock pulse width measured at 1.4V TCK rise and fall times Specification obsolete, intentionally omitted TRST assert time Boundary-scan input data setup time Boundary-scan input data hold time TCK to output data valid TCK to output high impedance TMS, TDI data setup time 25 4 15 4 3 0 -- -- -- 20 19 -- ns ns ns ns ns ns 1 2 2 3 3, 4 20 MPC750A RISC Microprocessor Hardware Specifications Electrical and Thermal Characteristics Table 14. JTAG AC Timing Specifications (Independent of SYSCLK) (Continued) At recommended operating conditions (See Table 3), CL = 50 pF Num 11 12 13 Characteristic TMS, TDI data hold time TCK to TDO data valid TCK to TDO high impedance 12 4 3 Min -- Max Unit ns ns ns Notes 12 9 4 Notes: 1. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only. 2. Non-JTAG signal input timing with respect to TCK. 3. Non-JTAG signal output timing with respect to TCK. 4. Guaranteed by design and characterization. Figure 10 provides the JTAG clock input timing diagram. 1 2 2 VM VM TCK 3 3 VM VM = Midpoint Voltage Figure 10. JTAG Clock Input Timing Diagram Figure 11 provides the TRST timing diagram. TRST 5 Figure 11. TRST Timing Diagram MPC750A RISC Microprocessor Hardware Specifications 21 Electrical and Thermal Characteristics Figure 12 provides the boundary-scan timing diagram. TCK 6 7 DATA INPUTS 8 INPUT DATA VALID DATA OUTPUTS 9 OUTPUT DATA VALID DATA OUTPUTS 8 DATA OUTPUTS OUTPUT DATA VALID Figure 12. Boundary-Scan Timing Diagram Figure 13 provides the test access port timing diagram. TCK 10 11 TDI, TMS 12 INPUT DATA VALID TDO 13 OUTPUT DATA VALID TDO 12 TDO OUTPUT DATA VALID Figure 13. Test Access Port Timing Diagram 22 MPC750A RISC Microprocessor Hardware Specifications Pin Assignments 1.5 Pin Assignments Figure 14 (in part A) shows the pinout of the MPC740, 255 CBGA package as viewed from the top surface. Part B shows the side profile of the CBGA package to indicate the direction of the top surface view. Part A 1 A B C D E F G H J K L M N P R T Not to Scale Part B Substrate Assembly Encapsulant View Die 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Figure 14. Pinout of the MPC740, 255 CBGA Package as Viewed from the Top Surface MPC750A RISC Microprocessor Hardware Specifications 23 Pin Assignments Figure 15 (in part A) shows the pinout of the MPC750, 360 CBGA package as viewed from the top surface. Part B shows the side profile of the CBGA package to indicate the direction of the top surface view. Part A 1 A B C D E F G H J K L M N P R T U V W Not to Scale Part B Substrate Assembly Encapsulant View Die 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Figure 15. Pinout of the MPC750, 360 CBGA Package as Viewed from the Top Surface 24 MPC750A RISC Microprocessor Hardware Specifications Pinout Listings 1.6 Pinout Listings Table 15 provides the pinout listing for the MPC740, 255 CBGA package. Table 15. Pinout Listing for the MPC740, 255 CBGA Package Signal Name A[0-31] Pin Number C16, E4, D13, F2, D14, G1, D15, E2, D16, D4, E13, G2, E15, H1, E16, H2, F13, J1, F14, J2, F15, H3, F16, F4, G13, K1, G15, K2, H16, M1, J15, P1 L2 K4 C1, B4, B3, B2 J4 A10 L1 B6 E1 D8 A6 D7 J14 N1 H15 G4 P14, T16, R15, T15, R13, R12, P11, N11, R11, T12, T11, R10, P9, N9, T10, R9, T9, P8, N8, R8, T8, N7, R7, T7, P6, N6, R6, T6, R5, N5, T5, T4 K13, K15, K16, L16, L15, L13, L14, M16, M15, M13, N16, N15, N13, N14, P16, P15, R16, R14, T14, N10, P13, N12, T13, P3, N3, N4, R3, T1, T2, P4, T3, R4 M2, L3, N2, L4, R1, P2, M4, R2 G16 F1 C5, C12, E3, E6, E8, E9, E11, E14, F5, F7, F10, F12, G6, G8, G9, G11, H5, H7, H10, H12, J5, J7, J10, J12, K6, K8, K9, K11, L5, L7, L10, L12, M3, M6, M8, M9, M11, M14, P5, P12 A7 B15 1 Active High I/O I/O AACK ABB AP[0-3] ARTRY AVDD BG BR CI CKSTP_IN CKSTP_OUT CLK_OUT DBB DBG DBDIS DBWO DH[0-31] DL[0-31] Low Low High Low -- Low Low Low Low Low -- Low Low Low Low High High Input I/O I/O I/O -- Input Output Output Input Output Output I/O Input Input Input I/O I/O DP[0-7] DRTRY GBL GND High Low Low -- I/O Input I/O -- HRESET INT L1_TSTCLK L2_TSTCLK 1 LSSD_MODE 1 MCP NC (No-Connect) OVDD PLL_CFG[0-3] Low Low High High Low Low -- -- High Input Input Input Input Input Input -- -- Input D11 D12 B10 C13 B7, B8, C3, C6, C8, D5, D6, H4, J16, A4, A5, A2, A3, B1, B5 C7, E5, E7, E10, E12, G3, G5, G12, G14, K3, K5, K12, K14, M5, M7, M10, M12, P7, P10 A8, B9, A9, D9 MPC750A RISC Microprocessor Hardware Specifications 25 Pinout Listings Table 15. Pinout Listing for the MPC740, 255 CBGA Package (Continued) Signal Name QACK QREQ RSRV SMI SRESET SYSCLK TA TBEN TBST TCK TDI TDO TEA TLBISYNC TMS TRST TS TSIZ[0-2] TT[0-4] WT VDD 2 VOLTDET 3 Notes: 1. These are test signals for factory use only and must be pulled up to OVdd for normal machine operation. 2. OVdd inputs supply power to the I/O drivers and Vdd inputs supply power to the processor core. 3. Internally tied to GND in the MPC740 CBGA package to indicate to the power supply that a low-voltage processor is present. This signal is not a power supply input. D3 J3 D1 A16 B14 C9 H14 C2 A14 C11 A11 A12 H13 C4 B11 C10 J13 A13, D10, B12 B13, A15, B16, C14, C15 D2 F6, F8, F9, F11, G7, G10, H6, H8, H9, H11, J6, J8, J9, J11, K7, K10, L6, L8, L9, L11 F3 Pin Number Active Low Low Low Low Low -- Low High Low High High High Low Low High Low Low High High Low -- High I/O Input Output Output Input Input Input Input Input I/O Input Input Output Input Input Input Input I/O Output I/O Output -- Output Table 16 provides the pinout listing for the MPC750, 360 CBGA package. Table 16. Pinout Listing for the MPC750, 360 CBGA Package Signal Name A[0-31] AACK ABB AP[0-3] ARTRY AVDD BG Pin Number A13, D2, H11, C1, B13, F2, C13, E5, D13, G7, F12, G3, G6, H2, E2, L3, G5, L4, G4, J4, H7, E1, G2, F3, J7, M3, H3, J2, J6, K3, K2, L2 N3 L7 C4, C5, C6, C7 L6 A8 H1 Active High Low Low High Low -- Low I/O I/O Input I/O I/O I/O -- Input 26 MPC750A RISC Microprocessor Hardware Specifications Pinout Listings Table 16. Pinout Listing for the MPC750, 360 CBGA Package (Continued) Signal Name BR CKSTP_OUT CI CKSTP_IN CLKOUT DBB DBDIS DBG DBWO DH[0-31] DL[0-31] DP[0-7] DRTRY GBL GND E7 D7 C2 B8 E3 K5 G1 K1 D1 W12, W11, V11, T9, W10, U9, U10, M11, M9, P8, W7, P9, W9, R10, W6, V7, V6, U8, V9, T7, U7, R7, U6, W5, U5, W4, P7, V5, V4, W3, U4, R5 M6, P3, N4, N5, R3, M7, T2, N6, U2, N7, P11, V13, U12, P12, T13, W13, U13, V10, W8, T11, U11, V12, V8, T1, P1, V1, U1, N1, R2, V3, U3, W2 L1, P2, M2, V2, M1, N2, T3, R1 H6 B1 D10, D14, D16, D4, D6, E12, E8, F4, F6, F10, F14, F16, G9, G11, H5, H8, H10, H12, H15, J9, J11, K4, K6, K8, K10, K12, K14, K16, L9, L11, M5, M8, M10, M12, M15, N9, N11, P4, P6, P10, P14, P16, R8, R12, T4, T6, T10, T14, T16 B6 C11 1 Pin Number Active Low Low Low Low -- Low Low Low Low High High High Low Low -- I/O Output Output Output Input Output I/O Input Input Input I/O I/O I/O Input I/O -- HRESET INT L1_TSTCLK Low Low High High -- Low Low Low High Input Input Input Output -- Output Output Output I/O F8 L17, L18, L19, M19, K18, K17, K15, J19, J18, J17, J16, H18, H17, J14, J13, H19, G18 L13 P17 N15 L16 U14, R13, W14, W15, V15, U15, W16, V16, W17, V17, U17, W18, V18, U18, V19, U19, T18, T17, R19, R18, R17, R15, P19, P18, P13, N14, N13, N19, N17, M17, M13, M18, H13, G19, G16, G15, G14, G13, F19, F18, F13, E19, E18, E17, E15, D19, D18, D17, C18, C17, B19, B18, B17, A18, A17, A16, B16, C16, A14, A15, C15, B14, C14, E13 V14, U16, T19, N18, H14, F17, C19, B15 D15, E14, E16, H16, J15, L15, M16, P15, R14, R16, T15, F15 L14 M14 F7 L2ADDR[0-16] L2AVDD L2CE L2CLKOUTA L2CLKOUTB L2DATA[0-63] L2DP[0-7] L2OVDD L2SYNC_IN L2SYNC_OUT L2_TSTCLK1 High -- -- -- High I/O -- Input Output Input MPC750A RISC Microprocessor Hardware Specifications 27 Pinout Listings Table 16. Pinout Listing for the MPC750, 360 CBGA Package (Continued) Signal Name L2WE L2ZZ LSSD_MODE1 MCP NC (No-Connect) OVDD PLL_CFG[0-3] QACK QREQ RSRV SMI SRESET SYSCLK TA TBEN TBST TCK TDI TDO TEA TLBISYNC TMS TRST TS TSIZ[0-2] TT[0-4] WT VDD 2 Pin Number N16 G17 F9 B11 B3, B4, B5, A19, W19, W1, K9, K114, K194 Active Low High Low Low -- -- High Low Low Low Low Low -- Low High Low High High High Low Low High Low Low High High Low -- High I/O Output Output Input Input -- -- Input Input Output Output Input Input Input Input Input I/O Input Input Output Input Input Input Input I/O Output I/O Output -- Output D5, D8, D12, E4, E6, E9, E11, F5, H4, J5, L5, M4, P5, R4, R6, R9, R11, T5, T8, T12 A4, A5, A6, A7 B2 J3 D3 A12 E10 H9 F1 A2 A11 B10 B7 D9 J1 A3 C8 A10 K7 A9, B9, C9 C10, D11, B12, C12, F11 C3 G8, G10, G12, J8, J10, J12, L8, L10, L12, N8, N10, N12 K13 VOLTDET 3 Notes: 1. These are test signals for factory use only and must be pulled up to OVdd for normal machine operation. 2. OVdd inputs supply power to the I/O drivers and Vdd inputs supply power to the processor core. 3. Internally tied to L2OVDD in the MPC750 CBGA package to indicate the power present at the L2 cache interface. This signal is not a power supply input. Caution: This is different from the MPC740 CBGA package. 4. These pins are reserved for potential future use as additional L2 address pins. 28 MPC750A RISC Microprocessor Hardware Specifications Package Description 1.7 Package Description The following sections provide the package parameters and mechanical dimensions for the MPC740, 255 CBGA packages. 1.7.1 Parameters for the MPC740 The package parameters are as provided in the following list. The package type is 21 x 21 mm, 255-lead ceramic ball grid array (CBGA). Package outline Interconnects Pitch Minimum module height Maximum module height Ball diameter 21 x 21 mm 255 (16 x 16 ball array - 1) 1.27 mm (50 mil) 2.45 mm 3.00 mm 0.89 mm (35 mil) 1.7.2 Mechanical Dimensions of the MPC740 Figure 16 provides the mechanical dimensions and bottom surface nomenclature of the MPC740, 255 CBGA package. MPC750A RISC Microprocessor Hardware Specifications 29 Package Description 2X 0.2 A1 CORNER D A C 0.15 C E E1 Notes: 2X Dimensioning and tolerancing per ASME Y14.5M, 1994. 0.2 B D1 Dimensions in millimeters. Top side A1 corner index is a metalized feature with various shapes. bottom side A1 corner is designated with a ball M 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 T R P N M L K J H G F E D C B A Millimeters DIM A A1 A2 b D D1 e E E1 M Min Max 2.45 3.00 0.79 0.99 0.9 1.10 0.82 0.93 21.00 BSC 8.3 8.5 1.27 BSC 21.00 BSC 9.0 9.2 2.00 e/2 A2 A1 A e 255X e/2 b 0.3 C A B 0.15 C Figure 16. Mechanical Dimensions and Bottom Surface Nomenclature of the MPC740 1.7.3 Parameters for the MPC750 The package parameters are as provided in the following list. The package type is 25 x 25 mm, 360-lead ceramic ball grid array (CBGA). Package outline Interconnects Pitch Minimum module height Maximum module height Ball diameter 25 x 25 mm 360 (19 x 19 ball array - 1) 1.27 mm (50 mil) 2.65 mm 3.20 mm 0.89 mm (35 mil) 30 MPC750A RISC Microprocessor Hardware Specifications System Design Information 1.7.4 Mechanical Dimensions of the MPC750 Figure 17 provides the mechanical dimensions and bottom surface nomenclature of the MPC750, 360 CBGA package. PIN A1 INDEX 2X 0.2 B A 360X D 1 0.15 A 0.25 A E2 E4 E 0.35 A 2X 0.2 NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION b IS THE MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. D2 AND E2 DEFINE THE AREA OCCUPIED BY THE DIE AND UNDERFILL. ACTUAL SIZE OF THIS AREA MAY BE SMALLER THAN SHOWN. D3 AND E3 ARE THE MINIMUM CLEARANCE FROM THE PACKAGE EDGE TO THE CHIP CAPACITORS. 5. CAPACITORS MAY NOT BE PRESENT ON ALL DEVICES. 6. CAUTION MUST BE TAKEN NOT TO SHORT EXPOSED METAL CAPACITOR PADS ON PACKAGE TOP. 2X D3 D4 D2 TOP VIEW D1 18X 2X E3 C DIM A A1 A2 A3 A4 b D D1 D2 D3 D4 e E E1 E2 E3 E4 MILLIMETERS MIN MAX 2.72 3.20 0.80 1.00 1.10 1.30 --0.60 0.82 0.90 0.82 0.93 25.00 BSC 22.86 BSC --- 12.50 2.75 --6.00 9.00 1.27 BSC 25.00 BSC 22.86 BSC --- 14.30 3.00 --8.00 11.00 e 18X C L W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10111213141516171819 e A3 A4 C L E1 A SIDE VIEW A2 A1 360X b 0.3 A B C 0.15 A BOTTOM VIEW Figure 17. Mechanical Dimensions and Bottom Surface Nomenclature of the MPC750 1.8 System Design Information This section provides electrical and thermal design recommendations for successful application of the MPC750. MPC750A RISC Microprocessor Hardware Specifications 31 System Design Information 1.8.1 PLL Configuration The MPC750's PLL is configured by the PLL_CFG[0-3] signals. For a given SYSCLK (bus) frequency, the PLL configuration signals set the internal CPU and VCO frequency of operation. The PLL configuration for the MPC750 is shown in Table 17 for nominal frequencies. Table 17. MPC750 Microprocessor PLL Configuration Sample Bus-to-Core Frequency in MHz (VCO Frequency in MHz) PLL_CFG [0-3] Bus-toCore Multiplier 3x 3.5x 4x 4.5x 5x 5.5x 6x 6.5x 7x 7.5x Core-to VCO Multiplier 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 150 (300) 166 (333) 183 (366) 150 (300) 200 (400) 162 (325) 216 (433) 175 (350) 233 (466) 187 (375) 1100 8x 2x 200 (400) 0011 1111 PLL off/bypass PLL off 250 (500) 266 (533) Bus 25 MHz Bus 33.3 MHz Bus 40 MHz Bus 50 MHz Bus 66.6 MHz Bus 75 MHz Bus 83.3 MHz 1000 1110 1010 0111 1011 1001 1101 0101 0010 0001 150 (300) 200 (400) 175 (350) 233 (466) 160 (320) 200 (400) 266 (533) 180 (360) 225 (450) 200 (400) 250 (500) 220 (440) 240 (480) 260 (520) 225 (450) 250 (500) 262 (525) PLL off, SYSCLK clocks core circuitry directly, 1x bus-to-core implied PLL off, no core clocking occurs Notes: 1. PLL_CFG[0-3] settings not listed are reserved. 2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO frequencies which are not useful, not supported, or not tested for by the MPC750; see Section 1.4.2.1, "Clock AC Specifications," for valid SYSCLK and VCO frequencies. 3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set for 1:1 mode operation. This mode is intended for factory use only. Note: The AC timing specifications given in this document do not apply in PLL-bypass mode. 4. In clock-off mode, no clocking occurs inside the MPC750 regardless of the SYSCLK input. 32 MPC750A RISC Microprocessor Hardware Specifications System Design Information Table 18 provides sample core-to-L2 frequencies. Table 18. Sample Core-to-L2 Frequencies Core Frequency in MHz 200 208.3 210 220 225 233.3 240 266 200 208 210 220 225 233.3 240 266 /1 /1.5 133.3 138.6 140 146.6 150 155.5 160 177.3 100 104 105 110 112.5 116.6 120 133 /2 80 83.3 84 88 90 93.3 96 106.4 /2.5 -- -- -- -- -- -- 80 88.6 /3 Note: The core and L2 frequencies are for reference only. Some configurations may select core or L2 frequencies which are not useful, not supported, or not tested for by the MPC750; see Section 1.4.2.4, "L2 Clock AC Specifications," for valid L2CLK frequencies. The L2CR[L2SL] bit should be set for L2CLK frequencies less than 110 MHz. 1.8.2 PLL Power Supply Filtering The AVdd and L2AVdd power signals are provided on the MPC750 to provide power to the clock generation phase-locked loop and L2 cache delay-locked loop respectively. To ensure stability of the internal clock, the power supplied to the AVdd input signal should be filtered using a circuit similar to the one shown in Figure 18. The circuit should be placed as close as possible to the AVdd pin to ensure it filters out as much noise as possible. An identical but separate circuit should be placed as close as possible to the L2AVdd pin. 10 Vdd 10 F 0.1 F AVdd (or L2AVdd) GND Figure 18. PLL Power Supply Filter Circuit 1.8.3 Decoupling Recommendations Due to the MPC750's dynamic power management feature, large address and data buses, and high operating frequencies, the MPC750 can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the MPC750 system, and the MPC750 itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each Vdd and OVdd pin (and L2OVdd for the 360 CBGA) of the MPC750. It is also recommended that these decoupling capacitors receive their power from separate Vdd, OVdd, and GND power planes in the PCB, utilizing short traces to minimize inductance. MPC750A RISC Microprocessor Hardware Specifications 33 System Design Information These capacitors should vary in value from 220 pF to 10 F to provide both high- and low-frequency filtering, and should be placed as close as possible to their associated Vdd or OVdd pins. Suggested values for the Vdd pins--220 pF (ceramic), 0.01 F (ceramic), and 0.1 F (ceramic). Suggested values for the OVdd pins--0.01 F (ceramic), 0.1 F (ceramic), and 10 F (tantalum). Only SMT (surface mount technology) capacitors should be used to minimize lead inductance. In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the Vdd and OVdd planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors--100 F (AVX TPS tantalum) or 330 F (AVX TPS tantalum). 1.8.4 Connection Recommendations To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to Vdd. Unused active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external Vdd, OVdd, and GND pins of the MPC750. External clock routing should ensure that the rising-edge of the L2 clock is coincident at the CLK input of all SRAMs and at the L2SYNC_IN input of the MPC750. The L2CLKOUTA network could be used only, or the L2CLKOUTB network could also be used depending on the loading, frequency, and number of SRAMs. 1.8.5 Output Buffer DC Impedance The MPC750 60x and L2 I/O drivers were characterized over process, voltage, and temperature. To measure Z0, an external resistor is connected to the chip pad, either to OVdd or OGND. Then, the value of such resistor is varied until the pad voltage is OVdd/2; see Figure 19. The output impedance is actually the average of two components, the resistances of the pull-up and pull-down devices. When Data is held low, SW1 is closed (SW2 is open), and R N is trimmed until Pad = OVdd/2. RN then becomes the resistance of the pull-down devices. When Data is held high, SW2 is closed (SW1 is open), and RP is trimmed until Pad = OVdd/2. RP then becomes the resistance of the pull-up devices. With a properly designed driver RP and RN are close to each other in value. Then Z0 = (RP + RN)/2. 34 MPC750A RISC Microprocessor Hardware Specifications System Design Information OVdd RP SW2 Pad Data SW1 RN OGND Figure 19. Driver Impedance Measurement Table 19 summarizes the signal impedance results. The driver impedance values were derived by simulation at 65 C. As the process varies, the output impedance will be reduced by several ohms. Table 19. Impedance Characteristics Vdd = 2.6V, OVdd = 3.3V, Tj = 65 C Process TYP 60x 43 L2 38 Symbol Z0 Unit Ohms MPC750A RISC Microprocessor Hardware Specifications 35 System Design Information 1.8.6 Pull-up Resistor Requirements The MPC750 requires high-resistive (weak: 10 K) pull-up resistors on several control signals of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the MPC750 or other bus masters. These signals are TS, ABB, DBB, and ARTRY. In addition, the MPC750 has one open-drain style output that requires a pull-up resistors (weak or stronger: 4.7 K-10 K) if it is used by the system. This signal is CKSTP_OUT. During inactive periods on the bus, the address and transfer attributes on the bus are not driven by any master and may float in the high-impedance state for relatively long periods of time. Since the MPC750 must continually monitor these signals for snooping, this float condition may cause excessive power draw by the input receivers on the MPC750 or by other receivers in the system. It is recommended that these signals be pulled up through weak (10 K) pull-up resistors or restored in some manner by the system. The snooped address and transfer attribute inputs are A[0-31], AP[0-3], TT[0-4], TBST, and GBL. The data bus input receivers are normally turned off when no read operation is in progress and do not require pull-up resistors on the data bus. Other data bus receivers in the system, however, may require pullups, or that those signals be otherwise driven by the system during inactive periods. The data bus signals are DH[0-31], DL[0-31], DP[0-7]. If address or data parity is not used by the system, and the respective parity checking is disabled through HID0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and should be left unconnected by the system. If all parity generation is disabled through HID0, then all parity checking should also be disabled through HID0, and all parity pins may be left unconnected by the system. No pull-up resistors are normally required for the L2 interface. 1.8.7 Thermal Management Information This section provides thermal management information for the ceramic ball grid array (CBGA) package for air-cooled applications. Proper thermal control design is primarily dependent upon the system-level design--the heat sink, airflow and thermal interface material. To reduce the die-junction temperature, heat sinks may be attached to the package by several methods--adhesive, spring clip to holes in the printed-circuit board or package, and mounting clip and screw assembly; see Figure 20. This spring force should not exceed 5.5 pounds of force. 36 MPC750A RISC Microprocessor Hardware Specifications System Design Information CBGA Package Heat Sink Heat Sink Clip Adhesive or Thermal Interface Material Printed-Circuit Board Option Figure 20. Package Exploded Cross-Sectional View with Several Heat Sink Options The board designer can choose between several types of heat sinks to place on the MPC750. There are several commercially-available heat sinks for the MPC750 provided by the following vendors: Chip Coolers Inc. 333 Strawberry Field Rd. Warwick, RI 02887-6979 International Electronic Research Corporation (IERC) 135 W. Magnolia Blvd. Burbank, CA 91502 Thermalloy 2021 W. Valley View Lane P.O. Box 810839 Dallas, TX 75731 Wakefield Engineering 60 Audubon Rd. Wakefield, MA 01880 Aavid Engineering One Kool Path Laconia, NH 03247-0440 800-227-0254 (USA/Canada) 401-739-7600 818-842-7277 214-243-4321 617-245-5900 603-528-3400 Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. MPC750A RISC Microprocessor Hardware Specifications 37 System Design Information 1.8.7.1 Internal Package Conduction Resistance For the exposed-die packaging technology, shown in Table 4, the intrinsic conduction thermal resistance paths are as follows: * * The die junction-to-case (or top-of-die for exposed silicon) thermal resistance The die junction-to-ball thermal resistance Figure 21 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. External Resistance Radiation Convection Heat Sink Thermal Interface Material Internal Resistance Die/Package Die Junction Package/Leads Printed-Circuit Board External Resistance Radiation Convection (Note the internal versus external package resistance) Figure 21. C4 Package with Heat Sink Mounted to a Printed-Circuit Board Heat generated on the active side of the chip is conducted through the silicon, then through the heat sink attach material (or thermal interface material), and finally to the heat sink where it is removed by forced-air convection. Since the silicon thermal resistance is quite small, for a first-order analysis, the temperature drop in the silicon may be neglected. Thus, the heat sink attach material and the heat sink conduction/convective thermal resistances are the dominant terms. 1.8.7.2 Adhesives and Thermal Interface Materials A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance. For those applications where the heat sink is attached by spring clip mechanism, Figure 22 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. As shown, the performance of these thermal interface materials improves with increasing contact pressure. The use of thermal grease significantly reduces the interface thermal resistance. That is, the bare joint results in a thermal resistance approximately 7 times greater than the thermal grease joint. Heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see Figure 20). This spring force should not exceed 5.5 pounds of force. Therefore, the synthetic grease offers the best thermal performance, considering the low interface pressure. Of course, the selection of any thermal interface material depends on many factors--thermal performance requirements, manufacturability, service temperature, dielectric properties, cost, etc. 38 MPC750A RISC Microprocessor Hardware Specifications System Design Information 2 Silicone Sheet (0.006 inch) Bare Joint Floroether Oil Sheet (0.007 inch) Graphite/Oil Sheet (0.005 inch) Synthetic Grease Specific Thermal Resistance (Kin2/W) 1.5 1 0.5 0 0 10 20 30 40 50 60 70 80 Contact Pressure (psi) Figure 22. Thermal Performance of Select Thermal Interface Material The board designer can choose between several types of thermal interface. Heat sink adhesive materials should be selected based upon high conductivity, yet adequate mechanical strength to meet equipment shock/vibration requirements. There are several commercially-available thermal interfaces and adhesive materials provided by the following vendors: Dow-Corning Corporation Dow-Corning Electronic Materials PO Box 0997 Midland, MI 48686-0997 Chomerics, Inc. 77 Dragon Court Woburn, MA 01888-4850 Thermagon Inc. 3256 West 25th Street Cleveland, OH 44109-1668 Loctite Corporation 1001 Trout Brook Crossing Rocky Hill, CT 06067 AI Technology (e.g. EG7655) 1425 Lower Ferry Rd. Trent, NJ 08618 517-496-4000 617-935-4850 216-741-7659 860-571-5100 609-882-2332 MPC750A RISC Microprocessor Hardware Specifications 39 System Design Information The following section provides a heat sink selection example using one of the commercially available heat sinks. 1.8.7.3 Heat Sink Selection Example For preliminary heat sink sizing, the die-junction temperature can be expressed as follows: Tj = Ta + Tr + (jc + int + sa) * Pd Where: Tj is the die-junction temperature Ta is the inlet cabinet ambient temperature Tr is the air temperature rise within the computer cabinet jc is the junction-to-case thermal resistance int is the adhesive or interface material thermal resistance sa is the heat sink base-to-ambient thermal resistance Pd is the power dissipated by the device During operation the die-junction temperatures (Tj) should be maintained less than the value specified in Table 3. The temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (Ta) may range from 30 to 40 C. The air temperature rise within a cabinet (Tr) may be in the range of 5 to 10 C. The thermal resistance of the thermal interface material (int) is typically about 1 C/W. Assuming a Ta of 30 C, a Tr of 5 C, a CQFP package jc = 2.2, and a power consumption (Pd) of 4.5 watts, the following expression for Tj is obtained: Die-junction temperature: Tj = 30 C + 5 C + (2.2 C/W + 1.0 C/W + sa) * 4.5 W For a Thermalloy heat sink #2328B, the heat sink-to-ambient thermal resistance (sa) versus airflow velocity is shown in Figure 23. 40 MPC750A RISC Microprocessor Hardware Specifications System Design Information 8 7 Heat Sink Thermal Resistance (C/W) Thermalloy #2328B Pin-fin Heat Sink (25 x28 x 15 mm) 6 5 4 3 2 1 0 0.5 1 1.5 2 2.5 3 3.5 Approach Air Velocity (m/s) Figure 23. Thermalloy #2328B Heat Sink-to-Ambient Thermal Resistance Versus Airflow Velocity Assuming an air velocity of 0.5 m/s, we have an effective Rsa of 7 C/W, thus Tj = 30 C + 5 C + (2.2 C/W +1.0 C/W + 7 C/W) * 4.5 W, resulting in a die-junction temperature of approximately 81 C which is well within the maximum operating temperature of the component. Other heat sinks offered by Chip Coolers, IERC, Thermalloy, Wakefield Engineering, and Aavid Engineering offer different heat sink-to-ambient thermal resistances, and may or may not need air flow. Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-of-merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. The final die-junction operating temperature, is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. In addition to the component's power consumption, a number of factors affect the final operating die-junction temperature--airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, etc. Due to the complexity and the many variations of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models for the board, as well as, system-level designs. To expedite system-level thermal analysis, several "compact" thermal-package models are available within FLOTHERM(R). These are available upon request. MPC750A RISC Microprocessor Hardware Specifications 41 Document Revision History 1.9 Document Revision History Table 20. Document Revision History Document Revision Rev 1 Substantive Change(s) Modified introduction to indicate this document also addresses MPC750P parts fabricated in .19 process with attendant changes in supply voltages and electrical characteristics. Changed Section 1.3, "General Parameters," to include new Technology, Die size, and Core power supply for MPC750P. Changed Table 2 to include absolute maximum supply voltage for MPC750P. Changed Table 3 to include recommended supply voltages for MPC750P and extended L2 bus supply voltage down to 2.5V for all parts. Added Table 7 to provide power consumption of MPC750P. Changed Table 8, Table 9, and Table 10 to show test conditions appropriate to the process and add 300 MHz to AC specifications. Changed Table 9 to reduce input hold time (spec 11a and 11b) from 1ns to 0ns for all CPU frequencies. Changed Table 11, Table 12 and Table 13 to show extended test conditions for L2OVdd and add 300MHz to AC specifications. Changed Table 13 and Table 14 to show test conditions appropriate to the process. Rev 2 Removed Preliminary overlay from document Deleted electrical specifications for the MPC750P part and created a separate specification describing the unique operating conditions of that part. Corrected Active polarity of CKSTP_OUT, CKSTP_IN, L2CE, L2WE, L2SYNC_IN, L2SYNC_OUT in Table 17. Added extended junction temperature parts to Table 3. Rev 2.1 Rev 2.2 Rev 2.3 Removed 333MHz column from Table 13. In Table 7, Maximum sleep power is increased to 300 mW. Corrected Figure 16 and Figure 17, which omitted some dimensions due to format error. 1.10 Ordering Information This section provides the part numbering nomenclature for the MPC750. Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Motorola sales office. Figure 24 provides the Motorola part numbering nomenclature for the MPC750. In addition to the processor frequency, the part numbering scheme also consists of a part modifier and application modifier. The part modifier indicates any enhancement(s) in the part from the original production design. The bus divider may specify special bus frequencies or application conditions. Each part number also contains a 42 MPC750A RISC Microprocessor Hardware Specifications Ordering Information revision code. This refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. MPC 750 A RX XXX X X Product Code Part Identifier (740 or 750) Part Modifier Revision Level (Contact Local Motorola Sales Office) Application Modifier (L = Any Valid PLL Configuration T=Extended Temperature) Processor Frequency Package (RX = BGA) Figure 24. Motorola Part Number Key MPC750A RISC Microprocessor Hardware Specifications 43 DigitalDNA is a trademark of Motorola, Inc. The PowerPC name, the PowerPC logotype, and PowerPC 603e are trademarks of International Business Machines Corporation used by Motorola under license from International Business Machines Corporation. Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors. There are no express or implied copyright licenses granted hereunder to design or fabricate PowerPC integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852-26668334 TECHNICAL INFORMATION CENTER: 1-800-521-6274 HOME PAGE: http://www.motorola.com/semiconductors DOCUMENT COMMENTS: FAX (512) 933-2625, Attn: RISC Applications Engineering WORLD WIDE WEB ADDRESSES: http://www.motorola.com/PowerPC http://www.motorola.com/NetComm MPC750EC/D |
Price & Availability of MPC750ED
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |