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Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope suitable for surface mounting. Using 'trench' technology the device features very low on-state resistance. It is intended for use in automotive and general purpose switching applications.
BUK9635-100A
QUICK REFERENCE DATA
SYMBOL VDS ID Ptot Tj RDS(ON) PARAMETER Drain-source voltage Drain current (DC) Total power dissipation Junction temperature Drain-source on-state resistance VGS = 5 V VGS = 10 V MAX. 100 40 150 175 35 34 UNIT V A W C m m
PINNING - SOT404
PIN 1 2 3 mb gate drain (no connection possible) source drain DESCRIPTION
PIN CONFIGURATION
mb
SYMBOL
d
g
2 1 3
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDGR VGS VGSM ID ID IDM Ptot Tstg, Tj PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage Non Repetive gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage & operating temperature CONDITIONS RGS = 20 k Tmb = 25 C Tmb = 100 C Tmb = 25 C Tmb = 25 C MIN. - 55 MAX. 100 100 10 15 40 29 133 150 175 UNIT V V V V A A A W C
THERMAL RESISTANCES
SYMBOL Rth j-mb Rth j-a PARAMETER Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS Minimum footprint, FR4 board TYP. 50 MAX. 1.01 UNIT K/W K/W
August 1999
1
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
STATIC CHARACTERISTICS
Tj= 25C unless otherwise specified SYMBOL V(BR)DSS VGS(TO) IDSS IGSS RDS(ON) PARAMETER Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current Gate source leakage current Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55C VDS = VGS; ID = 1 mA Tj = 175C Tj = -55C VDS = 100 V; VGS = 0 V; VGS = 10 V; VDS = 0 V VGS = 5 V; ID = 25 A VGS = 10 V; ID = 25 A VGS = 4.5 V; ID = 25 A Tj = 175C Tj = 175C MIN. 100 89 1 0.5 -
BUK9635-100A
TYP. 1.5 0.05 2 26 24.1 26.1
MAX. 2 2.3 10 500 100 35 95 34 38
UNIT V V V V V A A nA m m m m
DYNAMIC CHARACTERISTICS
Tmb = 25C unless otherwise specified SYMBOL Ciss Coss Crss td on tr td off tf Ld Ls PARAMETER Input capacitance Output capacitance Feedback capacitance Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal source inductance CONDITIONS VGS = 0 V; VDS = 25 V; f = 1 MHz MIN. TYP. 2700 260 160 10 62 194 108 2.5 7.5 MAX. 3500 314 220 15 87 291 162 UNIT pF pF pF ns ns ns ns nH nH
VDD = 30 V; Rload =1.2; VGS = 10 V; RG = 10
Measured from upper edge of drain tab to centre of die Measured from source lead soldering point to source bond pad
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25C unless otherwise specified SYMBOL IDR IDRM VSD trr Qrr PARAMETER Continuous reverse drain current Pulsed reverse drain current Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS MIN. IF = 25 A; VGS = 0 V IF = 40 A; VGS = 0 V IF = 40 A; -dIF/dt = 100 A/s; VGS = -10 V; VR = 30 V TYP. 0.85 1.1 60 0.3 MAX. 40 133 1.2 UNIT A A V V ns C
AVALANCHE LIMITING VALUE
SYMBOL WDSS PARAMETER Drain-source non-repetitive unclamped inductive turn-off energy CONDITIONS ID = 40 A; VDD 25 V; VGS = 10 V; RGS = 50 ; Tmb = 25 C MIN. TYP. MAX. 125 UNIT mJ
August 1999
2
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
BUK9635-100A
120 110 100 90 80 70 60 50 40 30 20 10 0
PD%
Normalised Power Derating
10
Zth/(K/W)
D=
1
0.5 0.2
0.1
0.1 0.05 0.02
0.01
0
P D
tp
D=
tp T t
T
0
20
40
60
80 100 Tmb / C
120
140
160
180
0.001 1E-07
1E-05
1E-3 t/S
1E-01
1E+01
Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Tmb)
ID% Normalised Current Derating
150
ID/A
Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T
120 110 100 90 80 70 60 50 40 30 20 10 0
VGS/V= 10.0 5.0 4.0 3.8
100
3.6 3.4 3.2
50
3.0 2.8 2.6 2.4 2.2
0
20
40
60
80 100 Tmb / C
120
140
160
180
0
0
2
4
VDS/V
6
8
10
Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Tmb); conditions: VGS 5 V
1000
Fig.5. Typical output characteristics, Tj = 25 C. ID = f(VDS); parameter VGS
RDS(ON)/mOhm
40
ID/A RDS(ON)=VDS/ID
100
tp=
35
1uS 10uS
30
VGS/V= 3.0 3.2 3.4 3.6 4.0 5.0
100uS
10
DC
1mS 10mS 100mS
25
1
20
1
10
VDS/V
100
1000
0
10
20
30
ID/A
40
50
60
70
Fig.3. Safe operating area. Tmb = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(ID); parameter VGS
August 1999
3
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
BUK9635-100A
33 32 31 30 29 28 27 26 25
RDS(ON)/mOhm
3
a
Rds(on) normalised to 25degC
2.5
2
1.5
1
24 23 22
0.5
3 4 5 6
ID/A
7
8
9
10
-100
-50
0
50 100 Tmb / degC
150
200
Fig.7. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(VGS); conditions: ID = 25 A;
90 ID/A 80 70 60 50 40
Fig.10. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 C = f(Tj); ID = 25 A; VGS = 5 V
VGS(TO) / V max. 2 typ. 1.5 min. 1 BUK959-60
2.5
30 20 10 0 0.0 1.0 2.0 3.0 4.0 5.0
Tj/C=
175
25
0.5
0 -100
-50
0
VGS/V
50 Tj / C
100
150
200
Fig.8. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
70 gfs/S 60 50 40 30
Fig.11. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Sub-Threshold Conduction
1E-01
1E-02 2% typ 98%
1E-03
1E-04
20 10 0
1E-05
0
20
40
ID/A
60
80
100
1E-05
0
0.5
1
1.5
2
2.5
3
Fig.9. Typical transconductance, Tj = 25 C. gfs = f(ID); conditions: VDS = 25 V
Fig.12. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C; VDS = VGS
August 1999
4
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
BUK9635-100A
7 6 5
120 110 100 90 80 70 60 50
Ciss
WDSS%
Thousands pF
4 3 2 1 0 0.01
40 30 20 10
0.1
1 VDS/V
10
Coss Crss 100
0 20 40 60 80 100 120 Tmb / C 140 160 180
Fig.13. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
Fig.16. Normalised avalanche energy rating. WDSS% = f(Tmb); conditions: ID = 75 A
6 VGS / V 5 VDS = 14V 4 VDS = 44V 3 2
+
L VDS VGS 0 T.U.T. R 01 shunt
VDD
-ID/100
1 0 0 10 QG / nC 20 30 40
RGS
Fig.14. Typical turn-on gate-charge characteristics. VGS = f(QG); conditions: ID = 25 A; parameter VDS
100
Fig.17. Avalanche energy test circuit. 2 WDSS = 0.5 LID BVDSS /(BVDSS - VDD )
80
+
RD VDS
Tj/C= 175 25
VDD
60
VGS
40
RG T.U.T.
0
20
0 0.0
0.5
1.0
1.5
Fig.15. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
Fig.18. Switching test circuit.
August 1999
5
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
MECHANICAL DATA
Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads (one lead cropped)
BUK9635-100A
SOT404
A E A1 mounting base
D1
D
HD
2
Lp
1
3
b c Q
e
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 4.50 4.10 A1 1.40 1.27 b 0.85 0.60 c 0.64 0.46 D max. 11 D1 1.60 1.20 E 10.30 9.70 e 2.54 Lp 2.90 2.10 HD 15.40 14.80 Q 2.60 2.20
OUTLINE VERSION SOT404
REFERENCES IEC JEDEC EIAJ
EUROPEAN PROJECTION
ISSUE DATE 98-12-14 99-06-25
Fig.19. SOT404 surface mounting package. Centre pin connected to mounting base.
Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18. 3. Epoxy meets UL94 V0 at 1/8".
August 1999
6
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOSTM transistor Logic level FET
MOUNTING INSTRUCTIONS
Dimensions in mm
11.5
BUK9635-100A
9.0
17.5 2.0
3.8
5.08
Fig.20. SOT404 : soldering pattern for surface mounting.
DEFINITIONS
Data sheet status Objective specification Product specification Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
August 1999
7
Rev 1.000

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