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S6B0108
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
July. 2001 Ver. 0.0
Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team. Precautions for Light Light has characteristics to move electrons in the integrated circuitry of semiconductors, therefore may change the characteristics of semiconductor devices when irradiated with light. Consequently, the users of the packages which may expose chips to external light such as COB, COG, TCP and COF must consider effective methods to block out light from reaching the IC on all parts of the surface area, the top, bottom and the sides of the chip. Follow the precautions below when using the products. 1. Consider and verify the protection of penetrating light to the IC at substrate (board or glass) or product design stage. Always test and inspect products under the environment with no penetration of light.
2.
S6B0108
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
S6B0755 Specification Revision History Version 0.0 Original Content Date July.2001
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S6B0108
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
CONTENTS
INTRODUCTION ............................................................................................................................................. 1 BLOCK DIAGRAM .......................................................................................................................................... 2 PIN CONFIGURATION .................................................................................................................................... 3 100 QFP.................................................................................................................................................. 3 PAD DIAGRAM (CHIP LAYOUT FOR THE 100QFP).................................................................................... 4 PAD CENTER COORDINATES (100QFP).................................................................................................. 5 100TQFP (S6B2108)................................................................................................................................. 6 PAD DIAGRAM (CHIP LAYOUT FOR THE 100TQFP).................................................................................. 7 PAD CENTER COORDINATES (100TQFP- S6B2108).................................................................................. 8 PIN DESCRIPTION ........................................................................................................................................ 9 MAXIMUM ABSOLUTE LIMIT ......................................................................................................................11 ELECTRICAL CHARACTERISTICS ................................................................................................................12 DC CHARACTERISTICS ..........................................................................................................................12 AC CHARACTERISTICS (V DD = +5V 10%, VSS = 0V, Ta =-30 to +85C) ..................................................13 OPERATING PRINCIPLES AND METHODS ....................................................................................................17 I/O BUFFER ...........................................................................................................................................17 RESET...................................................................................................................................................18 DISPLAY CONTROL INSTRUCTION.............................................................................................................21 DISPLAY ON/OFF...................................................................................................................................22 STATUS READ.......................................................................................................................................23 APPLICATION CIRCUIT................................................................................................................................24 1/64 DUTY COMMON DRIVER (S6B0107) INTERFACE CIRCUIT ................................................................24 TIMING DIAGRAM (1/64 DUTY)................................................................................................................25 LCD PANEL INTERFACE APPLICATION CIRCUIT .....................................................................................26
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64CH SEGMENT DRIVER FOR DOT MATRIX LCD
S6B0108
INTRODUCTION
The S6B0108 (TQFP type: S6B2108) is a LCD driver LSI with 64 channel output for dot matrix liquid crystal graphic display systems. This device consists of the display RAM, 64 bit data latch, 64 bit drivers and decoder logic. It has the internal display RAM for storing the display data transferred from a 8 bit micro controller and generates the dot matrix Iiquid crystal driving signals corresponding to stored data. The S6B0108 composed of the liquid crystal display system in combination with the S6B0107 (64 channel common driver -TQFP type: S6B2107).
FEATURES
-- -- Dot matrix LCD segment driver with 64 channel output Input and output signal - Input: 8 bit parallel display data control signal from MPU divided bias voltage (V0R, V0L, V2R, V2L, V3R, V3L, V5R, V5L) - Output: 64 channel for LCD driving. Display data is stored in display data RAM from MPU. Interface RAM - Capacity: 512 bytes (4096 bits) - RAM bit data: RAM bit data = 1: On RAM bit data = 0: Off Applicable LCD duty: 1/32-1/64 LCD driving voltage: 8V-17V (V DD-VEE) Power supply voltage: + 5V 10% Interface Drivers Common S6B0107 -- -- Segment Other S6B0108 MPU Controller
-- --
-- -- -- --
High voltage CMOS process 100QFP/100TQFP or bare chip available.
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S6B0108
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
BLOCK DIAGRAM
CLK1 CLK2
DB<0:7>
8
8
Display On/Off
1
Busy
Instruction Decoder
6
Y-Counter
6 6
3
I/O Buffer
Input Register
Output Register
CS1B CS2B CS3 R/W RS E RSTB
ADC
Y-Counter
64
X-Decoder
8
CL
Display Start Line Register
6
64
Display Data RAM 512 x 8 = 4096 bits
8
FRM
64
Data Latch
64
V0L V2L V3L V5L M
Page Selector
Z-Decoder
LCD Driver
V0R V2R V3R V5R
S2
2
S64
S63
S1
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
S6B0108
PIN CONFIGURATION
100 QFP
100 99 98 97 96 95 94 93 92 91 90 86 85 84 83 82 81
FRM E CLK1 CLK2 CL RS R/W RSTB CS1B CS2B CS3 DB7 DB6 DB5 DB4 DB3 DB2
ADC M VDD V3R V2R V5R V0R VEE2 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
S6B0108
(100-QFP)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DB1 DB0 VSS V3L V2L V5L V0L VEE1 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22
S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
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S6B0108
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
PAD DIAGRAM (CHIP LAYOUT FOR THE 100QFP)
V3R V2R V5R V0R VEE2 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
3 2 1 100 99 98 97 96 95 94 93 92 91 90 86 85 84 83 82 81 80 79 78
VDD M ADC FRM E CLK1 CLK2 CL RS R/W RSTB CS1B CS2B CS3 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VSS
Y
(0, 0)
X
Chip size: 4090 x 4020 PAD size: 100 x 100 Unit : m
S6B0108
77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
V3L V2L V5L V0L VEE1 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21
There is mark of S6B0108 on the bottom left in the chip.
4
S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22
30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
S6B0108
PAD CENTER COORDINATES (100QFP)
PAD Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 PAD Name ADC M VDD V3R V2R V5R V0R VEE2 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 Coordinate X -1140 -1275 -1410 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1882 -1487 -1187 -1062 -937 -812 Y 1845 1845 1845 1809 1684 1559 1434 1309 1165 1040 915 790 665 540 415 290 165 40 -84 -209 -334 -459 -584 -709 -834 -959 -1099 -1239 -1379 -1845 -1845 -1845 -1845 -1845 PAD Number 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 PAD Name S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 Coordinate X -687 -562 -437 -312 -187 -62 62 187 312 437 562 687 812 937 1062 1187 1487 1882 1882 1882 1882 1882 1882 1882 1882 1882 1882 1882 1882 1882 1882 1882 1882 1882 Y -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1845 -1379 -1239 -1099 -959 -834 -709 -584 -459 -334 -209 -84 41 166 291 416 541 666 PAD Number 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 90 91 92 93 94 95 96 97 98 99 100 PAD Name S4 S3 S2 S1 VEE1 V0L V5L V2L V3L VSS DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 CS3 CS2B CS1B RSTB R/W RS CL CLK2 CLK1 E FRM Coordinate X 1882 1882 1882 1882 1882 1882 1882 1882 1882 1412 1277 1142 1007 882 757 632 507 382 245 120 -5 -130 -255 -380 -505 -630 -755 -880 -1005 Y 791 916 1041 1166 1310 1435 1559 1684 1809 1845 1845 1845 1845 1845 1845 1845 1845 1845 1845 1845 1845 1845 1845 1845 1845 1845 1845 1845 1845
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S6B0108
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
100TQFP (S6B2108)
VDD V3R V2R V5R V0R VEE2 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
M ADC FRM E CLK1 CLK2 CL RS R/W RSTB NC CS1B NC CS2B CS3 NC DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VSS
S6B2108
(100-TQFP)
V3L V2L V5L V0L VEE1 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20
6
S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
S6B0108
PAD DIAGRAM (CHIP LAYOUT FOR THE 100TQFP)
M ADC FRM E CLK1 CLK2 CL RS R/W RSTB
CS1B
CS2B CS3 87 86
100 99 98 97 96 95 94 93 92 91
89
VDD V3R V2R V5R V0R VEE2 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
84 83 82 81 80 79 78 77 76
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VSS
Y
(0, 0)
X
Chip size: 4180 x 4030 PAD size: 100 x 100 Unit : m S6B0108BTQ
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
V3L V2L V5L V0L VEE1 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20
There is mark of S6B2108 on the bottom left in the chip.
S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
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S6B0108
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
PAD CENTER COORDINATES (100TQFP- S6B2108)
PAD Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 PAD Name VDD V3 V2 V5 V0 VEE S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 Coordinate X -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1924 -1573.1 -1445.9 -1318.7 -1191.5 -1064.3 -937.1 -809.9 -682.7 -555.5 -428.3 Y 1812.5 1687.5 1562.5 1437.5 1312.5 1187.5 1033.2 906 778.8 651.6 524.4 397.2 270 142.8 15.6 -111.6 -238.8 -366 -493.2 -620.4 -747.6 -874.8 -1002 -1129.2 -1256.4 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 PAD Number 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 PAD Name S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 Coordinate X -301.1 -173.9 -46.7 80.5 207.7 334.9 462.1 589.3 716.5 843.7 970.9 1098.1 1225.3 1352.5 1479.7 1924 1924 1924 1924 1924 1924 1924 1924 1924 1924 1924 1924 1924 1924 1924 1924 1924 1924 1924 1924 Y -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1849 -1245.3 -1118.1 -990.9 -863.7 -736.5 -609.3 -482.1 -354.9 -227.7 -100.5 26.7 153.9 281.1 408.3 535.5 662.7 789.9 917.1 1044.3 1171.5 PAD Number 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 RSTB RW RS CL CLK2 CLK1 E FRW ADC M CS1B CS3 CS2B PAD Name VEE V0 V5 V2 V3 VSS DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 Coordinate X 1924 1924 1924 1924 1924 1450.5 1315.5 1180.5 1045.5 920.5 795.5 670.5 545.5 420.5 NC 282.8 157.8 NC 32.8 NC -92.2 -217.2 -342.2 467.2 -592.2 -717.2 -842.2 -967.2 -1177.8 -1312.8 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 1849 Y 1312.5 1437.5 1562.5 1687.5 1812.5 1849 1849 1849 1849 1849 1849 1849 1849 1849
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64CH SEGMENT DRIVER FOR DOT MATRIX LCD
S6B0108
PIN DESCRIPTION
Table 1. Pin Description Pin Number QFP(TQFP) 3(1) 78(76) 73(71), 8(6) Symbol VDD VSS VEE1.2 Power Input/Output Description For internal logic circuit (+5V 10%) GND (0V) For LCD driver circuit VSS = 0V, VDD = +5V 10%, VDD-VEE = 8V - 17V VEE1 and VEE2 is connected by the same voltage. 74(72), 7(5) 76(74), 5(3) 77(75), 4(2) 75(73), 6(4) V0L, V2L, V3L, V5L, V0R V2R V3R V5R Bias supply voltage terminals to drive the LCD. Power
Select Level V0L(R), V5L(R) Non-Select Level V2L(R), V3L(R)
V0L and V0R (V2L & V2R, V3L & V3R, V5L & V5R) should be connected by the same voltage. 92(89) 91(87) 90(86) 2(100) 1(99) CS1B CS2B CS3 M ADC Input Chip selection In order to interface data for input or output, the terminals have to be CS1B = L, CS2B = L, and CS3 = H. Alternating signal input for LCD driving. Address control signal to determine the relation between Y address of display RAM and terminals from which the data is output. ADC = H Y0: S1 - Y63: S64 ADC = L Y0: S64 - Y63: S1 Synchronous control signal. Presets the 6-bit Z counter and synchronizes the common signal with the frame signal when the frame signal becomes high. Enable signal. Write mode (R/W = L) data of DB<0:7> is latched at the falling edge of E. Read mode (R/W = H) DB<0:7> appears the reading data while E is at high level. 2 phase clock signal for internal operation. Used to execute operations for input/output of display RAM data and others. Display synchronous signal. Display data is latched at rising time of the CL signal and increments the Z-address counter at the CL falling time. Data or Instruction. RS = H DB<0:7>: Display RAM data RS = L DB<0:7>: Instruction data
Input Input
100(98)
FRM
Input
99(97)
E
Input
98(96) 97(95) 96(94)
CLK1 CLK2 CL
Input
Input
95(93)
RS
Input
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S6B0108
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
Table 1. Pin Description (Continued) Pin Number QFP(TQFP) 94(92) Symbol R/W Input/Output Input Description Read or Write. R/W = H Data appears at DB<0:7> and can be read by the CPU while E = H, CS1B = L, CS2B = L and CS3 = H . R/W = L Display data DB<0:7> can be written at falling of E when CS1B = L, CS2B = L and CS3 = H. 79-86 (77-84) 72-9 (70-7) DB0-DB7 S1-S64 Input/Output Output Data bus. There state I/O common terminal. LCD segment driver output. Display RAM data 1: On Display RAM data 0: Off (relation of display RAM data & M)
M L H Data L H L H Output Level V2 V0 V3 V5
93(91)
RSTB
Input
Reset signal. When RSTB=L, - ON/OFF register becomes set by 0. (display off) - Display start line register becomes set by 0 (Z-address 0 set, display from line 0) After releasing reset, this condition can be changed only by instruction.
87(85), 88(88) 89(90)
NC
No connection. (open)
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64CH SEGMENT DRIVER FOR DOT MATRIX LCD
S6B0108
MAXIMUM ABSOLUTE LIMIT
Characteristic Operating voltage Supply voltage Driver supply voltage Symbol VDD VEE VB VLCD Operating temperature Storage temperature
NOTES: 1. Based on VSS = 0V. 2. 3. 4. Applies the same supply voltage to VEE1 and VEE2. VLCD=VDD-VEE. Applies to M, FRM, CL, RSTB, ADC, CLK1, CLK2, CS1B, CS2B, CS3, E, R/W, RS and DB0 - DB7. Applies to V0L(R), V2L(R), V3L(R) and V5L(R). Voltage level: VDD V0L = V0R V2L = V2R V3L = V3R V5L = V5R VEE.
Value -0.3 to +7.0 VDD-19.0 to VDD+0.3 -0.3 to VDD+0.3 VEE-0.3 to VDD+0.3 -30 to +85 -55 to +125
Unit V V V V C C
Note
(1) (4) (1), (3) (2)
TOPR TSTG
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S6B0108
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (V DD = +5V 10%, VSS = 0V, VDD-VEE = 8 to 17V, Ta =-30 to +85C) Characteristic Input high voltage Symbol VIH1 VIH2 Input low voltage VIL1 VIL2 Output high voltage Output low voltage Input leakage current Three-state(off) input current Driver input leakage current Operating current VOH VOL ILKG ITSL IDIL IDD1 IDD2 On resistance RON Condition - - - - IOH = -200A IOL = 1.6mA VIN = VSS - VDD VIN = VSS - VDD VIN = VEE - VDD During display During access Access cycle = 1MHz VDD-VEE = 15V ILOAD = 0.1mA
NOTES: 1. CL, FRM, M, RSTB, CLK1, CLK2 2. CS1B, CS2B, CS3, E, R/W, RS, DB0 - DB7 3. DB0 - DB7 4. Except DB0 - DB7 5. DB0 - DB7 at high impedance 6. V0L(R), V2L(R), V3L(R), V5L(R) 7. 1/64 duty, FCLK = 250kHz, frame frequency = 70HZ, output: no load 8. VDD - VEE = 15.5V V0L(R) > V2L(R) = VDD - 2/7 (VDD-VEE) > V3L(R) = VEE + 2/7 (VDD-VEE) > V5L(R)
Min 0.7V DD 2.0 0 0 2.4 - -1.0 -5.0 -2.0 - - -
Typ - - - - - - - - - - - -
Max VDD VDD 0.3V DD 0.8 - 0.4 1.0 5.0 2.0 100 500 7.5
Unit V V V V V V A A A A A K
Note
(1) (2) (1) (2) (3) (3) (4) (5)
(6)
(7) (7)
(8)
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64CH SEGMENT DRIVER FOR DOT MATRIX LCD
S6B0108
AC CHARACTERISTICS (V DD = +5V 10%, VSS = 0V, Ta =-30 to +85C) Clock Timing Characteristic CLK1, CLK2 cycle time CLK1 "low" level width CLK2 "low" level width CLK1 "high" level width CLK2 "high" level width CLK1-CLK2 phase difference CLK2-CLK1 phase difference CLK1, CLK2 rise time CLK1, CLK2 fall time Symbol tCY tWL1 tWL2 tWH1 tWH2 tD12 tD21 tR tF Min 2.5 625 625 1875 1875 625 625 - - Typ - - - - - - - - - Max 20 - - - - - - 150 150 Unit s ns
tC Y tW H 1 tF CLK1 0.7VD D 0.3VD D tWL1 CLK2 tR
tD12 0.7VD D 0.3VD D tF
tD21
tW L 2
tW H 2 tR tC Y
Figure 1. External Clock Waveform
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S6B0108
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
Display Control Timing Characteristic FRM delay time M delay time CL "low" level width CL "high" level width Symbol tDF tDM tWL tWH Min -2 -2 35 35 Typ - - - - Max +2 +2 - - Unit us us us us
tW L 0.7VD D 0.3VD D tD F 0.7VD D 0.3VD D tD M 0.7VD D 0.3VD D tD F tW H
Figure 2. Display Control Waveform
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64CH SEGMENT DRIVER FOR DOT MATRIX LCD
S6B0108
MPU Interface Characteristic E cycle E high level width E low level width E rise time E fall time Address set-up time Address hold time Data set-up time Data delay time Data hold time (write) Data hold time (read) Symbol tC tWH tWL tR tF tASU tAH tDSU tD tDHW tDHR Min 1000 450 450 - - 140 10 200 - 10 20 Typ - - - - - - - - - - - Max - - - 25 25 - - - 320 - - Unit ns ns ns ns ns ns ns ns ns ns ns
tC E 2.0V 0.8V tW L tW H tR t ASU R/W t ASU CS1B, CS2B, CS3, RS 0.8V t DSU tD H W tAH 2.0V tF tAH
DB0 - 7
Figure 3. MPU Write Timing
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S6B0108
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
tC E tW L tR R/W t ASU t ASU CS1B, CS2B, CS3, RS tD DB0 - 7 tD H R tW H tF tAH tAH
Figure 4. MPU Read Timing
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64CH SEGMENT DRIVER FOR DOT MATRIX LCD
S6B0108
OPERATING PRINCIPLES AND METHODS
I/O BUFFER Input buffer controls the status between the enable and disable of chip. Unless the CS1B to CS3 is in active mode, Input or output of data and instruction does not execute. Therefore internal state is not change. But RSTB and ADC can operate regardless CS1B-CS3.
INPUT REGISTER Input register is provided to interface with MPU which is different operating frequency. Input register stores the data temporarily before writing it into display RAM. When CS1B to CS3 are in the active mode, R/W and RS select the input register. The data from MPU is written into input register. Then Writing it into display RAM. Data latched for falling of the E signal and write automatically into the display data RAM by internal operation.
OUTPUT REGISTER Output register stores the data temporarily from display data RAM when CS1B, CS2B and CS3 are in active mode and R/W and RS = H, stored data in display data RAM is latched in output register. When CS1B to CS3 is in active mode and R/W = H, RS = L, status data (busy check) can read out. To read the contents of display data RAM, twice access of read instruction is needed. In first access, data in display data RAM is latched into output register. In second access, MPU can read data which is latched. That is, to read the data in display data RAM, it needs dummy read. But status read is not needed dummy read. RS L R/W L H H L H Instruction Status read (busy check) Data write (from input register to display data RAM) Data read (from display data RAM to output register) Function
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S6B0108
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
RESET The system can be initialized by setting RSTB terminal at low level when turning power on, receiving instruction from MPU. When RSTB becomes low, following procedure is occurred. -- -- Display off Display start line register become set by 0. (Z-address 0)
While RSTB is low, No instruction except status read can be accepted. Therefore, execute other instructions after making sure that DB4 = 0 (clear RSTB) and DB7 = 0 (ready) by status read instruction. The Conditions of power supply at initial power up are shown in Table 2.
Table 2. Power Supply Initial Conditions Item Reset time Rise time Symbol tRS tR Min 1.0 - Typ - - Max - 200 Unit us ns
VDD
4.5V tR S tR 0.7VD D 0.3VD D
RSTB
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64CH SEGMENT DRIVER FOR DOT MATRIX LCD
S6B0108
Busy Flag Busy Flag indicates that S6B0108 is operating or no operating. When busy flag is high, S6B0108 is in internal operating. When busy flag is low, S6B0108 can accept the data or instruction. DB7 indicates busy flag of the S6B0108.
RS R/W E Address Output Register DB0-DB7
Busy check Write address N Busy check Read data (dummy)
N
N+1
N+2
Data at address N Data at address N+1
Busy check Read data Busy at address check N Data read address N + 1
Busy Check
E Busy Flag T Busy 1/f C L K < T Busy < 3/f C L K fC L K is CLK1, CLK2 frequency Busy Check
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S6B0108
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
Display ON/OFF Flip - Flop The display on/off flip-flop makes on/off the liquid crystal display. When flip-flop is reset (logical low), selective voltage or non selective voltage appears on segment output terminals. When flip-flop is set (logic high), non selective voltage appears on segment output terminals regardless of display RAM data. The display on/off flip-flop can changes status by instruction. The display data at all segment disappear while RSTB is low. The status of the flip-flop is output to DB5 by status read instruction. The display on/off flip-flop synchronized by CL signal.
X Page Register X page register designates pages of the internal display data RAM. Count function is not available. An address is set by instruction.
Y Address Counter Y address counter designates address of the internal display data RAM. An address is set by instruction and is increased by 1 automatically by read or write operations of display data.
Display Data RAM Display data RAM stores a display data for liquid crystal display. To indicate on state dot matrix of liquid crystal display, write data 1. The other way, off state, writes 0. Display data RAM address and segment output can be controlled by ADC signal. -- -- ADC = H Y-address 0:S1 - Y address 63:S64 ADC = L Y-address 0:S64 - Y address 63:S1
ADC terminal connect the VDD or VSS.
Display Start Line Register The display start line register indicates of display data RAM to display top line of liquid crystal display. Bit data (DB<0:5>) of the display start line set instruction is latched in display start line register. Latched data is transferred to the Z address counter while FRM is high, presetting the Z address counter. It is used for scrolling of the liquid crystal display screen.
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64CH SEGMENT DRIVER FOR DOT MATRIX LCD
S6B0108
DISPLAY CONTROL INSTRUCTION
The display control instructions control the internal state of the S6B0108. Instruction is received from MPU to S6B0108 for the display control. The following table shows various instructions. Instruction Display on/off RS L R/W L DB7 L DB6 L DB5 H DB4 H DB3 H DB2 H DB1 H DB0 L/H Function Controls the display on or off. Internal status and display RAM data is not affected. L: OFF, H: ON Sets the Y address in the Y address counter. Sets the X address at the X address register. Indicates the display data RAM displayed at the top of the screen. L Read status. BUSY L: Ready H: In operation ON/OFF L: Display ON H: Display OFF RESET L: Normal H: Reset Writes data (DB0:7) into display data RAM. After writing instruction, Y address is increased by 1 automatically. Reads data (DB0:7) from display data RAM to the data bus.
Set address (Y address) Set page (X address) Display start line (Z address) Status read
L
L
L
H
Y address (0 - 63)
L L
L L
H H
L H
H
H
H
Page (0 - 7)
Display start line (0 - 63)
L
H
Busy
L
On/ Off
Rese t
L
L
L
Write display data
H
L
Write data
Read display data
H
H
Read data
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S6B0108
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
DISPLAY ON/OFF RS 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 1 DB3 1 DB2 1 DB1 1 DB0 D
The display data appears when D is 1 and disappears when D is 0. Though the data is not on the screen with D = 0, it remains in the display data RAM. Therefore, you can make it appear by changing D = 0 into D = 1.
SET ADDRESS (Y ADDRESS) S 0 R/W 0 DB7 0 DB6 1 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0
Y address (AC0 - AC5) of the display data RAM is set in the Y address counter. An address is set by instruction and increased by 1 automatically by read or write operations of display data.
SET PAGE (X ADDRESS) RS 0 R/W 0 DB7 1 DB6 0 DB5 1 DB4 1 DB3 1 DB2 AC2 DB1 AC1 DB0 AC0
X address(AC0 - AC2) of the display data RAM is set in the X address register. Writing or reading to or from MPU is executed in this specified page until the next page is set.
DISPLAY START LINE (Z ADDRESS) RS 0 R/W 0 DB7 1 DB6 1 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0
Z address (AC0 - AC5) of the display data RAM is set in the display start line register and displayed at the top of the screen. When the display duty cycle is 1/64 or others(1/32 - 1/64), the data of total line number of LCD screen, from the line specified by display start line instruction, is displayed.
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64CH SEGMENT DRIVER FOR DOT MATRIX LCD
S6B0108
STATUS READ RS 0 * R/W 1 DB7 BUSY DB6 0 DB5 ON/OFF DB4 RESET DB3 0 DB2 0 DB1 0 DB0 0
BUSY When BUSY is 1, the Chip is executing internal operation and no instructions are accepted. When BUSY is 0, the Chip is ready to accept any instructions. ON/OFF When ON/OFF is 1, the display is off. When ON/OFF is 0, the display is on.
*
*
RESET When RESET is 1, the system is being initialized. In this condition, no instructions except status read can be accepted. When RESET is 0, initializing has finished and the system is in the usual operation condition.
WRITE DISPLAY DATA RS 1 R/W 0 DB7 D7 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0
Writes data (D0 - D7) into the display data RAM. After writing instruction, Y address is increased by 1 automatically. READ DISPLAY DATA RS 1 R/W 1 DB7 D7 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0
Reads data (D0 - D7) from the display data RAM. After reading instruction, Y address is increased by 1 automatically.
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S6B0108
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
APPLICATION CIRCUIT
1/64 DUTY COMMON DRIVER (S6B0107) INTERFACE CIRCUIT
R1 R2
From MPU
-
CS1B CS2B CS3 R/W RS E DB0
R
CR
C
-
DB7 RSTB VD D ADC
VD D V0 V5 V2 V3 VEE VSS
V0 V5 V1 V4 VEE
V0R, V 0L V5R, V 5L V1R, V 1L V4R, V 4L VEE S6B0107
DIO1 DIO2 M FRM CLK1 CLK2 CL2
Open Open M FRM CLK1 CLK2 CL2 S6B0108
V0R, V 0L V5R, V 5L V2R, V 2L V3R, V 3L VEE1, V EE2 VSS
VD D
VD D SHL FS MS PCLK2 SD2 DS1 VSS
S1
S64
C1 C64
SEG1 COM1 LCD COM64
SEG64
VD D V0 R1 V1 R1 V2 R2 V3 R1 V4 R1 V5
VEE
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64CH SEGMENT DRIVER FOR DOT MATRIX LCD
S6B0108
TIMING DIAGRAM (1/64 DUTY)
CLK1 1 CLK2 64 Input CL FRM 1 Frame M V0 V1 C1 V4 V4 V5 V1 Common C2 V4 V0 V1 C64 V4 V5 V0 S1 V3 Segment S64 V3 V5 V0 V2 V3 V2 V3 V5 V2 V2 V4 V5 V0 V1 V1 V4 V4 V0 V5 V1 1 Frame 1 2 3 64 1 2 3 64 1 2 3 48 49
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S6B0108
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
LCD PANEL INTERFACE APPLICATION CIRCUIT
S6B0108 No. 1 S1 ..... S64 ..... S6B0107 (master) C1 C2 C3 Cf Rf CR R C64 COM64 COM1 COM2 COM3
S6B0108 No. 2 S1 ..... S64 .....
.....
S6B0108 No. 8 S1 ..... S64 .....
LCD Panel
C1 C2 C3 COM65 COM66 COM67
(128 x 512dots)
C64 S6B0107 (slave) COM128 ..... S1 ..... S64 No. 9 S6B0108 ..... S1 ..... S64 No. 10 S6B0108 ..... ..... S1 ..... S64 No. 16 S6B0108
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