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| Order this document from Analog Marketing Product Preview Picture-in-Picture (PIP) Controller The MC44463 Picture-In-Picture (PIP) controller is a low cost member of a family of high performance PIP controllers and video processors for television. It is a follow-up to the MC44461 PIP, in which two additional modes of operation have been added. A replay mode is provided, which captures several seconds of the main picture for replay in four different speeds. The capture time is programmable in four resolutions (ratio of captured fields to total fields), which trade the number of fields captured to the length of replay time. The second additional mode provides for multiple small picture overlays from a second non-synchronized source. The number of PIP images is 3 for the 1/9 screen area and 4 for the 1/16 screen area. Like the MC44461 this is NTSC compatible, I2C bus controlled and available in the 56-pin shrink dip (SDIP) package. MC44463 REPLAY AND MULTIPLE PICTURE-IN-PICTURE (PIP) CONTROLLER SEMICONDUCTOR TECHNICAL DATA * * * * * * * * * * * * * * * The main features of the MC44463 are: Three PIP Functional Modes: Standard Single Active PIP Mode, Up to 8 Seconds of Capture and Replay Mode, and a 3 or 4 Multiple PIP Mode - Vertical Stacked with 1 Active at Any One Time 4 Capture Resolutions - 1 out of 10, 1:8, 1:6, 1:4. 4 Playback Speeds = 1 Times Acquire Speed; 1/2; 1/4; 1/8 Full 2 Frame Store for the Single PIP Removes the Rolling Store/Playback Memory Interference - "Joint Line" External Memory for Replay and Multiple Modes: 4 Meg and 16 Meg Two NTSC CVBS Inputs - Switchable Main and PIP Video Signals Single NTSC CVBS Output Allows Simple TV Chassis Integration Two PIP Sizes; 1/16 and 1/9 Screen Area - Freeze Field Feature Variable PIP Position in 64-X by 64-Y Steps PIP Border with Programmable Color Programmable PIP Tint and Saturation Control Automatic Main to PIP Contrast Balance Vertical Filter I2C Bus Control - No External Variable Adjustments Needed Operates from a Single 5.0 V Supply Economical 56-Pin Shrink DIP Package 56 1 B SUFFIX PLASTIC PACKAGE CASE 859 (SDIP) ORDERING INFORMATION Device MC44463B Operating Temperature Range TJ = -65 to +150C Package SDIP Composite Video Simplified System Diagram CV Tuner/IF CVin Video Processor CV1 PIP MC44463 CV2 IIC R G B Back Panel Composite Video Input 4 Meg Memory This document contains information on a product under development. Motorola reserves the right to change or discontinue thisIC DEVICE DATA MOTOROLA ANALOG product without notice. (c) Motorola, Inc. 1996 Issue 1 1 AAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAA A A A A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAA A A A A AAA A A A A A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A ANALOG TO DIGITAL CONVERTER VERTICAL TIMEBASE HORIZONTAL TIMEBASE VIDEO POWER SUPPLY MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS (VCC = VDD = 5.0 V, TA = 25C, unless otherwise noted.) AA A A A AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAA AA A A AAA A AA A AA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA A AA A AA AA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AA A A A AA AAAAAAAAAAAAAAAAAAAAAAA A AA AAA A AA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAA A AA NOTE: Sample Clock Frequency (4/3 FSC) ADC - U, V Frequency Response @ -5.0 dB ADC - Y Frequency Response @ -5.0 dB Differential Non-Linearity Integral Non-Linearity Resolution Vertical Sync Integration Time Vertical Countdown Window Burst Gate Width Burst Gate Timing (from Trailing Edge Hsync, Pin 24) HPLL Jitter HPLL Pull-In Range Free Run HPLL Frequency (Pin 16) Output Impedance Video Crosstalk (@ 75% Color Bars) Main to PIP PIP to Main Color Bar Accuracy Video Frequency Response (Main Video to -1.0 dB) Video Gain Video Output DC Level (Sync Tip) Composite Video Output (Pin 49, Unterminated) Composite Video Input (Pin 34 or 36) Total Supply (Pins 8, 15, 43 and 50) Junction Temperature (Storage and Operating) Power Dissipation Maximum Power Dissipation @ 70C Thermal Resistance, Junction-to-Air Output Current Input Voltage Range Power Supply Voltage Power Supply Voltage 2 ESD data available upon request. Rating Characteristic Symbol PD RJA TJ VCC VDD VIR IO MC44463 -65 to +150 -0.5 to +6.0 -0.5 to +6.0 -0.5, VDD + 0.5 Value 160 1.3 59 Total ISupply Symbol CVi - - - - - - - - - - - - - - - - - - - - W C/W Unit mA C V V V MOTOROLA ANALOG IC DEVICE DATA Min - - - - - - - - - - - - - - - - - - - - - - - 232/296 15734 +2/-1 4.773 400 4.0 4.0 Typ 200 110 1.0 4.0 1.0 5.0 6.0 1.0 2.0 1.0 31 55 55 10 1 - Max 160 - - - - - 6 - - - - - - - - - - - - - - - - H lines MHz MHz MHz Unit LSB LSB Vpp Vpp Vdc Bits deg mA Hz Hz dB dB s s s ns kHz MC44463 ELECTRICAL CHARACTERISTICS (continued) (VCC = VDD = 5.0 V, TA = 25C, unless otherwise noted.) Characteristic DIGITAL TO ANALOG CONVERTER Resolution Symbol Min Typ Max Unit Y Decoder ACC Main Out Decoder Xtal Decoder PLL 16 FSC PLL 37 49 38 39 7 NTSC Encoder 0 90 4X S/C Osc + PLL PIP Switch 0 90 4X S/C Osc + PLL 14.32 MHz 16X S/C Osc + PLL Clamp YUV NTSC Decoder V U 57.28 MHz Multiplexer AAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAA A A A A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAA A A A A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAA A A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A - - - - - - - - - - - 6 - - - - Bits Integral Non-Linearity 1 LSB LSB Deg dB Differential Non-Linearity +2/-1 10 Tint DAC Control Range (in 64 Steps) Saturation DAC Control Range (in 64 steps) 6.0 NTSC DECODER Color Kill Threshold - - - - - - -24/-16 1.0 5.0 - - - dB dB dB Threshold Hysteresis ACC (Chroma Amplitude Change, +3.0 dB to -12 dB) PIP CHARACTERISTICS PIP Size 1/9 Screen Horizontal 1/9 Screen Vertical 1/16 Screen Horizontal 1/16 Screen Vertical Border Size Horizontal Border Size Vertical - - - - - - - - - - 114 71 84 53 3 2 - - - - - - - - - pels lines pels lines pels - - - - - lines Output PEL Clock (4 FSC) 14.318 100 100 MHz % % Position Control Range Horizontal (% of Main Picture), 64 Steps Position Control Range Vertical (% of Main Picture), 64 Steps Figure 1. Representative Block Diagram Decoder Clamp Caps Filter PLL 33 40 41 42 ADC Mid-Ref 51 28 31 Sync Sep H PLL Video 1 Video 2 36 34 Input Switch Low Pass Filter Band Pass Filter Filter Tracking H and V Timebase Y YUV Clamp V U 6-Bit ADC 3 6 6 Tint DAC Sat DAC Vert 6 6 Digital Logic 6 1 2 3 4 5 30 Test Clock Hin Vin SCL SDA Reset Multi Test 44 Encoder Phase 45 Encoder ACC 3.0 MHz LPF 3.0 MHz LPF 3.0 MHz LPF U DAC V DAC Y DAC 6 6 Memory Control Logic 10 to 27 Memory 46 Encoder PLL 47 52 53 54 Encoder Encoder Clamp Caps Xtal This device contains approximately 300,000 active transistors. MOTOROLA ANALOG IC DEVICE DATA 3 MC44463 Figure 2. Application Circuit 5.0 V 5.0 V Horiz In Vert In I2C Ser Cl I2C Ser Data 5.0 V 1.0 k 1.0 k 1.0 k 1.0 k 1 470 k 2.2 F 47 k 100 2 3 4 5 6 7 8 Hin Vin SCL SDA Reset Test Clock MC44463 N/C N/C 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 0.01 0.01 0.01 0.01 5.0 V 0.1 F 75 Video Out 100 k X3 0.1 0.01 5.0 V 0.01 0.01 0.01 68 k 0.068 0.22 X2 12 0.1 0.1 X1 75 Video 1 Video 2 75 2700 12 1000 0.1 Encoder V Cap Encoder U Cap Endoder Y Cap ADC Mid Ref Video Out VCC Video Out Analog Gnd Encoder Xtal Encoder PLL Encoder ACC Encoder Phase Analog VCC Decoder V Cap Decoder U Cap Decoder Y Cap Decoder PLL Decoder Xtal Decoder ACC Video In 1 Analog Gnd Video In 2 Filter PLL 503 kHz Resonator H PLL Multi Test Sync In 16 FSC Filter VDD (dig) VSS (dig) OEB CASB DQ2 DQ3 DQ0 DQ1 RWB RASB A9 A0 A1 A2 A3 A4 A5 A6 A7 A8 Sync Sep 1000 5.0 V 100 9 10 11 12 13 14 15 16 17 18 5.0 V 1 2 3 4 5 6 7 8 9 10 A0 A1 A2 A3 A4 A5 A6 A7 A8 19 20 21 22 23 24 25 26 27 28 GN CASN DQ2 DQ3 YSS DQ0 DQ1 WN RASN A9 A8 A7 A6 A5 A4 VCC A3 A2 A1 A0 20 19 18 17 16 15 14 13 12 11 A8 A7 A6 A5 A4 A3 A2 A1 A0 0.01 1000 0.01 330 2200 4.7 F 62 k 2.2 k 4.7 F MCM54400A-C X1 - 503 kHz - Murata Erie CSB503F2 or equivalent X2 - 14.31818 MHz - Fox 143-20 or equivalent X3 - 14.31818 MHz - Fox 143-20 or equivalent 4 MOTOROLA ANALOG IC DEVICE DATA MC44463 I2C REGISTER DESCRIPTIONS Base write address = 26h Base read address = 27h Read Register There are two active bits in the single read byte available from the MC44463 as follows: Test Mode/Main Vertical and Horizontal Polarity Register Sub-address = 03h Internal Test Mode Register (ITM0-2) - D0-D2 Sets the Multi Test Pin output to provide one of several internal signals for test and production alignment. Also controls the test memory address counter. Write Vertical Indicator (WVI0) - D7 When 0 indicates that the write operation specified by the last I2C command has been completed. PIP Sync Detect Bit (PSD0) - D1 When 0 indicates that the PIP video H pulses are present and the horizontal timebase oscillator is within acceptable limits. Write Registers Read Start Position/Write Start Position Registers Sub-address = 00h Write Raster Position Start Bits (WPS0-2) - D0-D2 Establishes the horizontal beginning of the PIP and its black level measurement gate. This beginning may be varied by approximately 3.0 s. The position of this pulse may be observed through the Multi Test Pin 30 (See Test Mode Register Sub-address 03h). Read Raster Position Bits (RPS0-3) - D4-D7 Establishes the clamp gate position for the black level reference for the main picture. This position may be varied by approximately 5.0 s. The position of this pulse may be observed through the Multi Test Pin 30 (See Test Mode Register Sub-address 03h). Pip Switch Delay/Vertical Filter Register Sub-address = 01h PIP Switch Delay Bits (PSD0-3) - D0-D3 Delays the start of PIP on time relative to the PIP picture. These bits are used to center the PIP border and PIP picture in the horizontal direction. Vertical Filter Bit (VFON) - D4 When the filter is activated (VFON = 1) a three line weighted average is taken to provide the data stored in the field memory. Border Color Register Sub-address = 02h Border Color Bits (BC0-2) - D0-D2 These Bits control the color of the border. Note that when using one of the saturated border colors it is possible to get objectionable dot crawl at the edge of the border in some TVs unless appropriate comb filtering is used in the TV circuitry. BC (2:0) 000 001 010 011 Border Color Black White 70% No Border (clear) Blue 100 101 110 111 Green Red White MOTOROLA ANALOG IC DEVICE DATA AAAAAAAAAAAAAAAA A AAAAAAAAAAA A AAAAAAAAAAAAAAAA A AAAAAAAAAAA A AAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAA A No Border (clear) AAAAAAAAAAA A AAAAAAAAAAAAAAAA A AAAAAAAAAAA A AAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAA A AAAAAAAAAAA A AAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA AAAAAA ITM (2:0) 000 001 010 011 Multi-Test I/O and Function Input - Analog Test mode Input - Digital Test mode Output - Sync Detect Output - PIP Switch 100 101 110 111 Output - PIP H Detect Output - PIP V Detect Output - PIP Clamp Output - Main Clamp Main vertical polarity select bit (MVP0) - D6 Selects polarity of active level of vertical reference input. 0 = positive going, 1 = negative going. Main horizontal polarity select bit (MHP0) - D7 Selects polarity of active level of horizontal reference input. 0 = positive going, 1 = negative going. PIP Freeze/PIP Size/Main and PIP Video Source Register Sub-address = 04h A A A A A AAAAAAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAA AAAAAAA A AAAAAAAAAAAAAAAA AAAAAA A A A A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAA AAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAA AAAAAAAAAA AAAA LIVE_P (1:0) 00 01 10 11 1/16 Size 1/9 Size Top = LIVE Top = LIVE 2nd from Top = LIVE 3rd from Top = LIVE 4th from Top = LIVE 2nd from Top = LIVE 3rd from Top = LIVE 3rd from Top = LIVE LIVE PIP Select Bits (LIVE_P0-1) - D0-D1 Selects which of the mutliple PIP pictures is the active "live" one. PIP Freeze Bit (STIL0) - D4 When set to one, the most recently received field is continuously displayed until the freeze bit is cleared. PIP Size Bit (PSI90) - D5 Switches the PIP size between 1/16 main size (when 0) and 1/9 main size (when 1). Main Video Source Select Bit (MSEL0) - D6 Selects which video input will be applied to the PIP switch as the main video out. PIP Video Source Select Bit (PSEL0) - D7 Selects which video input will be applied to the video decoder to provide the PIP video. MSEL/PSEL 0 1 Function AAAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA AAAAAAAA Video 1 Input to Main/ Video 1 Input to PIP Video 2 Input to Main/ Video 2 Input to PIP 5 MC44463 PIP On/PIP Blank Register Sub-address = 05h bits are set to a single value determined to be correct in the application. PIP Acquire/Playback Register Sub-address = 0Bh 0010 0100 1000 2nd from Top = On 3rd from Top = On 4th from Top = On 2nd from Top = On 3rd from Top = On 3rd from Top = On PIP Blanking Bits (PBL0-3) - D4-D7 When on (1) sets the corresponding PIP to black. If the individual PIP is off, then it will be black when it is turned on. PBL (7:4) 0000 0001 0010 0100 1000 Function PIP Picture Normal Top = Blanked (Set to Black) 2nd from Top = Blanked (Set to Black) 3rd from Top = Blanked (Set to Black) 4th from Top = Blanked (Set to Black) PIP X Position Register Sub-address = 06h X Position Bits (XPS0-5) - D0-D5 Moves the PIP start position from the left to the right edge of the display in 64 steps. There is protection circuitry to prevent the PIP from interfering with the main picture sync pulses. PIP Y Position Register Sub-address = 07h Y Position Bits (YPS0-5) - D0-D5 Moves the PIP start position from the top to the bottom edge of the display in 64 steps. There is protection circuitry to prevent the PIP from interfering with the main picture sync pulses. PIP Chroma Level Register Sub-address = 08h PIP Tint Level Register Sub-address = 09h Tint (T0-5) - D0-D5 An auto phase control compares the main color burst to the internally generated pseudo color burst so that the tints are matched. In addition to this, the tint of the PIP can be varied 10 in a total of 64 steps by changing the value of these bits to suit viewer preference. PIP Luma Delay Register Sub-address = 0Ah Y Delay (YDL0-2) - D0-D2 Since the Chroma passes through a bandpass filter and the color decoder, it is delayed with respect to the Luma signal. Therefore, to time match the Luma and Chroma these 6 A A A AAAAAAAAAAA AAAAAAAAAAA A A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAA A AAAAAAAAAAAAAAAA A AAAAAAAAAAA A AAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAA A Chroma (C0-5) - D0-D5 The color of the PIP can be adjusted to suit viewer preference by setting the value stored in these bits. A total of 64 steps varies the color from no color to maximum. This control acts in conjunction with the auto phase control. AAAAAAAAAAA A AAAAAAAAAAAAAAAA A AAAAAAAAAAA A AAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAA A A A A A A A AAAAAAAAAAAAAAAA AAAAAAAAAAA A A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A AAAAAAAAAAA A A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAA A AAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAA A AAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAA A AAAAAAAAAAAAAAAA A AAAAAAAAAAA A AAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAA A AAAAAAAAAAA A AAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA AAAAAA ACQ_SP (1:0) 00 01 10 11 Function Acquire 1 Out of Every 4 Fields Acquire 1 Out of Every 6 Fields Acquire 1 Out of Every 8 Fields Acquire 1 Out of Every 10 Fields AAAAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA AAAAAAA AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAA AAAAAAA AAAAAAA A A AAAAAAAAAAAAAAAAA A A AAAAAAA A A AAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAA AAAAAAA A AAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAA AAAAAAAAAAA AAAAA PON (3:0) 0000 0001 1/16 Size 1/9 Size No PIP No PIP Top = On Top = On PIP On Bits (PON0-3) - D4-D3 When on (1) turns the corresponding PIP display on. PIP Acquire Speed Bits (ACQ_SP0-1) - D0-D1 These select the speed of the video acquisition. This is only active when RE_AQ = 1. PIP Save/Clear Bit (RE_AQ) -D2 This bit controls the save and clear function for the instant replay. The bit value 1 is only effective when PON0-3 = 0000. (No PIP display.) RE_AQ (2:2) 0 1 Function Save Memory Clear Reacquire PIP Playback Speed Bits (PB_SP0-1) - D4-D5 These bits control the relative playback speed, to the acquired speed. PB_SP (5:4) 00 01 10 11 Function Playback at 1 x ACQ_SP Speed Playback at 1/2 x ACQ_SP Speed Playback at 1/4 x ACQ_SP Speed Playback at 1/8 x ACQ_SP Speed PIP Playback Control Bit (PB) - D6 This bit controls the start/stop of the instant replay function. PB (6:6) 0 1 Function No Action Instant Replay Activated PIP Fill/Background/Free Run/Test Register Sub-address = 0Ch PIP Fill Bits (PIPFILL0-1) - D0-D1 May be used to fill the PIP with one of three selectable solid colors PIPFILL (1:0) 00 01 10 11 Function Normal Red Green Blue Test Register Bits (INTC0 and MACR0) - D6-D7 When the FRUN is set to 1 the circuitry provides a generated sync and displays a flat field that can be either dark blue or gray determined by the BGND bit. BGND (2:2) 0 1 Function Blue 50% White MOTOROLA ANALOG IC DEVICE DATA AAAAA A A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA AAAAA A A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA AAAAA A A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Sub- address 0C 0B 0A 09 08 07 06 05 04 03 02 01 00 PSEL0 MHP0 RPS3 PBL3 INTC D7 - - - - - - - - MSEL0 MACR MVP0 RPS2 PBL2 PB D6 - - - - - - - PB_SP1 FRUN PSI90 RPS1 YPS5 XPS5 PBL1 C5 D5 T5 - - - - Register 0Ch : D5 -> 1, D2 -> 0 or 1 (Optional) Register 0Bh : D6 -> 0 Register 04h : D0-D1 -> 0 to 3 Register 05h : D0-D3 -> 07h or 0Fh Multiple PIP (MPIP) Operation Register 05h : D0-D7 -> 01h Register 0Bh : D6 -> 0 Single PIP (SPIP) Operation Function Control of the MC44463 There are three modes of operation; Single PIP, Multiple PIP and Replay. These are enabled by setting specific register bits in the I2C register set. MOTOROLA ANALOG IC DEVICE DATA I2C REGISTER TABLE MC44463 PB_SP0 VFON STIL0 RPS0 YPS4 XPS4 PBL0 C4 D4 T4 - - - - Data Bit Register 05h: D0 -> 1 Register 0Bh : D6 -> 1, D2 -> 0, D4-D5 -> 0 to 3 Capture Register 0Bh : D6 -> 0, D2 -> 1, D0-D1 -> 0 to 3 Register 05h : D0-D3 -> 0 Capture Ready Replay PIP (RPIP) Operation In sequence, the Capture Ready mode must be first activated, allowing up to 8 seconds of fill memory with the desired video stream. Then the Capture mode must be set, disabling further write to memory. The Capture data may be re-displayed at any time afterword. PON3 PSD3 YPS3 XPS3 C3 D3 T3 - - - - - - - RE_AQ BGND WPS2 PON2 PSD2 YPS2 XPS2 YDL2 ITM2 BC2 C2 D2 T2 - ACQ_SP1 PIPFILL1 LIVE_P1 WPS1 PON1 PSD1 YPS1 XPS1 YDL1 ITM1 BC1 C1 D1 T1 ACQ_SP0 PIPFILL0 LIVE_P0 WPS0 PON0 PSD0 YPS0 XPS0 YDL0 ITM0 BC0 C0 D0 T0 7 MC44463 OUTLINE DIMENSIONS B SUFFIX PLASTIC PACKAGE CASE 859-01 (SDIP) ISSUE O -A56 29 NOTES: 1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH. MAXIMUM MOLD FLASH 0.25 (0.010). INCHES MIN MAX 2.035 2.065 0.540 0.560 0.155 0.200 0.014 0.022 0.035 BSC 0.032 0.046 0.070 BSC 0.300 BSC 0.008 0.015 0.115 0.135 0.600 BSC 0 15 0.020 0.040 MILLIMETERS MIN MAX 51.69 52.45 13.72 14.22 3.94 5.08 0.36 0.56 0.89 BSC 0.81 1.17 1.778 BSC 7.62 BSC 0.20 0.38 2.92 3.43 15.24 BSC 0 15 0.51 1.02 -B1 28 L H C -TSEATING PLANE K F D 56 PL 0.25 (0.010) E M DIM A B C D E F G H J K L M N G N J 56 PL BS M TA S 0.25 (0.010) M T Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 8 MOTOROLA ANALOG IC DEVICE DATA *MC44463/D* MC44463/D |
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