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1M x 32 CMOS STATIC RAM MODULE
Integrated Device Technology, Inc.
IDT7MP4120
FEATURES
* High-density 4MB Static RAM module * Low profile 72-pin ZIP (Zig-zag In-line vertical Package) or 72-pin SIMM (Single In-line Memory Module) * Fast access time: 20ns (max.) * Surface mounted plastic components on an epoxy laminate (FR-4) substrate * Single 5V (10%) power supply * Multiple GND pins and decoupling capacitors for maximum noise immunity * Inputs/outputs directly TTL-compatible
DESCRIPTION
The IDT7MP4120 is a 1M x 32 Static RAM module constructed on an epoxy laminate (FR-4) substrate using 8 1M x 4 Static RAMs in plastic packages. Availability of four chip select lines (one for each group of two RAMs) provides byte access. The IDT7MP4120 is available with access time as fast as 20ns with minimal power consumption. The IDT7MP4120 is packaged in a 72-pin FR-4 ZIP (Zigzag In-line vertical Package)or a 72-pin SIMM (Single In-line Memory Module). The ZIP configuration allows 72 pins to be placed on a package 4.05" long and 0.365" wide. At only 0.60" high, this low-profile package is ideal for systems with minimum board spacing while the SIMM configuration allows use of edge mounted sockets to secure the module. All inputs and outputs of the IDT7MP4120 are TTL-compatible and operate from a single 5V supply. Full asynchronous circuitry requires no clocks or refresh for operation and provides equal access and cycle times for ease of use. Four identification pins (PD0, PD1, PD2 and PD3) are provided for applications in which different density versions of the module are used. In this way, the target system can read the respective levels of PD0, PD1, PD2 and PD3 to determine a 1M depth. The contact pins are plated with 100 micro-inches of nickel covered by 30 micro-inches minimum of selective gold.
PIN CONFIGURATION(1)
NC PD3 PD0 I/O0 I/O1 I/O2 I/O3 VCC A7 A8 A9 I/O4 I/O5 I/O6 I/O7 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
ZIP, SIMM TOP VIEW NOTE: 1. Pins 3, 4, 6 and 7 (PD0, PD1, PD2 and PD3 respectively) are read by the user to determine the density of the module. If PD0 reads GND, PD1 reads NC, PD2 reads GND and PD3 reads NC, then the module has a 1M depth.
The IDT logo is a registered trademark of Integrated Device Technology Inc.
WE
CS1 CS3
A16 GND I/O 16 I/O 17 I/O 18 I/O 19 A10 A11 A12 A13 I/O 20 I/O 21 I/O 22 I/O 23 GND A19 NC
A14
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71
NC PD2 GND PD1 I/O 8 I/O 9 I/O 10 I/O 11 A0 A1 A2 I/O 12 I/O 13 I/O 14 I/O 15 GND A15
PD0 - GND PD1 - NC PD2 - GND PD3 - NC
FUNCTIONAL BLOCK DIAGRAM
CS2 CS4
A17
CS1 CS2 CS3 CS4
A0 - A19
20 3
PD0 - PD3
OE
I/O 24 I/O 25 I/O 26 I/O 27 A3 A4 A5 VCC A6 I/O 28 I/O 29 I/O 30 I/O 31 A18 NC
3019 drw 01
WE OE
8
1M x 32 RAM
8
8
8
I/O0-7
I/O8-15 I/O16-23 I/O24-31
3019 drw 02
PIN NAMES
I/O0-I/O31 A0-A19 Data Inputs/Outputs Addresses Chip Selects Write Enable Output Enable Depth Identification Power Ground No Connect
3019 tbl 01
CS1-CS4 WE OE
PD0-PD3 VCC GND NC
COMMERCIAL TEMPERATURE RANGE
(c)1996 Integrated Device Technology, Inc.
SEPTEMBER 1996
DSC-3019/5
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IDT7MP4120 1M x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CI/O CIN1 CIN2 CIN3 Parameter
(1)
TRUTH TABLE
Max. 15 60 75 20 Unit pF pF pF pF
3019 tbl 02
Conditions V(IN) = 0V V(IN) = 0V V(IN) = 0V V(IN) = 0V
Mode Standby Read Write Read
CS OE WE
H L L L X L X H X H L H
Output High-Z DATAOUT DATAIN High-Z
Power Standby Active Active Active
3019 tbl 05
Data I/O Capacitance Input Capacitance (Address) Input Capacitance (WE, OE) Input Capacitance (CS)
NOTE: 1. This parameter is guaranteed by design but not tested.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM TA TBIAS TSTG IOUT Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature DC Output Current Value -0.5 to +7.0 0 to +70 -10 to +85 -55 to +125 50 Unit V C C C mA
RECOMMENDED DC OPERATING CONDITIONS
Symbol VCC GND VIH VIL Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5(1) Typ. 5.0 0 -- -- Max. 5.5 0 6.0 0.8 Unit V V V V
3019 tbl 03
NOTE: 1. VIL (min) = -1.5V for pulse width less than 10ns.
NOTE: 3019 tbl 06 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Grade Commercial Ambient Temperature 0C to +70C GND 0V VCC 5.0V 10%
3019 tbl 04
DC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V 10%, TA = 0C to +70C)
Symbol |ILI| |ILI| |ILO| VOL VOH Parameter Input Leakage (Address and Control) Input Leakage (Data) Output Leakage Output LOW Output HIGH Test Conditions VCC = Max.; VIN = GND to VCC VCC = Max.; VIN = GND to VCC VCC = Max.; CS = VIH, VOUT = GND to VCC VCC = Min., IOL = 8mA VCC = Min., IOH = -4mA Min. -- -- -- -- 2.4 Max. 80 10 10 0.4 -- Unit A A A V V
3019 tbl 07
Symbol ICC ISB ISB1
Parameter Dynamic Operating Current Standby Supply Current Full Standby Supply Current
Test Conditions f = fMAX; CS = VIL VCC = Max.; Output Open
7MP4120 Max. 1280 480 120
Unit mA mA mA
3019 tbl 08
CS VIH, VCC = Max. Outputs Open, f = fMAX CS VCC - 0.2V; f = 0 VIN > VCC - 0.2V or < 0.2V
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IDT7MP4120 1M x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns 1.5V 1.5V See Figures 1 and 2
2769 tbl 09
+5 V
+5 V
480 DATAOUT
DATAOUT
480
255
30 pF*
255
5 pF*
3019 drw 03
3019 drw 04
*Includes scope and jig. Figure 1. Output Load Figure 2. Output Load (for tOLZ,tOHZ, tCHZ, tCLZ, tWHZ, tOW)
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IDT7MP4120 1M x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(VCC = 5V 10%, TA = 0C to +70C)
7MP4120SxxZ/M -20 Symbol tRC tAA tACS tCLZ tOE tOLZ(1) tCHZ(1) tOHZ(1) tOH tPU(1) tPD
(1) (1)
-25 Max. -- 20 20 -- 12 -- 10 10 -- -- 20 -- -- -- -- -- -- 10 -- -- -- Min. 25 -- -- 3 -- 0 -- -- 3 0 -- 25 20 20 0 20 3 -- 15 0 0 Max. -- 25 25 -- 15 -- 12 12 -- -- 25 -- -- -- -- -- -- 15 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
3019 tbl 10
Parameter Read Cycle Time Address Access Time Chip Select Access Time Chip Select to Output in Low-Z Output Enable to Output Valid Output Enable to Output in Low-Z Chip Deselect to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change Chip Select to Power-Up Time Chip Deselect to Power-Down Time Write Cycle Time Chip Select to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Write Enable to Output in High-Z Data to Write Time Overlap Data Hold from Write Time Output Active from End-of-Write
Min. 20 -- -- 3 -- 0 -- -- 3 0 -- 20 17 17 0 15 3 -- 12 0 0
Read Cycle
Write Cycle tWC tCW tAW tAS tWP tWR tWHZ(1) tDW tDH tOW(1)
NOTE: 1. This parameter is guaranteed by design, but not tested.
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IDT7MP4120 1M x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
tRC ADDRESS tAA
OE
tOE tOH
CS
tACS tCLZ (5) DATA OUT
tOLZ
(5)
tOHZ tCHZ
(5)
(5)
3019 drw 05
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
tRC ADDRESS tAA tOH DATAOUT PREVIOUS DATA VALID tOH DATA VALID
3019 drw 06
TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)
CS
tACS tCLZ DATAOUT
(5)
tCHZ
(5)
3019 drw 07
NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected. CS = VIL. 3. Address valid prior to or coincident with CS transition LOW. 4. OE = VIL. 5. Transition is measured 200mV from steady state. This parameter is guaranteed by design, but not tested.
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IDT7MP4120 1M x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED) (1, 2, 3, 7) WE
tWC ADDRESS
OE
tAW
CS
tAS tWP (7) tWR
WE
tWHZ tOHZ DATA OUT
(4) (6) (6)
tOHZ (6) tOW
(6)
(4)
tDW DATA IN DATA VALID
tDH
3019 drw 08
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED) (1, 2, 3, 5) CS
tWC ADDRESS tAW
CS
tAS tCW tWR
WE
tDW DATAIN DATA VALID
3019 drw 09
tDH
NOTES: 1. WE or CS must be HIGH during all address transitions. 2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE. 3. tWR is measured from the earlier of CS or WE going HIGH to the end of write cycle. 4. During this period, I/O pins are in the output state, and input signals must not be applied. 5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 6. Transition is measured 200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested. 7. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
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IDT7MP4120 1M x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS ZIP VERSION
FRONT VIEW 3.940 3.960 SIDE VIEW 0.365 MAX
0.580 0.600
PIN 1
0.100 TYP
0.250 TYP
0.015 0.025 0.025 TYP
0.125 0.175
0.100 TYP
0.025 TYP
0.050 TYP
PIN 1 REAR VIEW
3019 drw 10
SIMM VERSION
4.240 4.260 3.980 3.988
0.350 MAX.
0.640 0.660
0.390 0.410 0.250 TYP. FRONT VIEW 0.050 TYP. 0.045 0.055 SIDE VIEW
0.240 0.260
PIN 1 0.070 0.090
BACK VIEW
PIN 1
3019 drw 11
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IDT7MP4120 1M x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XXXXX Device Type X Power X Speed X Package X Process/ Temperature Range Blank Z M 20 25 S Commercial (0C to +70C) FR-4 ZIP (Zig-Zag In-line vertical Package) FR-4 SIMM (Single In-line Memory Module) Speed in Nanoseconds Standard Power
7MP4120 1M x 32 Static RAM Module
3019 drw 12
7.07
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