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LTC2430/LTC2431 20-Bit No Latency TM ADCs with Differential Input and Differential Reference
FEATURES
s s
DESCRIPTIO
s s s s
s s
s s
Low Supply Current (200A in Conversion Mode and 4A in Autosleep Mode) Differential Input and Differential Reference with GND to VCC Common Mode Range 3ppm INL, No Missing Codes 10ppm Full-Scale Error and 1ppm Offset 0.56ppm Noise, 20.8 ENOBs No Latency: Digital Filter Settles in a Single Cycle. Each Conversion Is Accurate, Even After an Input Step Single Supply 2.7V to 5.5V Operation Internal Oscillator--No External Components Required 110dB Min, 50Hz/60Hz Notch Filter Pin Compatible with 24-Bit LTC2410/LTC2411
The LTC(R)2430/LTC2431 are 2.7V to 5.5V micropower 20-bit differential analog-to-digital converters with an integrated oscillator, 3ppm INL and 0.56ppm RMS noise. They use delta-sigma technology and provide single cycle settling time for multiplexed applications. Through a single pin, the LTC2430/LTC2431 can be configured for better than 110dB differential mode rejection at 50Hz or 60Hz 2%, or they can be driven by an external oscillator for a user-defined rejection frequency. The internal oscillator requires no external frequency setting components. The converters accept any external differential reference voltage from 0.1V to VCC for flexible ratiometric and remote sensing measurement configurations. The fullscale differential input range is from - 0.5VREF to 0.5VREF. The reference common mode voltage, VREFCM, and the input common mode voltage, VINCM, may be independently set anywhere within GND to VCC. The DC common mode input rejection is better than 120dB. The LTC2430/LTC2431 communicate through a flexible 3-wire digital interface that is compatible with SPI and MICROWIRETM protocols.
, LTC and LT are registered trademarks of Linear Technology Corporation. No Latency is a trademark of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation.
APPLICATIO S
s s s s s s s s s
Direct Sensor Digitizer Weight Scales Direct Temperature Measurement Gas Analyzers Strain Gauge Transducers Instrumentation Data Acquisition Industrial Process Control DVMs and Meters
TYPICAL APPLICATIO S
(VOUT + 0.25V) TO 20V VOUT 3V TO 5V 4.7F 6 LT1790 1 2 4 0.1F
VCC
TUE (ppm OF VREF)
VCC 0.1F
FO
LTC2431 REF + SCK REF -
= INTERNAL OSC/50Hz REJECTION = EXTERNAL CLOCK SOURCE = INTERNAL OSC/60Hz REJECTION
ANALOG INPUT RANGE -0.5VREF TO 0.5VREF
IN + IN - GND
SDO CS
24301 TA01
3-WIRE SPI INTERFACE
U
Total Unadjusted Error (VCC = 5V, VREF = 5V)
5 VCC = 5V 4 VREF = 5V VINCM = VINCM = 2.5V 3 F = GND O 2 1 0 -1 -2 -3 -4 -5 -2.5 -2 -1.5 -1 - 0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) 2 2.5 -45C 25C 85C
24301 G01
U
U
24301f
1
LTC2430/LTC2431
ABSOLUTE AXI U RATI GS (Notes 1, 2)
Digital Output Voltage to GND ..... - 0.3V to (VCC + 0.3V) Operating Temperature Range LTC2430C/LTC2431C .............................. 0C to 70C LTC2430I/LTC2431I ........................... - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C Supply Voltage (VCC) to GND .......................- 0.3V to 7V Analog Input Pins Voltage to GND ......................................... - 0.3V to (VCC + 0.3V) Reference Input Pins Voltage to GND ......................................... - 0.3V to (VCC + 0.3V) Digital Input Voltage to GND ........ - 0.3V to (VCC + 0.3V)
PACKAGE/ORDER I FOR ATIO
TOP VIEW GND VCC REF
+
ORDER PART NUMBER
16 GND 15 GND 14 FO 13 SCK 12 SDO 11 CS 10 GND 9 GND
1 2 3 4 5 6 7 8
LTC2430CGN LTC2430IGN
REF - IN + IN - GND GND
GN PART MARKING 2430 2430I
GN PACKAGE 16-LEAD PLASTIC SSOP
TJMAX = 125C, JA = 110C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
PARAMETER Resolution (No Missing Codes) Integral Nonlinearity
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 3, 4)
CONDITIONS 0.1V VREF VCC, - 0.5 * VREF VIN 0.5 * VREF (Note 5) 4.5V VCC 5.5V, REF + = 2.5V, REF- = GND, VINCM = 1.25V (Note 6) 5V VCC 5.5V, REF + = 5V, REF - = GND, VINCM = 2.5V (Note 6) REF + = 2.5V, REF - = GND, VINCM = 1.25V (Note 6) 2.5V REF + VCC, REF - = GND, GND IN + = IN - VCC (Note 14) 2.5V REF + VCC, REF - = GND, GND IN + = IN - VCC 2.5V REF + VCC, REF - = GND, IN + = 0.75REF +, IN - = 0.25 * REF + 2.5V REF + VCC, REF - = GND, IN + = 0.75REF +, IN - = 0.25 * REF + 2.5V REF + VCC, REF - = GND, IN + = 0.25 * REF+, IN - = 0.75 * REF + 2.5V REF + VCC, REF - = GND, IN + = 0.25 * REF+, IN - = 0.75 * REF + 4.5V VCC 5.5V, REF + = 2.5V, REF - = GND, VINCM = 1.25V 5V VCC 5.5V, REF + = 5V, REF - = GND, VINCM = 2.5V REF + = 2.5V, REF - = GND, VINCM = 1.25V 5V VCC 5.5V, REF + = 5V, VREF - = GND, GND IN - = IN + 5V, (Note 13)
q q q
Offset Error Offset Error Drift Positive Full-Scale Error Positive Full-Scale Error Drift Negative Full-Scale Error Negative Full-Scale Error Drift Total Unadjusted Error
Output Noise
2
U
U
W
WW
U
W
ORDER PART NUMBER
TOP VIEW VCC REF + REF - IN + IN - 1 2 3 4 5 10 9 8 7 6 FO SCK SDO CS GND
LTC2431CMS LTC2431IMS
MS PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125C, JA = 120C/W
MS PART MARKING LTXD LTXE
MIN 20
TYP 2 3 10 5 50
MAX
20 20
UNITS Bits ppm of VREF ppm of VREF ppm of VREF V nV/C
q
10 0.1
20
ppm of VREF ppm of VREF/C
q
10 0.1 3 6 15 2.8
20
ppm of VREF ppm of VREF/C ppm of VREF ppm of VREF ppm of VREF VRMS
24301f
LTC2430/LTC2431
CO VERTER CHARACTERISTICS
PARAMETER Input Common Mode Rejection DC Input Common Mode Rejection 60Hz 2% Input Common Mode Rejection 50Hz 2% Input Normal Mode Rejection 60Hz 2% Input Normal Mode Rejection 50Hz 2% Reference Common Mode Rejection DC Power Supply Rejection, DC Power Supply Rejection, 60Hz 2% Power Supply Rejection, 50Hz 2% CONDITIONS GND 2.5V REF + V
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 3, 4)
MIN
q q q q q q
A ALOG I PUT A D REFERE CE
SYMBOL IN + IN - VIN REF + REF - VREF CS (IN +) CS (IN -) CS (REF +) CS (REF -) IDC_LEAK IDC_LEAK IDC_LEAK (IN +) (REF +) (REF -) IDC_LEAK (IN -) PARAMETER Absolute/Common Mode IN + Voltage Absolute/Common Mode IN - Voltage Input Differential Voltage Range (IN + - IN -) Absolute/Common Mode REF + Voltage Absolute/Common Mode REF - Voltage Reference Differential Voltage Range (REF + - REF -) IN + Sampling Capacitance IN - Sampling Capacitance REF + Sampling Capacitance REF - Sampling Capacitance IN + DC Leakage Current IN - DC Leakage Current REF + DC Leakage Current REF - DC Leakage Current
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3)
CONDITIONS
q q q q q q
U
U
U
U
TYP 120
MAX
UNITS dB dB dB
- CC, REF = GND, - = IN + 5V (Note 5) IN
110 140 140 110 110 130
2.5V REF+ VCC, REF - = GND, GND IN - = IN + 5V, (Notes 5, 7) 2.5V REF + VCC, REF - = GND, GND IN - = IN + 5V, (Notes 5, 8) (Notes 5, 7) (Notes 5, 8) 2.5V REF+ VCC, GND REF - 2.5V, VREF = 2.5V, IN - = IN + = GND (Note 5) REF + = 2.5V, REF - = GND, IN - = IN + = GND REF + = 2.5V, REF - REF + = 2.5V, REF - = GND, IN - = GND, IN - = IN + = GND, (Note 7) = IN + = GND, (Note 8)
140 140 140 110 120 120
dB dB dB dB dB dB
U
MIN GND - 0.3V GND - 0.3V - VREF/2 0.1 GND 0.1
TYP
MAX VCC + 0.3V VCC + 0.3V VREF/2 VCC VCC - 0.1V VCC
UNITS V V V V V V pF pF pF pF
1.5 1.5 1.5 1.5 CS = VCC, IN + = GND CS = VCC, IN - = VCC CS = VCC, REF + = VCC CS = VCC, REF - = GND
q q q q
-10 -10 -10 -10
1 1 1 1
10 10 10 10
nA nA nA nA
24301f
3
LTC2430/LTC2431 DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL VIH VIL VIH VIL IIN IIN CIN CIN VOH VOL VOH VOL IOZ PARAMETER High Level Input Voltage CS, FO Low Level Input Voltage CS, FO High Level Input Voltage SCK Low Level Input Voltage SCK Digital Input Current CS, FO Digital Input Current SCK Digital Input Capacitance CS, FO Digital Input Capacitance SCK High Level Output Voltage SDO Low Level Output Voltage SDO High Level Output Voltage SCK Low Level Output Voltage SCK Hi-Z Output Leakage SDO (Note 9) IO = - 800A IO = 1.6mA IO = - 800A (Note 10) IO = 1.6mA (Note 10)
q q q q q
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3)
CONDITIONS 2.7V VCC 5.5V 2.7V VCC 3.3V 4.5V VCC 5.5V 2.7V VCC 5.5V 2.7V VCC 5.5V (Note 9) 2.7V VCC 3.3V (Note 9) 4.5V VCC 5.5V (Note 9) 2.7V VCC 5.5V (Note 9) 0V VIN VCC 0V VIN VCC (Note 9)
q q q q q q
POWER REQUIRE E TS
SYMBOL VCC ICC PARAMETER Supply Voltage Supply Current Conversion Mode Sleep Mode Sleep Mode
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3)
CONDITIONS
q
4
UW
U
U
MIN 2.5 2.0
TYP
MAX
UNITS V V
0.8 0.6 2.5 2.0 0.8 0.6 -10 -10 10 10 VCC - 0.5V 0.4 VCC - 0.5V 0.4 -10 10 10 10
V V V V V V A A pF pF V V V V A
MIN 2.7
TYP
MAX 5.5
UNITS V A A A
CS = 0V (Note 12) CS = VCC (Note 12) CS = VCC, 2.7V VCC 3.3V (Note 12)
q q
200 4 2
300 10
24301f
LTC2430/LTC2431 TI I G CHARACTERISTICS
SYMBOL fEOSC tHEO tLEO tCONV PARAMETER External Oscillator Frequency Range External Oscillator High Period External Oscillator Low Period Conversion Time FO = 0V FO = VCC External Oscillator (Note 11) Internal Oscillator (Note 10) External Oscillator (Notes 10, 11) (Note 10) (Note 9) (Note 9) (Note 9) Internal Oscillator (Notes 10, 12) External Oscillator (Notes 10, 11)
q q q q q q q q q
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3)
CONDITIONS
q q q q q q
fISCK DISCK fESCK tLESCK tHESCK tDOUT_ISCK tDOUT_ESCK t1 t2 t3 t4 tKQMAX tKQMIN t5 t6
Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: VCC = 2.7V to 5.5V unless otherwise specified. VREF = REF + - REF -, VREFCM = (REF + + REF -)/2; VIN = IN + - IN -, VINCM = (IN + + IN -)/2. Note 4: FO pin tied to GND or to VCC or to external conversion clock source with fEOSC = 153600Hz unless otherwise specified. Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is calculated as the measured code minus the expected value. Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz 2% (external oscillator). Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz 2% (external oscillator).
UW
MIN 5 0.25 0.25
TYP
MAX 2000 200 200
UNITS kHz s s ms ms ms kHz kHz
130.86 133.53 136.20 157.03 160.23 163.44 20510/fEOSC (in kHz) 19.2 fEOSC/8 45 250 250 1.22 1.25 1.28 192/fEOSC (in kHz) 24/fESCK (in kHz) 0 0 0 50 220 15 50 50 200 200 200 55 2000
Internal SCK Frequency Internal SCK Duty Cycle External SCK Frequency Range External SCK Low Period External SCK High Period Internal SCK 24-Bit Data Output Time
% kHz ns ns ms ms ms ns ns ns ns ns ns ns ns
External SCK 24-Bit Data Output Time (Note 9) CS to SDO Low Z CS to SDO High Z CS to SCK CS to SCK SCK to SDO Valid SDO Hold After SCK SCK Set-Up Before CS SCK Hold After CS (Note 5) (Note 10) (Note 9)
q q q q q q
Note 9: The converter is in external SCK mode of operation such that the SCK pin is used as digital input. The frequency of the clock signal driving SCK during the data output is fESCK and is expressed in kHz. Note 10: The converter is in internal SCK mode of operation such that the SCK pin is used as digital output. In this mode of operation the SCK pin has a total equivalent load capacitance CLOAD = 20pF. Note 11: The external oscillator is connected to the FO pin. The external oscillator frequency, fEOSC, is expressed in kHz. Note 12: The converter uses the internal oscillator. FO = 0V or FO = VCC. Note 13: The output noise includes the contribution of the internal calibration operations. Note 14: Guaranteed by design and test correlation.
24301f
5
LTC2430/LTC2431 TYPICAL PERFOR A CE CHARACTERISTICS
Total Unadjusted Error (VCC = 5V, VREF = 5V)
5 VCC = 5V 4 VREF = 5V VINCM = VINCM = 2.5V 3 F = GND O 2 1 0 -1 -2 -3 -4 -5 -2.5 -2 -1.5 -1 - 0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) 2 2.5 -45C 5
TUE (ppm OF VREF)
TUE (ppm OF VREF)
25C
85C
TUE (ppm OF VREF)
Integral Nonlinearity (VCC = 5V, VREF = 5V)
5 4 3 25C 5
INL (ppm OF VREF)
INL (ppm OF VREF)
INL (ppm OF VREF)
2 1 0 -1 -2
-45C
85C
VCC = 5V -3 V REF = 5V -4 VINCM = VINCM = 2.5V FO = GND -5 -2.5 -2 -1.5 -1 - 0.5 0 0.5 1 1.5 2 INPUT VOLTAGE (V)
Noise Histogram (Output Rate = 7.5Hz, VCC = 5V, VREF = 5V)
40 35 NUMBER OF READINGS (%) 30 25 20 15 10 5 0 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 OUTPUT CODE (ppm OF VREF) 2 2.5 10,000 CONSECUTIVE READINGS VCC = 5V VREF = 5V VIN = 0V VINCM = 2.5V FO = GND TA = 25C GAUSSIAN DISTRIBUTION m = - 0.25ppm = 0.550ppm
NUMBER OF READINGS (%)
14 12 10 8 6 4 2 0
RMS NOISE (ppm OF VREF)
6
UW
24301 G01 24301 G04
Total Unadjusted Error (VCC = 5V, VREF = 2.5V)
VCC = 5V 4 VREF = 2.5V VINCM = VINCM = 1.25V 3 F = GND O 2 1 0 -1 -2 -3 -4 -5 -1.25 -1 -0.75-0.5 -0.25 0 0.25 0.5 0.75 1 1.25 INPUT VOLTAGE (V)
24301 G02
Total Unadjusted Error (VCC = 2.7V, VREF = 2.5V)
20 VCC = 2.7V 15 VREF = 2.5V VINCM = VINCM = 1.25V 10 FO = GND 5 0 -5 -10 -15 -20 -1.25 -1 -0.75-0.5 -0.25 0 0.25 0.5 0.75 1 1.25 INPUT VOLTAGE (V)
24301 G03
-45C 25C
-45C
25C 85C
85C
Integral Nonlinearity (VCC = 5V, VREF = 2.5V)
VCC = 5V 4 VREF = 2.5V VINCM = VINCM = 1.25V 3 F = GND O 2 85C 1 0 -1 -2 -3 -4 2.5 -5 -1.25 -1 -0.75-0.5 -0.25 0 0.25 0.5 0.75 1 1.25 INPUT VOLTAGE (V)
24301 G05
Integral Nonlinearity (VCC = 2.7V, VREF = 2.5V)
20 VCC = 2.7V 15 VREF = 2.5V VINCM = VINCM = 1.25V 10 FO = GND -45C 5 0 -5 -10 -15 -20 -1.25 -1 -0.75-0.5 -0.25 0 0.25 0.5 0.75 1 1.25 INPUT VOLTAGE (V)
24301 G06
25C
-45C 25C
85C
Noise Histogram (Output Rate = 7.5Hz, VCC = 2.7V, VREF = 2.5V)
20 18 16 10,000 CONSECUTIVE READINGS VCC = 2.7V VREF = 2.5V VIN = 0V VINCM = 2.5V FO = GND TA = 25C GAUSSIAN DISTRIBUTION m = -1.07ppm = 1.06ppm 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 -4 -3 -2 -1 0 1 2 3 4 OUTPUT CODE (ppm OF VREF) 5 6
RMS Noise vs Input Differential Voltage
VCC = 5V VREF = 5V VINCM = 2.5V FO = GND TA = 25C
0 -2.5 -2 -1.5 -1 - 0.5 0 0.5 1 1.5 2 INPUT DIFFERENTIAL VOLTAGE (V)
2.5
24301 G07
24301 G08
24301 G10
24301f
LTC2430/LTC2431 TYPICAL PERFOR A CE CHARACTERISTICS
RMS Noise vs VINCM
3.4 VCC = 5V REF + = 5V REF - = GND VIN = 0V VINCM = GND FO = GND TA = 25C
3.4
3.2
RMS NOISE (V)
RMS NOISE (V)
RMS NOISE (V)
3.0
2.8
2.6
2.4 -1 0 1 3 2 VINCM (V) 4 5 6
RMS Noise vs VREF
3.4
OFFSET ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
3.2
RMS NOISE (V)
3.0
VCC = 5V REF - = GND VIN = 0V VINCM = GND FO = GND TA = 25C
2.8
2.6
2.4
0
1
3 2 VREF (V)
Offset Error vs VCC
1.0 0.8 5 4
FULL-SCALE ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
0.6 0.4 0.2 0 REF + = VCC REF - = GND VIN = 0V VINCM = GND FO = GND TA = 25C 2.7 3.1 3.5 3.9 4.3 VCC (V) 4.7 5.1 5.5
-0.2 -0.4 -0.6 -0.8 -1.0
UW
24301 G11
RMS Noise vs Temperature (TA)
VCC = 5V VREF = 5V VIN = 0V VINCM = GND FO = GND
3.4
RMS Noise vs VCC
REF + = 2.5V REF - = GND VIN = 0V VINCM = GND FO = GND TA = 25C
3.2
3.2
3.0
3.0
2.8
2.8
2.6
2.6
2.4 -50
2.4
-25
0 25 50 TEMPERATURE (C)
75
100
2.7
3.1
3.5
3.9 4.3 VCC (V)
4.7
5.1
5.5
24301 G12
24301 G13
Offset Error vs VINCM
1.0 0.8 0.6 0.4 0.2 0 VCC = 5V REF + = 5V REF - = GND VIN = 0V FO = GND TA = 25C -1 0 1 3 2 VINCM (V) 4 5 6
1.0 0.8 0.6 0.4 0.2 0
Offset Error vs Temperature
-0.2 -0.4 -0.6 -0.8 -1.0
-0.2 -0.4 -0.6 -0.8 VCC = 5V VREF =5V VIN = 0V VINCM = GND FO = GND 0 15 30 45 60 TEMPERATURE (C) 75 90
4
5
24301 G14
-1.0 -45 -30 -15
24301 G15
24301 G16
Offset Error vs VREF
20
Full-Scale Error vs Temperature
3 2 1 0 -1 -2 -3 -4 -5 0 VCC = 5V REF - = GND VIN = 0V VINCM = GND FO = GND TA = 25C 1 3 2 VREF (V) 4 5
24301 G18
+FS ERROR 10 VCC = 5V VREF = 5V FO = GND VINCM = 2.5V -FS ERROR -10
0
-20 -45 -30 -15
0 15 30 45 60 TEMPERATURE (C)
75
90
24301 G17
24301 G19
24301f
7
LTC2430/LTC2431 TYPICAL PERFOR A CE CHARACTERISTICS
Full-Scale Error vs VREF
20 FULL-SCALE ERROR (ppm OF VREF) 15 10 +FS ERROR 5 0 -5 -FS ERROR -10 -15 -20 0 0.5 1 1.5 2 2.5 3 VREF (V) 3.5 4 4.5 5
FULL-SCALE ERROR (ppm OF VREF)
1 0 -1 -2 -3 -4 -5 2.7 3.1 3.5 3.9 4.3 VCC (V) 4.7 5.1 5.5 -FS ERROR
REJECTION (dB)
VCC = 5V REF - = GND FO = GND VINCM = 0.5VREF TA = 25C
PSRR vs Frequency at VCC
0 -20 -40
REJECTION (dB)
CONVERSION CURRENT (A)
REJECTION (dB)
-60 -80 -100 -120 -140 1
VCC = 4.1VDC REF+ = 2.5V REF- = GND IN+ = GND IN- = GND FO = GND TA = 25C
10
10k 100k 1k 100 FREQUENCY AT VCC (Hz)
Conversion Current vs Output Data Rate
1000 900 VREF = VCC IN+ = GND IN- = GND SCK = NC SDO = NC SDI = GND CS = GND FO = EXT OSC TA = 25C 6 VCC = 5V 5
SUPPLY CURRENT (A)
800 700 600 500 400 300 200 100 0
SLEEP MODE CURRENT (A)
10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
24301 G26
8
UW
24301 G20
24301 G23
Full-Scale Error vs VCC
5 4 3 2 +FS ERROR VREF = 2.5V REF - = GND FO = GND VINCM = 0.5VREF TA = 25C
0 -20 -40 -60 -80 -100 -120 -140
PSRR vs Frequency at VCC
VCC = 4.1VDC 1.4V REF+ = 2.5V REF- = GND IN+ = GND IN- = GND FO = GND TA = 25C
0 20 40 60 80 100 120 140 160 180 200 220 FREQUENCY AT VCC (Hz)
24301 G22
24301 G21
PSRR vs Frequency at VCC
0 -20 -40 -60 -80 -100 -120 -140 15170 VCC = 4.1VDC 0.7V REF+ = 2.5V REF- = GND IN+ = GND IN- = GND FO = GND TA = 25C
240 230 220 210 200 190 180 170
Conversion Current vs Temperature
VCC = 5.5V VCC = 5V FO = GND CS = GND SCK = NC SDO = NC VCC = 3V VCC = 2.7V
1M
15220
15270 15320 FREQUENCY AT VCC (Hz)
15370
24301 G24
160 -45 -30 -15
0 15 30 45 60 TEMPERATURE (C)
75
90
24301 G25
Sleep Mode Current vs Temperature
FO = GND CS = VCC SCK = NC SDO = NC
4 3 2 1
VCC = 5.5V
VCC = 5V VCC = 3V
VCC = 3V
VCC = 2.7V 0 -45 -30 -15 0 15 30 45 60 TEMPERATURE (C) 75 90
24301 G27
24301f
LTC2430/LTC2431
PI FU CTIO S
GND (Pins 1, 7, 8, 9, 10, 15, 16): Ground. Multiple ground pins internally connected for optimum ground current flow and VCC decoupling. Connect each one of these pins to a ground plane through a low impedance connection. All seven pins must be connected to ground for proper operation. VCC (Pin 2): Positive Supply Voltage. Bypass to GND with a 10F tantalum capacitor in parallel with 0.1F ceramic capacitor as close to the part as possible. REF + (Pin 3), REF - (Pin 4): Differential Reference Input. The voltage on these pins can have any value between GND and VCC as long as the reference positive input, REF +, is maintained more positive than the reference negative input, REF -, by at least 0.1V. IN + (Pin 5), IN- (Pin 6): Differential Analog Input. The voltage on these pins can have any value between GND - 0.3V and VCC + 0.3V. Within these limits the converter bipolar input range (VIN = IN+ - IN-) extends from - 0.5 * (VREF ) to 0.5 * (VREF ). Outside this input range the converter produces unique overrange and underrange output codes. CS (Pin 11): Active LOW Digital Input. A LOW on this pin enables the SDO digital output and wakes up the ADC. Following each conversion the ADC automatically enters the Sleep mode and remains in this low power state as long as CS is HIGH. A LOW-to-HIGH transition on CS during the Data Output transfer aborts the data transfer and starts a new conversion. (LTC2431) VCC (Pin 1): Positive Supply Voltage. Bypass to GND (Pin 6) with a 10F tantalum capacitor in parallel with 0.1F ceramic capacitor as close to the part as possible. REF + (Pin 2), REF - (Pin 3): Differential Reference Input. The voltage on these pins can have any value between GND and VCC as long as the reference positive input, REF +, is maintained more positive than the reference negative input, REF -, by at least 0.1V. IN + (Pin 4), IN- (Pin 5): Differential Analog Input. The voltage on these pins can have any value between GND - 0.3V and VCC + 0.3V. Within these limits, the converter bipolar input range (VIN = IN+ - IN-) extends from - 0.5 * (VREF ) to 0.5 * (VREF ). Outside this input range, the converter produces unique overrange and underrange output codes. GND (Pin 6): Ground. Connect this pin to a ground plane through a low impedance connection. CS (Pin 7): Active LOW Digital Input. A LOW on this pin enables the SDO digital output and wakes up the ADC. Following each conversion, the ADC automatically enters the Sleep mode and remains in this low power state as long as CS is HIGH. A LOW-to-HIGH transition on CS during the Data Output transfer aborts the data transfer and starts a new conversion.
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(LTC2430) SDO (Pin 12): Three-State Digital Output. During the Data Output period, this pin is used as serial data output. When the chip select CS is HIGH (CS = VCC) the SDO pin is in a high impedance state. During the Conversion and Sleep periods, this pin is used as the conversion status output. The conversion status can be observed by pulling CS LOW. SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal Serial Clock Operation mode, SCK is used as digital output for the internal serial interface clock during the Data Output period. In External Serial Clock Operation mode, SCK is used as digital input for the external serial interface clock during the Data Output period. A weak internal pullup is automatically activated in Internal Serial Clock Operation mode. The Serial Clock Operation mode is determined by the logic level applied to the SCK pin at power up or during the most recent falling edge of CS. FO (Pin 14): Frequency Control Pin. Digital input that controls the ADC's notch frequencies and conversion time. When the FO pin is connected to VCC (FO = VCC), the converter uses its internal oscillator and the digital filter first null is located at 50Hz. When the FO pin is connected to GND (FO = OV), the converter uses its internal oscillator and the digital filter first null is located at 60Hz. When FO is driven by an external clock signal with a frequency fEOSC, the converter uses this signal as its system clock and the digital filter first null is located at a frequency fEOSC/2560.
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LTC2430/LTC2431
PI FU CTIO S
SDO (Pin 8): Three-State Digital Output. During the Data Output period, this pin is used as the serial data output. When the chip select CS is HIGH (CS = VCC), the SDO pin is in a high impedance state. During the Conversion and Sleep periods, this pin is used as the conversion status output. The conversion status can be observed by pulling CS LOW. SCK (Pin 9): Bidirectional Digital Clock Pin. In Internal Serial Clock Operation mode, SCK is used as the digital output for the internal serial interface clock during the Data Output period. In External Serial Clock Operation mode, SCK is used as the digital input for the external serial interface clock during the Data Output period. A weak internal pull-up is automatically activated in Internal Serial
FU CTIO AL BLOCK DIAGRA
VCC GND
IN + IN -
+ -

ADC SERIAL INTERFACE DECIMATING FIR
REF + REF -
DAC
TEST CIRCUITS
SDO 1.69k CLOAD = 20pF
2431 TA03
Hi-Z TO VOH VOL TO VOH VOH TO Hi-Z
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(LTC2431) Clock Operation mode. The Serial Clock Operation mode is determined by the logic level applied to the SCK pin at power up or during the most recent falling edge of CS. FO (Pin 10): Frequency Control Pin. Digital input that controls the ADC's notch frequencies and conversion time. When the FO pin is connected to VCC (FO = VCC), the converter uses its internal oscillator and the digital filter first null is located at 50Hz. When the FO pin is connected to GND (FO = OV), the converter uses its internal oscillator and the digital filter first null is located at 60Hz. When FO is driven by an external clock signal with a frequency fEOSC, the converter uses this signal as its system clock and the digital filter first null is located at a frequency fEOSC/2560.
INTERNAL OSCILLATOR AUTOCALIBRATION AND CONTROL
FO (INT/EXT)
SDO SCK CS
2431 FD
Figure 1
VCC 1.69k SDO CLOAD = 20pF
2431 TA04
Hi-Z TO VOL VOH TO VOL VOL TO Hi-Z
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LTC2430/LTC2431
APPLICATIO S I FOR ATIO
CONVERTER OPERATION Converter Operation Cycle
The LTC2430/LTC2431 are low power, delta-sigma analogto-digital converters with an easy-to-use 3-wire serial interface (see Figure 1). Their operation is made up of three states. The converters' operating cycle begins with the conversion, followed by the low power sleep state and ends with the data output (see Figure 2). The 3-wire interface consists of serial data output (SDO), serial clock (SCK) and chip select (CS). Initially, the LTC2430/LTC2431 perform a conversion. Once the conversion is complete, the device enters the sleep state. The part remains in the sleep state as long as CS is HIGH. While in this sleep state, power consumption is reduced by nearly two orders of magnitude. The conversion result is held indefinitely in a static shift register while the converter is in the sleep state. Once CS is pulled LOW, the device exits the low power mode and enters the data output state. If CS is pulled HIGH before the first rising edge of SCK, the device returns to the low power sleep mode and the conversion result is still held in the internal static shift register. If CS remains LOW after the first rising edge of SCK, the device begins outputting the conversion result. Taking CS high at this point will terminate the data output state and start a new conversion. There is no latency in the conversion result. The data output corresponds to the conversion just performed. This result is shifted out on the serial data out pin (SDO) under the control of the serial clock (SCK). Data is updated on the
CONVERT
SLEEP
FALSE
CS = LOW AND SCK TRUE DATA OUTPUT
2431 F02
Figure 2. LTC2430/LTC2431 State Transition Diagram
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falling edge of SCK allowing the user to reliably latch data on the rising edge of SCK (see Figure 3). The data output state is concluded once 24 bits are read out of the ADC or when CS is brought HIGH. The device automatically initiates a new conversion and the cycle repeats. Through timing control of the CS and SCK pins, the LTC2430/LTC2431 offer several flexible modes of operation (internal or external SCK and free-running conversion modes). These various modes do not require programming configuration registers; moreover, they do not disturb the cyclic operation described above. These modes of operation are described in detail in the Serial Interface Timing Modes section. Conversion Clock A major advantage the delta-sigma converter offers over conventional type converters is an on-chip digital filter (commonly implemented as a Sinc or Comb filter). For high resolution, low frequency applications, this filter is typically designed to reject line frequencies of 50Hz or 60Hz plus their harmonics. The filter rejection performance is directly related to the accuracy of the converter system clock. The LTC2430/LTC2431 incorporate a highly accurate on-chip oscillator. This eliminates the need for external frequency setting components such as crystals or oscillators. Clocked by the on-chip oscillator, the LTC2430/ LTC2431 achieve a minimum of 110dB rejection at the line frequency (50Hz or 60Hz 2%). Ease of Use The LTC2430/LTC2431 data output has no latency, filter settling delay or redundant data associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple analog inputs is easy. The LTC2430/LTC2431 perform offset and full-scale calibrations in every conversion cycle. This calibration is transparent to the user and has no effect on the cyclic operation described above. The advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage change and temperature drift.
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LTC2430/LTC2431
APPLICATIO S I FOR ATIO
Power-Up Sequence
The LTC2430/LTC2431 automatically enter an internal reset state when the power supply voltage VCC drops below approximately 2V. This feature guarantees the integrity of the conversion result and of the serial interface mode selection. (See the 2-wire I/O sections in the Serial Interface Timing Modes section.) When the VCC voltage rises above this critical threshold, the LTC2430 or LTC2431 creates an internal power-onreset (POR) signal with a duration of approximately 1ms. The POR signal clears all internal registers. Following the POR signal, the converter starts a normal conversion cycle and follows the succession of states described above. The first conversion result following POR is accurate within the specifications of the device if the power supply voltage is restored within the operating range (2.7V to 5.5V) before the end of the POR time interval. Reference Voltage Range The LTC2430/LTC2431 accept a differential external reference voltage. The absolute/common mode voltage specification for the REF + and REF - pins covers the entire range from GND to VCC. For correct converter operation, the REF + pin must always be more positive than the REF - pin. The LTC2430/LTC2431 can accept a differential reference voltage from 0.1V to VCC. The converter (LTC2430 or LTC2431) output noise is determined by the thermal noise of the front-end circuits, and, as such, its value in microvolts is nearly constant with reference voltage. A decrease in reference voltage will not significantly improve the converter's effective resolution. On the other hand, a reduced reference voltage will improve the converter's overall INL performance. A reduced reference voltage will also improve the converter performance when operated with an external conversion clock (external FO signal) at substantially higher output data rates. Input Voltage Range The analog input is truly differential with an absolute/common mode range for the IN+ and IN- input pins extending from GND - 0.3V to VCC + 0.3V. Outside these limits, the ESD protection devices begin to turn on and the errors due
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to input leakage current increase rapidly. Within these limits, the LTC2430 or LTC2431 converts the bipolar differential input signal, VIN = IN + - IN -, from - FS = - 0.5 * VREF to +FS = 0.5 * VREF where VREF = REF+ - REF -. Outside this range the converter indicates the overrange or the underrange condition using distinct output codes. Input signals applied to IN+ and IN- pins may extend by 300mV below ground and above VCC. In order to limit any fault current, resistors of up to 5k may be added in series with the IN+ and IN- pins without affecting the performance of the device. In the physical layout, it is important to maintain the parasitic capacitance of the connection between these series resistors and the corresponding pins as low as possible; therefore, the resistors should be located as close as practical to the pins. In addition, series resistors will introduce a temperature dependent offset error due to the input leakage current. A 1nA input leakage current will develop a 1ppm offset error on a 5k resistor if VREF = 5V. This error has a very strong temperature dependency. Output Data Format The LTC2430/LTC2431 serial output data stream is 24 bits long. The first 3 bits represent status information indicating the sign and conversion state. The next 21 bits are the conversion result, MSB first. The third and fourth bits together are also used to indicate an underrange condition (the differential input voltage is below - FS) or an overrange condition (the differential input voltage is above + FS). Bit 23 (first output bit) is the end of conversion (EOC) indicator. This bit is available at the SDO pin during the conversion and sleep states whenever the CS pin is LOW. This bit is HIGH during the conversion and goes LOW when the conversion is complete. Bit 22 (second output bit) is a dummy bit (DMY) and is always LOW. Bit 21 (third output bit) is the conversion result sign indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this bit is LOW. Bit 20 (fourth output bit) is the most significant bit (MSB) of the result. This bit in conjunction with Bit 21 also provides the underrange or overrange indication. If both Bit 21 and Bit 20 are HIGH, the differential input voltage is
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LTC2430/LTC2431
APPLICATIO S I FOR ATIO
above +FS. If both Bit 21 and Bit 20 are LOW, the differential input voltage is below -FS. The function of these bits is summarized in Table 1.
Table 1. LTC2430/LTC2431 Status Bits
Input Range VIN 0.5 * VREF 0V VIN < 0.5 * VREF -0.5 * VREF VIN < 0V VIN < - 0.5 * VREF Bit 23 Bit 22 Bit 21 Bit 20 EOC DMY SIG MSB 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0
Bits 20-0 are the 21-bit conversion result MSB first. Bit 0 is the least significant bit (LSB). Data is shifted out of the SDO pin under control of the serial clock (SCK), see Figure 3. Whenever CS is HIGH, SDO remains high impedance and any externally generated SCK clock pulses are ignored by the internal data out shift register.
CS
BIT 23 SDO Hi-Z SCK EOC
BIT 22 "0"
1 SLEEP
Figure 3. Output Data Timing Table 2. LTC2430/LTC2431 Output Data Format
Differential Input Voltage VIN * VIN* 0.5 * VREF** 0.5 * VREF** - 1LSB 0.25 * VREF** 0.25 * VREF** - 1LSB 0 -1LSB - 0.25 * VREF** - 0.25 * VREF** - 1LSB - 0.5 * VREF** VIN* < -0.5 * VREF** Bit 23 EOC 0 0 0 0 0 0 0 0 0 0 Bit 22 DMY 0 0 0 0 0 0 0 0 0 0 Bit 21 SIG 1 1 1 1 1 0 0 0 0 0 Bit 20 MSB 1 0 0 0 0 1 1 1 1 0 Bit 19 0 1 1 0 0 1 1 0 0 1 Bit 18 0 1 0 1 0 1 0 1 0 1 Bit 17 0 1 0 1 0 1 0 1 0 1 ... ... ... ... ... ... ... ... ... ... ... Bit 0 LSB 0 1 0 1 0 1 0 1 0 1
*The differential input voltage VIN = IN+ - IN-. **The differential reference voltage VREF = REF+ - REF-.
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In order to shift the conversion result out of the device, CS must first be driven LOW. EOC is seen at the SDO pin of the device once CS is pulled LOW. EOC changes real time from HIGH to LOW at the completion of a conversion. This signal may be used as an interrupt for an external microcontroller. Bit 23 (EOC) can be captured on the first rising edge of SCK. Bit 22 is shifted out of the device on the first falling edge of SCK. The final data bit (Bit 0) is shifted out on the falling edge of the 23rd SCK and may be latched on the rising edge of the 24th SCK pulse. On the falling edge of the 24th SCK pulse, SDO goes HIGH indicating the initiation of a new conversion cycle. This bit serves as EOC (Bit 22) for the next conversion cycle. Table 2 summarizes the output data format. As long as the voltage on the IN+ and IN- pins is maintained within the - 0.3V to (VCC + 0.3V) absolute maximum operating range, a conversion result is generated for any differential input voltage VIN from -FS = - 0.5 * VREF to +FS = 0.5 * VREF. For differential input voltages greater than
BIT 21 SIG BIT 20 MSB BIT 19 BIT 0 LSB 2 3 4 5 24 CONVERSION
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DATA OUTPUT
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LTC2430/LTC2431
APPLICATIO S I FOR ATIO
NORMAL MODE REJECTION (dB)
+FS, the conversion result is clamped to the value corresponding to the +FS + 1LSB. For differential input voltages below -FS, the conversion result is clamped to the value corresponding to -FS - 1LSB. Frequency Rejection Selection (FO) The LTC2430/LTC2431 internal oscillator provides better than 110dB normal mode rejection at the line frequency and all its harmonics for 50Hz 2% or 60Hz 2%. For 60Hz rejection, FO should be connected to GND while for 50Hz rejection the FO pin should be connected to VCC. The selection of 50Hz or 60Hz rejection can also be made by driving FO to an appropriate logic level. A selection change during the sleep or data output states will not disturb the converter operation. If the selection is made during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. When a fundamental rejection frequency different from 50Hz or 60Hz is required or when the converter must be synchronized with an outside source, the LTC2430 or LTC2431 can operate with an external conversion clock. The converter automatically detects the presence of an external clock signal at the FO pin and turns off the internal oscillator. The frequency fEOSC of the external signal must be at least 5kHz to be detected. The external clock signal duty cycle is not significant as long as the minimum and maximum specifications for the high and low periods tHEO and tLEO are observed. While operating with an external conversion clock of a frequency fEOSC, the LTC2430 or LTC2431 provides better than 110dB normal mode rejection in a frequency range fEOSC/2560 4% and its harmonics. The normal mode rejection as a function of the input frequency deviation from fEOSC/2560 is shown in Figure 4. Whenever an external clock is not present at the FO pin, the converter (LTC2430 or LTC2431) automatically activates its internal oscillator and enters the Internal Conversion Clock mode. Its operation will not be disturbed if the change of conversion clock source occurs during the sleep state or during the data output state while the converter uses an external serial clock. If the change occurs during the conversion state, the result of the conversion in
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-80 -85 -90 -95 -100 -105 -110 -115 -120 -125 -130 -135 -140 -12 -8 -4 0 4 8 12 DIFFERENTIAL INPUT SIGNAL FREQUENCY DEVIATION FROM NOTCH FREQUENCY fEOSC/2560(%)
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Figure 4. LTC2430/LTC2431 Normal Mode Rejection When Using an External Oscillator of Frequency fEOSC
progress may be outside specifications but the following conversions will not be affected. If the change occurs during the data output state and the converter is in the Internal SCK mode, the serial clock duty cycle may be affected but the serial data stream will remain valid. Table 3 summarizes the duration of each state and the achievable output data rate as a function of FO. SERIAL INTERFACE PINS The LTC2430/LTC2431 transmit the conversion results and receives the start of conversion command through a synchronous 3-wire interface. During the conversion and sleep states, this interface can be used to assess the converter status and during the data output state it is used to read the conversion result. Serial Clock Input/Output (SCK) The serial clock signal present on SCK is used to synchronize the data transfer. Each bit of data is shifted out the SDO pin on the falling edge of the serial clock. In the Internal SCK mode of operation, the SCK pin is an output and the converter (LTC2430 or LTC2431) creates its own serial clock by dividing the internal conversion clock by 8. In the External SCK mode of operation, the SCK pin is used as input. The internal or external SCK mode is selected on power-up and then reselected every time a HIGH-to-LOW transition is detected at the CS pin. If SCK
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LTC2430/LTC2431
APPLICATIO S I FOR ATIO
Table 3. LTC2430/LTC2431 State Duration
State CONVERT Operating Mode Internal Oscillator
FO = LOW (60Hz Rejection) FO = HIGH (50Hz Rejection)
External Oscillator
FO = External Oscillator with Frequency fEOSC kHz (fEOSC/2560 Rejection) FO = LOW/HIGH (Internal Oscillator) FO = External Oscillator with Frequency fEOSC kHz
SLEEP DATA OUTPUT Internal Serial Clock
External Serial Clock with Frequency fSCK kHz
is HIGH or floating at power-up or during this transition, the converter enters the internal SCK mode. If SCK is LOW at power-up or during this transition, the converter enters the external SCK mode. Serial Data Output (SDO) The serial data output pin, SDO, provides the result of the last conversion as a serial bit stream (MSB first) during the data output state. In addition, the SDO pin is used as an end of conversion indicator during the conversion and sleep states. When CS is HIGH, the SDO driver is switched to a high impedance state. This allows sharing the serial interface with other devices. If CS is LOW during the convert or sleep state, SDO will output EOC. If CS is LOW during the conversion phase, the EOC bit appears HIGH on the SDO pin. Once the conversion is complete, EOC goes LOW. Chip Select Input (CS) The active LOW chip select, CS, is used to test the conversion status and to enable the data output transfer as described in the previous sections. In addition, the CS signal can be used to trigger a new conversion cycle before the entire serial data transfer has been completed. The converter (LTC2430 or LTC2431) will abort any serial data transfer in progress and start a
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Duration 133ms, Output Data Rate 7.5 Readings/s 160ms, Output Data Rate 6.2 Readings/s 20510/fEOSCs, Output Data Rate fEOSC/20510 Readings/s As Long As CS = HIGH As Long As CS = LOW But Not Longer Than 1.25ms (24 SCK cycles) As Long As CS = LOW But Not Longer Than 192/fEOSCms (24 SCK cycles) As Long As CS = LOW But Not Longer Than 24/fSCKms (24 SCK cycles)
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new conversion cycle anytime a LOW-to-HIGH transition is detected at the CS pin after the converter has entered the data output state (i.e., after the first rising edge of SCK occurs with CS = LOW). Finally, CS can be used to control the free-running modes of operation, see Serial Interface Timing Modes section. Grounding CS will force the ADC to continuously convert at the maximum output rate selected by FO. SERIAL INTERFACE TIMING MODES The LTC2430/LTC2431's 3-wire interface is SPI and MICROWIRE compatible. This interface offers several flexible modes of operation. These include internal/external serial clock, 2- or 3-wire I/O, single cycle conversion. The following sections describe each of these serial interface timing modes in detail. In all these cases, the converter can use the internal oscillator (FO = LOW or FO = HIGH) or an external oscillator connected to the FO pin. Refer to Table 4 for a summary. External Serial Clock, Single Cycle Operation (SPI/MICROWIRE Compatible) This timing mode uses an external serial clock to shift out the conversion result and a CS signal to monitor and control the state of the conversion cycle, see Figure 5.
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Table 4. LTC2430/LTC2431 Interface Timing Modes
Configuration External SCK, Single Cycle Conversion External SCK, 2-Wire I/O Internal SCK, Single Cycle Conversion Internal SCK, 2-Wire I/O, Continuous Conversion
1F VCC LTC2430/ LTC2431 REFERENCE VOLTAGE 0.1V TO VCC ANALOG INPUT RANGE -0.5VREF TO 0.5VREF REF + REF - IN + IN - GND SDO CS SCK FO
CS TEST EOC SDO Hi-Z Hi-Z TEST EOC TEST EOC
BIT 23 EOC
BIT 22
SCK (EXTERNAL) CONVERSION SLEEP SLEEP TEST EOC DATA OUTPUT CONVERSION
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Figure 5. External Serial Clock, Single Cycle Operation
The serial clock mode is selected on the falling edge of CS. To select the external serial clock mode, the serial clock pin (SCK) must be LOW during each CS falling edge. The serial data output pin (SDO) is Hi-Z as long as CS is HIGH. At any time during the conversion cycle, CS may be pulled LOW in order to monitor the state of the converter. While CS is pulled LOW, EOC is output to the SDO pin. EOC = 1 while a conversion is in progress and EOC = 0 if the conversion is over. With CS HIGH, the device automatically enters the low power sleep state once the conversion is complete. When CS is low, the device enters the data output mode. The result is held in the internal static shift register until the first SCK rising edge is seen while CS is LOW. Data is shifted out the SDO pin on each falling edge of SCK. This
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SCK Source External External Internal Internal
2.7V TO 5.5V
VCC
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Conversion Cycle Control CS and SCK SCK CS Continuous
Data Output Control CS and SCK SCK CS Internal
Connection and Waveforms Figures 5, 6 Figure 7 Figures 8, 9 Figure 10
= 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION
3-WIRE SPI INTERFACE
BIT 21 SIG
BIT 20 MSB
BIT 19
BIT 18
BIT 0 LSB
Hi-Z
enables external circuitry to latch the output on the rising edge of SCK. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result can be latched on the 24th rising edge of SCK. On the 24th falling edge of SCK, the device begins a new conversion. SDO goes HIGH (EOC = 1) indicating a conversion is in progress. At the conclusion of the data cycle, CS may remain LOW and EOC monitored as an end-of-conversion interrupt. Alternatively, CS may be driven HIGH setting SDO to Hi-Z. As described above, CS may be pulled LOW at any time in order to monitor the conversion status. Typically, CS remains LOW during the data output state. However, the data output state may be aborted by pulling CS HIGH anytime between the first rising edge and the 24th falling edge of SCK, see Figure 6. On the rising edge of CS,
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LTC2430/LTC2431
APPLICATIO S I FOR ATIO
REFERENCE VOLTAGE 0.1V TO VCC ANALOG INPUT RANGE -0.5VREF TO 0.5VREF
CS TEST EOC TEST EOC
BIT 0 SDO EOC
BIT 23 EOC
Hi-Z
Hi-Z
Hi-Z
SCK (EXTERNAL) SLEEP DATA OUTPUT CONVERSION SLEEP DATA OUTPUT SLEEP TEST EOC (OPTIONAL) CONVERSION
2431 F06
Figure 6. External Serial Clock, Reduced Data Output Length
the device aborts the data output state and immediately initiates a new conversion. This is useful for systems not requiring all 24 bits of output data, aborting an invalid conversion cycle or synchronizing the start of a conversion. External Serial Clock, 2-Wire I/O This timing mode utilizes a 2-wire serial I/O interface. The conversion result is shifted out of the device by an externally generated serial clock (SCK) signal, see Figure 7. CS may be permanently tied to ground, simplifying the user interface or isolation barrier. The external serial clock mode is selected at the end of the power-on reset (POR) cycle. The POR cycle is concluded approximately 1ms after VCC exceeds 2V. The level applied to SCK at this time determines if SCK is internal or external. SCK must be driven LOW prior to the end of POR in order to enter the external serial clock timing mode. Since CS is tied LOW, the end-of-conversion (EOC) can be continuously monitored at the SDO pin during the convert and sleep states. EOC may be used as an interrupt to an external controller indicating the conversion result is ready. EOC = 1 while the conversion is in progress and
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2.7V TO 5.5V 1F VCC LTC2430/ LTC2431 REF + REF - IN + IN - GND SDO CS SCK 3-WIRE SPI INTERFACE FO
VCC
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= 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION
BIT 22
BIT 21 SIG
BIT 20 MSB
BIT 19
BIT 9
BIT 8
Hi-Z
EOC = 0 once the conversion ends. On the falling edge of EOC, the conversion result is loaded into an internal static shift register. Data is shifted out the SDO pin on each falling edge of SCK enabling external circuitry to latch data on the rising edge of SCK. EOC can be latched on the first rising edge of SCK. On the 24th falling edge of SCK, SDO goes HIGH (EOC = 1) indicating a new conversion has begun. Internal Serial Clock, Single Cycle Operation This timing mode uses an internal serial clock to shift out the conversion result and a CS signal to monitor and control the state of the conversion cycle, see Figure 8. In order to select the internal serial clock timing mode, the serial clock pin (SCK) must be floating (Hi-Z) or pulled HIGH prior to the falling edge of CS. The device will not enter the internal serial clock mode if SCK is driven LOW on the falling edge of CS. An internal weak pull-up resistor is active on the SCK pin during the falling edge of CS; therefore, the internal serial clock timing mode is automatically selected if SCK is not externally driven.
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APPLICATIO S I FOR ATIO
ANALOG INPUT RANGE -0.5VREF TO 0.5VREF
CS
BIT 23 SDO EOC
SCK (EXTERNAL) CONVERSION DATA OUTPUT CONVERSION
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Figure 7. External Serial Clock, CS = 0 Operation
2.7V TO 5.5V 1F VCC LTC2430/ LTC2431 REFERENCE VOLTAGE 0.1V TO VCC ANALOG INPUT RANGE -0.5VREF TO 0.5VREF REF + REF - IN + IN - GND SDO CS SCK 3-WIRE SPI INTERFACE FO
VCC
BIT 23 EOC
BIT 22
SCK (INTERNAL) CONVERSION SLEEP DATA OUTPUT SLEEP TEST EOC (OPTIONAL) CONVERSION
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Figure 8. Internal Serial Clock, Single Cycle Operation
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2.7V TO 5.5V 1F VCC LTC2430/ LTC2431 REFERENCE VOLTAGE 0.1V TO VCC REF + REF - IN + IN - GND SDO CS SCK 2-WIRE I/O FO
VCC
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= 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION
BIT 22
BIT 21 SIG
BIT 20 MSB
BIT 19
BIT 18
BIT 0 LSB
VCC = 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION
10k
BIT 21 SIG
BIT 20 MSB
BIT 19
BIT 18
BIT 0 LSB
Hi-Z
Hi-Z
LTC2430/LTC2431
APPLICATIO S I FOR ATIO
The serial data output pin (SDO) is Hi-Z as long as CS is HIGH. At any time during the conversion cycle, CS may be pulled LOW in order to monitor the state of the converter. Once CS is pulled LOW, SCK goes LOW and EOC is output to the SDO pin. EOC = 1 while a conversion is in progress and EOC = 0 if the device is in the sleep state. When testing EOC, if the conversion is complete (EOC = 0), the device will exit the sleep state and enter the data output state if CS remains LOW. In order to allow the device to return to the low power sleep state, CS must be pulled HIGH before the first rising edge of SCK. In the internal SCK timing mode, SCK goes HIGH and the device begins outputting data at time tEOCtest after the falling edge of CS (if EOC = 0) or tEOCtest after EOC goes LOW (if CS is LOW during the falling edge of EOC). The value of tEOCtest is 23s if the device is using its internal oscillator (FO = logic LOW or HIGH). If FO is driven by an external oscillator of frequency fEOSC, then tEOCtest is 3.6/fEOSC. If CS is pulled HIGH before time tEOCtest, the device returns to the sleep state. The conversion result is held in the internal static shift register.
2.7V TO 5.5V 1F VCC
REFERENCE VOLTAGE 0.1V TO VCC ANALOG INPUT RANGE -0.5VREF TO 0.5VREF
> tEOCtest CS TEST EOC
BIT 0 SDO Hi-Z EOC Hi-Z
BIT 23 EOC Hi-Z Hi-Z
SCK (INTERNAL) SLEEP DATA OUTPUT CONVERSION SLEEP SLEEP TEST EOC (OPTIONAL) DATA OUTPUT CONVERSION
2431 F09
Figure 9. Internal Serial Clock, Reduced Data Output Length
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If CS remains LOW longer than tEOCtest, the first rising edge of SCK will occur and the conversion result is serially shifted out of the SDO pin. The data output cycle begins on this first rising edge of SCK and concludes after the 24th rising edge. Data is shifted out the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result on the 24th rising edge of SCK. After the 24th rising edge, SDO goes HIGH (EOC = 1), SCK stays HIGH and a new conversion starts. Typically, CS remains LOW during the data output state. However, the data output state may be aborted by pulling CS HIGH anytime between the first and 24th rising edge of SCK, see Figure 9. On the rising edge of CS, the device aborts the data output state and immediately initiates a new conversion. This is useful for systems not requiring all 24 bits of output data, aborting an invalid conversion cycle, or synchronizing the start of a conversion. If CS is pulled HIGH while the converter is driving SCK LOW, the
VCC
VCC
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FO
LTC2430/ LTC2431 REF + REF - IN + IN - GND SDO CS SCK
= 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION
10k
3-WIRE SPI INTERFACE
BIT 22
BIT 21 SIG
BIT 20 MSB
BIT 19
BIT 18
BIT 8
TEST EOC
Hi-Z
19
LTC2430/LTC2431
APPLICATIO S I FOR ATIO
internal pull-up is not available to restore SCK to a logic HIGH state. This will cause the device to exit the internal serial clock mode on the next falling edge of CS. This can be avoided by adding an external 10k pull-up resistor to the SCK pin or by never pulling CS HIGH when SCK is LOW. Whenever SCK is LOW, the LTC2430/LTC2431's internal pull-up at pin SCK is disabled. Normally, SCK is not externally driven if the device is in the internal SCK timing mode. However, certain applications may require an external driver on SCK. If this driver goes Hi-Z after outputting a LOW signal, the LTC2430/LTC2431's internal pull-up remains disabled. Hence, SCK remains LOW. On the next falling edge of CS, the device is switched to the external SCK timing mode. By adding an external 10k pull-up resistor to SCK, this pin goes HIGH once the external driver goes Hi-Z. On the next CS falling edge, the device will remain in the internal SCK timing mode. A similar situation may occur during the sleep state when CS is pulsed HIGH-LOW-HIGH in order to test the conversion status. If the device is in the sleep state (EOC = 0), SCK will go LOW. Once CS goes HIGH (within the time period defined above as tEOCtest), the internal pull-up is activated. For a heavy capacitive load on the SCK pin, the internal pull-up may not be adequate to return SCK to a
REFERENCE VOLTAGE 0.1V TO VCC ANALOG INPUT RANGE -0.5VREF TO 0.5VREF
CS
SDO
BIT 23 EOC
BIT 22
BIT 21 SIG
SCK (INTERNAL) CONVERSION DATA OUTPUT CONVERSION
2431 F10
Figure 10. Internal Serial Clock, CS = 0 Continuous Operation
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HIGH level before CS goes low again. This is not a concern under normal conditions where CS remains LOW after detecting EOC = 0. This situation is easily overcome by adding an external 10k pull-up resistor to the SCK pin. Internal Serial Clock, 2-Wire I/O, Continuous Conversion This timing mode uses a 2-wire, all output (SCK and SDO) interface. The conversion result is shifted out of the device by an internally generated serial clock (SCK) signal, see Figure 10. CS may be permanently tied to ground, simplifying the user interface or isolation barrier. The internal serial clock mode is selected at the end of the power-on reset (POR) cycle. The POR cycle is concluded approximately 1ms after VCC exceeds 2V. An internal weak pull-up is active during the POR cycle; therefore, the internal serial clock timing mode is automatically selected if SCK is not externally driven LOW (if SCK is loaded such that the internal pull-up cannot pull the pin HIGH, the external SCK mode will be selected). During the conversion, the SCK and the serial data output pin (SDO) are HIGH (EOC = 1). Once the conversion is complete, SCK and SDO go LOW (EOC = 0) indicating the conversion has finished and the device has entered the
2.7V TO 5.5V 1F VCC LTC2430/ LTC2431 REF + REF - IN + IN - GND SDO CS SCK 2-WIRE I/O FO
VCC
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= 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION
BIT 20 MSB
BIT 19
BIT 18
BIT 0 LSB
LTC2430/LTC2431
APPLICATIO S I FOR ATIO
low power sleep state. The part remains in the sleep state a minimum amount of time (1/2 the internal SCK period) then immediately begins outputting data. The data output cycle begins on the first rising edge of SCK and ends after the 24th rising edge. Data is shifted out the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result can be latched on the 24th rising edge of SCK. After the 24th rising edge, SDO goes HIGH (EOC = 1) indicating a new conversion is in progress. SCK remains HIGH during the conversion. PRESERVING THE CONVERTER ACCURACY The LTC2430/LTC2431 are designed to reduce as much as possible the conversion result sensitivity to device decoupling, PCB layout, antialiasing circuits, line frequency perturbations and so on. Nevertheless, in order to preserve the extreme accuracy capability of this part, some simple precautions are desirable. Digital Signal Levels The LTC2430/LTC2431's digital interface is easy to use. The digital inputs (FO, CS and SCK in External SCK mode of operation) accept standard TTL/CMOS logic levels and the internal hysteresis receivers can tolerate edge rates as slow as 100s. However, some considerations are required to take advantage of the exceptional accuracy and low supply current of this converter. The digital output signals (SDO and SCK in Internal SCK mode of operation) are less of a concern because they are not generally active during the conversion state. While a digital input signal is in the range 0.5V to (VCC - 0.5V), the CMOS input receiver draws additional current from the power supply. It should be noted that, when any one of the digital input signals (FO, CS and SCK in External SCK mode of operation) is within this range, the LTC2430/LTC2431 power supply current may increase even if the signal in question is at a valid logic level. For micropower operation, it is recommended to drive all digital input signals to full CMOS levels [VIL < 0.4V and VOH > (VCC - 0.4V)].
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During the conversion period, the undershoot and/or overshoot of a fast digital signal connected to the LTC2430/ LTC2431 pins may severely disturb the analog to digital conversion process. Undershoot and overshoot can occur because of the impedance mismatch at the converter pin when the transition time of an external control signal is less than twice the propagation delay from the driver to LTC2430/LTC2431. For reference, on a regular FR-4 board, signal propagation velocity is approximately 183ps/inch for internal traces and 170ps/inch for surface traces. Thus, a driver generating a control signal with a minimum transition time of 1ns must be connected to the converter pin through a trace shorter than 2.5 inches. This problem becomes particularly difficult when shared control lines are used and multiple reflections may occur. The solution is to carefully terminate all transmission lines close to their characteristic impedance. Parallel termination near the LTC2430/LTC2431 pin will eliminate this problem but will increase the driver power dissipation. A series resistor between 27 and 56 placed near the driver or near the LTC2431 pin will also eliminate this problem without additional power dissipation. The actual resistor value depends upon the trace impedance and connection topology. An alternate solution is to reduce the edge rate of the control signals. It should be noted that using very slow edges will increase the converter power supply current during the transition time. The differential input and reference architecture reduce substantially the converter's sensitivity to ground currents. Particular attention must be given to the connection of the FO signal when the converter (LTC2430 or LTC2431) is used with an external conversion clock. This clock is active during the conversion time and the normal mode rejection provided by the internal digital filter is not very high at this frequency. A normal mode signal of this frequency at the converter reference terminals may result into DC gain and INL errors. A normal mode signal of this frequency at the converter input terminals may result into a DC offset error. Such perturbations may occur due to asymmetric capacitive coupling between the FO signal trace and the converter input and/or reference connection traces. An immediate solution is to maintain maximum possible separation
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LTC2430/LTC2431
APPLICATIO S I FOR ATIO
between the FO signal trace and the input/reference signals. When the FO signal is parallel terminated near the converter, substantial AC current is flowing in the loop formed by the FO connection trace, the termination and the ground return path. Thus, perturbation signals may be inductively coupled into the converter input and/or reference. In this situation, the user must reduce to a minimum the loop area for the FO signal as well as the loop area for the differential input and reference connections. Driving the Input and Reference The input and reference pins of the converter (LTC2430 or LTC2431) are directly connected to a network of sampling capacitors. Depending upon the relation between the differential input voltage and the differential reference voltage, these capacitors are switching between these four pins transfering small amounts of charge in the process. A simplified equivalent circuit is shown in Figure 11. For a simple approximation, the source impedance RS driving an analog input pin (IN+, IN-, REF+ or REF-) can be considered to form, together with RSW and CEQ (see Figure 11), a first order passive network with a time constant = (RS + RSW) * CEQ. The converter is able to
IREF+ VREF+ ILEAK IIN+ VIN+ ILEAK IIN - VIN - ILEAK IREF - VREF - ILEAK VCC ILEAK RSW (TYP) 20k
2431 F11
VCC ILEAK RSW (TYP) 20k
VCC ILEAK RSW (TYP) 20k CEQ 6pF (TYP) RSW (TYP) 20k
VCC ILEAK
SWITCHING FREQUENCY fSW = 76800Hz INTERNAL OSCILLATOR (FO = LOW OR HIGH) fSW = 0.5 * fEOSC EXTERNAL OSCILLATOR
Figure 11. LTC2430/LTC2431 Equivalent Analog Input Circuit
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sample the input signal with better than 1ppm accuracy if the sampling period is at least 14 times greater than the input circuit time constant . The sampling process on the four input analog pins is quasi-independent so each time constant should be considered by itself and, under worstcase circumstances, the errors may add. When using the internal oscillator (FO = LOW or HIGH), the LTC2430/LTC2431's front-end switched-capacitor network is clocked at 76800Hz corresponding to a 13s sampling period. Thus, for settling errors of less than 1ppm, the driving source impedance should be chosen such that 13s/14 = 920ns. When an external oscillator of frequency fEOSC is used, the sampling period is 2/fEOSC and, for a settling error of less than 1ppm, 0.14/fEOSC. Input Current If complete settling occurs on the input, conversion results will be unaffected by the dynamic input current. An incomplete settling of the input signal sampling process may result in gain and offset errors, but it will not degrade the INL performance of the converter. Figure 11 shows the mathematical expressions for the average bias currents flowing through the IN + and IN - pins as a result of the
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() I(IN )
I IN+
-
AVG
AVG
VIN + VINCM - VREFCM 0.5 * REQ - V + VINCM - VREFCM = IN 0.5 * REQ = = =
2 VIN 1.5 * VREF - VINCM + VREFCM - VREF * REQ 0.5 * REQ 2 VIN -1.5 * VREF - VINCM + VREFCM + VREF * REQ 0.5 * REQ
I REF +
()
AVG
I REF -
()
AVG
WHERE: VREF = REF + - REF - REF + + REF - VREFCM = 2 VIN = IN+ - IN- IN+ - IN- VINCM = 2
REQ = 43.2M INTERNAL OSCILLATOR 60Hz Notch FO = LOW
REQ = 52.0M INTERNAL OSCILLATOR 50Hz Notch FO = HIGH REQ = 6.66 * 1012 / f EOSC EXTERNAL OSCILLATOR
(
)
( (
) )
LTC2430/LTC2431
APPLICATIO S I FOR ATIO
sampling charge transfers when integrated over a substantial time period (longer than 64 internal clock cycles). The effect of this input dynamic current can be analyzed using the test circuit of Figure 12. The CPAR capacitor includes the LTC2430/LTC2431 pin capacitance (5pF typical) plus the capacitance of the test fixture used to obtain the results shown in Figures 13 and 14. A careful implementation can bring the total input capacitance (CIN + CPAR) closer to 5pF thus achieving better performance than the one predicted by Figures 13 and 14. For simplicity, two distinct situations can be considered. For relatively small values of input capacitance (C IN < 0.01F), the voltage on the sampling capacitor settles almost completely and relatively large values for the source impedance result in only small errors. Such values for CIN will deteriorate the converter offset and gain performance without significant benefits of signal filtering and the user is advised to avoid them. Nevertheless, when small values of CIN are unavoidably present as parasitics of input multiplexers, wires, connectors or sensors, the LTC2430 or LTC2431 can maintain its exceptional accuracy while operating with relative large values of source resistance as shown in Figures 13 and 14. These measured results may be slightly different from the first order approximation suggested earlier because they include the effect of the actual second order input network together with the nonlinear settling process of the input amplifiers. For small CIN values, the settling on IN+ and IN - occurs almost independently and there is little benefit in trying to match the source impedance for the two pins. Larger values of input capacitors (CIN > 0.01F) may be required in certain configurations for antialiasing or general input signal filtering. Such capacitors will average the input sampling charge and the external source resistance will see a quasi constant input differential impedance. When FO = LOW (internal oscillator and 60Hz notch), the typical differential input resistance is 21.6M which will generate a gain error of approximately 0.023ppm for each ohm of source resistance driving IN+ or IN -. When FO = HIGH (internal oscillator and 50Hz notch), the typical differential input resistance is 26M which will generate a gain error of approximately 0.019ppm for each ohm of source resistance driving IN+ or IN -. When FO is driven by
+FS ERROR (ppm)
-FS ERROR (ppm)
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an external oscillator with a frequency fEOSC (external conversion clock operation), the typical differential input resistance is 3.3 * 1012/fEOSC and each ohm of source resistance driving IN+ or IN - will result in 0.15 * 10-6 * fEOSCppm gain error. The effect of the source resistance on the two input pins is additive with respect to this gain error.
RSOURCE CPAR 20pF IN + CIN VINCM + 0.5VIN LTC2430/ LTC2431 IN - CIN CPAR 20pF
2431 F12
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RSOURCE
VINCM - 0.5VIN
Figure 12. An RC Network at IN + and IN -
50 40 30 20 10 0 CIN = 0pF -10 1 10 100 1k RSOURCE () 10k 100k
2431 F13
VCC = 5V VREF + = 5V VREF - = GND VIN + = 3.75V CIN = 0.01F VIN - = 1.25V FO = GND TA = 25C CIN = 0.001F CIN = 100pF
Figure 13. +FS Error vs RSOURCE
10 0 -10 -20 -30 -40 -50 1 VCC = 5V VREF + = 5V VREF - = GND VIN + = 1.25V VIN - = 3.75V FO = GND TA = 25C 10 CIN = 100pF CIN = 0.01F CIN = 0.001F
at IN +
or IN - (Small CIN)
CIN = 0pF
100 1k RSOURCE ()
10k
100k
2431 F14
Figure 14. -FS Error vs RSOURCE at IN + or IN - (Small CIN)
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APPLICATIO S I FOR ATIO
The typical +FS and -FS errors as a function of the sum of the source resistance seen by IN+ and IN- for large values of CIN are shown in Figure 15. In addition to this gain error, an offset error term may also appear. The offset error is proportional with the mismatch between the source impedance driving the two input pins IN+ and IN- and with the difference between the input and reference common mode voltages. While the input drive circuit nonzero source impedance combined with the converter average input current will not degrade the INL performance, indirect distortion may result from the modulation of the offset error by the common mode component of the input signal. Thus, when using large CIN capacitor values, it is advisable to carefully match the source impedance seen by the IN+ and IN- pins. When FO = LOW
20 VCC = 5V VREF + = 5V VREF - = GND VIN + = 3.75V VIN - = 1.25V FO = GND TA = 25C
15
+FS ERROR (ppm)
CIN = 1F, 10F
10 CIN = 0.1F 5 CIN = 0.01F 0
0 100 200 300 400 500 600 700 800 900 1000 RSOURCE ()
2431 F15a
Figure 15a. + FS Error vs RSOURCE
0
at IN +
or IN -
(Large CIN)
OFFSET ERROR (ppm)
CIN = 0.01F -5
-FS ERROR (ppm)
CIN = 1F, 10F -10 VCC = 5V VREF + = 5V VREF - = GND VIN + = 1.25V VIN - = 3.75V FO = GND TA = 25C
CIN = 0.1F
-15
-20
0 100 200 300 400 500 600 700 800 900 1000 RSOURCE ()
2431 F15b
Figure 15b. - FS Error vs RSOURCE at IN + or IN - (Large CIN)
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(internal oscillator and 60Hz notch), every 1 mismatch in source impedance transforms a full-scale common mode input signal into a differential mode input signal of 0.023ppm. When FO = HIGH (internal oscillator and 50Hz notch), every 1 mismatch in source impedance transforms a full-scale common mode input signal into a differential mode input signal of 0.019ppm. When FO is driven by an external oscillator with a frequency fEOSC, every 1 mismatch in source impedance transforms a full-scale common mode input signal into a differential mode input signal of 0.15 * 10-6 * fEOSCppm. Figure 16 shows the typical offset error due to input common mode voltage for various values of source resistance imbalance between the IN+ and IN- pins when large CIN values are used. If possible, it is desirable to operate with the input signal common mode voltage very close to the reference signal common mode voltage as is the case in the ratiometric measurement of a symmetric bridge. This configuration eliminates the offset error caused by mismatched source impedances. The magnitude of the dynamic input current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. The accuracy of the internal clock over the entire temperature and power supply range is typically better than 1%. Such
40 A 20 B C D E F -20 G FO = GND RSOURCEIN - = 500 CIN = 10F TA = 25C 2 2.5 3 3.5 VINCM (V) 4 4.5 5 VCC = 5V VREF + = 5V VREF - = GND VIN+ = VIN- = VINCM 0 -40 0 0.5 1 1.5 A: RIN = +1k B: RIN = +500 C: RIN = +200 D: RIN = 0 E: RIN = -200 F: RIN = -500 G: RIN = -1k
2431 F16
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Figure 16. Offset Error vs Common Mode Voltage (VINCM = VIN+ = VIN-) and Input Source Resistance Imbalance (RIN = RSOURCEIN+ - RSOURCEIN-) for Large CIN Values (CIN 1F)
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APPLICATIO S I FOR ATIO
a specification can also be easily achieved by an external clock. When relatively stable resistors (50ppm/C) are used for the external source impedance seen by IN+ and IN-, the expected drift of the dynamic current, offset and gain errors will be insignificant (about 1% of their respective values over the entire temperature and voltage range). Even for the most stringent applications, a one-time calibration operation may be sufficient. In addition to the input sampling charge, the input ESD protection diodes have a temperature dependent leakage current. This current, nominally 1nA (10nA max), results in a small offset shift. A 100 source resistance will create a 0.1V typical and 1V maximum offset voltage. Reference Current In a similar fashion, the LTC2430 or LTC2431 samples the differential reference pins REF+ and REF- transfering small amount of charge to and from the external driving circuits thus producing a dynamic reference current. This current does not change the converter offset, but it may degrade the gain and INL performance. The effect of this current can be analyzed in the same two distinct situations. For relatively small values of the external reference capacitors (CREF < 0.01F), the voltage on the sampling capacitor settles almost completely and relatively large values for the source impedance result in only small errors. Such values for CREF will deteriorate the converter offset and gain performance without significant benefits of reference filtering and the user is advised to avoid them. Larger values of reference capacitors (CREF > 0.01F) may be required as reference filters in certain configurations. Such capacitors will average the reference sampling charge and the external source resistance will see a quasi constant reference differential impedance. When FO = LOW (internal oscillator and 60Hz notch), the typical differential reference resistance is 15.6M which will generate a gain error of approximately 0.032ppm for each ohm of source resistance driving REF+ or REF-. When FO = HIGH (internal oscillator and 50Hz notch), the typical differential reference resistance is 18.7M which will generate a gain error of approximately 0.027ppm for each ohm of source resistance driving REF+ or REF -. When FO is driven by an external oscillator with a frequency fEOSC
+FS ERROR (ppm)
-FS ERROR (ppm)
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(external conversion clock operation), the typical differential reference resistance is 2.4 * 1012/fEOSC and each ohm of source resistance drving REF+ or REF- will result in 0.206 * 10-6 * fEOSCppm gain error. The effect of the source resistance on the two reference pins is additive with respect to this gain error. The typical FS errors for various combinations of source resistance seen by the REF+ and REF- pins and external capacitance CREF connected to these pins are shown in Figures 17 and 18. Typical - FS errors are similar to + FS errors with opposite polarity. In addition to this gain error, the converter INL performance is degraded by the reference source impedance. When FO = LOW (internal oscillator and 60Hz notch), every 100 of source resistance driving REF+ or REF- translates
10 CREF = 0pF 0 -10 -20 -30 -40 -50 1 VCC = 5V CREF = 100pF VREF + = 5V VREF - = GND VIN + = 3.75V VIN - = 1.25V FO = GND TA = 25C 10 100 1k RSOURCE () 10k 100k
2431 F17a
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CREF = 0.01F CREF = 0.001F
Figure 17a. +FS Error vs RSOURCE at REF+ or REF- (Small CIN)
50 40 30 20 CREF = 100pF 10 0 CREF = 0pF -10 1 10 100 1k RSOURCE () 10k 100k
2431 F17b
VCC = 5V VREF + = 5V VREF - = GND VIN + = 1.25V C = 0.01F VIN - = 3.75V REF FO = GND TA = 25C CREF = 0.001F
Figure 17b. - FS Error vs RSOURCE at REF+ or REF- (Small CIN)
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APPLICATIO S I FOR ATIO
0 CREF = 0.01F -10 -20 CREF = 1F, 10F -30 -40 -50 -60 VCC = 5V VREF + = 5V VREF - = GND VIN + = 3.75V VIN - = 1.25V FO = GND TA = 25C 0 100 200 300 400 500 600 700 800 900 1000 RSOURCE ()
2431 F18a
CREF = 0.1F
INL (ppm OF VREF)
+FS ERROR (ppm)
Figure 18a. +FS Error vs RSOURCE at REF+ or REF- (Large CREF)
60 50
-FS ERROR (ppm)
40 30
VCC = 5V VREF + = 5V VREF - = GND VIN + = 1.25V VIN - = 3.75V FO = GND TA = 25C
CREF = 1F, 10F
CREF = 0.1F 20 10 CREF = 0.01F 0 0 100 200 300 400 500 600 700 800 900 1000 RSOURCE ()
2431 F18b
Figure 18b. - FS Error vs RSOURCE at REF+ or REF- (Large CREF)
into about 0.11ppm additional INL error. When FO = HIGH (internal oscillator and 50Hz notch), every 100 of source resistance driving REF+ or REF- translates into about 0.092ppm additional INL error. When FO is driven by an external oscillator with a frequency fEOSC, every 100 of source resistance driving REF+ or REF- translates into about 0.73 * 10-6 * fEOSCppm additional INL error. Figure 19 shows the typical INL error due to the source resistance driving the REF+ or REF- pins when large CREF values are used. The effect of the source resistance on the two reference pins is additive with respect to this INL error. In general, matching of source impedance for the REF+
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15 12 9 6 3 0 -3 -6 -9 -12 RSOURCE = 1k RSOURCE = 5k RSOURCE = 10k -15 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 VINDIF/VREFDIF FO = GND VCC = 5V VREF + = 5V CREF = 10F - = GND VREF TA = 25C VINCM = 0.5(VIN+ + VIN-) = 2.5V
2431 F19
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Figure 19. INL vs Differential Input Voltage (VIN = IN + - IN -) and Reference Source Resistance (RSOURCE at REF + and REF -) for Large CREF Values (CREF 1F)
and REF- pins does not help the gain or the INL error. The user is thus advised to minimize the combined source impedance driving the REF+ and REF- pins rather than to try to match it. The magnitude of the dynamic reference current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. The accuracy of the internal clock over the entire temperature and power supply range is typical better than 1%. Such a specification can also be easily achieved by an external clock. When relatively stable resistors (50ppm/C) are used for the external source impedance seen by REF+ and REF-, the expected drift of the dynamic current gain error will be insignificant (about 1% of its value over the entire temperature and voltage range). Even for the most stringent applications, a one-time calibration operation may be sufficient. In addition to the reference sampling charge, the reference pins ESD protection diodes have a temperature dependent leakage current. This leakage current, nominally 1nA (10nA max), results in a small gain error. A 100 source resistance will create a 0.05V typical and 0.5V maximum full-scale error.
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APPLICATIO S I FOR ATIO
Output Data Rate
When using the internal oscillator, the LTC2430/LTC2431 can produce up to 7.5 readings per second with a notch frequency of 60Hz (FO = LOW) and 6.25 readings per second with a notch frequency of 50Hz (FO = HIGH). The actual output data rate will depend upon the length of the sleep and data output phases which are controlled by the user and which can be made insignificantly short. When operated with an external conversion clock (FO connected to an external oscillator), the LTC2430/LTC2431 output data rate can be increased as desired. The duration of the conversion phase is 20510/fEOSC. If fEOSC = 153600Hz, the converter behaves as if the internal oscillator is used and the notch is set at 60Hz. There is no significant difference in the LTC2430/LTC2431 performance between these two operation modes. An increase in fEOSC over the nominal 153600Hz will translate into a proportional increase in the maximum output data rate. This substantial advantage is nevertheless accompanied by three potential effects, which must be carefully considered. First, a change in fEOSC will result in a proportional change in the internal notch position and in a reduction of the converter differential mode rejection at the power line frequency. In many applications, the subsequent performance degradation can be substantially reduced by relying upon the LTC2430/LTC2431's exceptional common mode rejection and by carefully eliminating common mode to differential mode conversion sources in the input circuit. The user should avoid single-ended input filters and should maintain a very high degree of matching and symmetry in the circuits driving the IN+ and IN- pins. Second, the increase in clock frequency will increase proportionally the amount of sampling charge transferred through the input and the reference pins. If large external input and/or reference capacitors (CIN, CREF) are used, the previous section provides formulae for evaluating the effect of the source resistance upon the converter performance for any value of fEOSC. If small external input and/ or reference capacitors (CIN, CREF) are used, the effect of the external source resistance upon the LTC2430/LTC2431 typical performance can be inferred from Figures 13, 14
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and 17 in which the horizontal axis is scaled by 153600/fEOSC. Third, an increase in the frequency of the external oscillator above 1.6MHz (a more than 10x increase in the output data rate) will start to decrease the effectiveness of the internal autocalibration circuits. This will result in a progressive degradation in the converter accuracy and linearity. Typical measured performance curves for output data rates up to 100 readings per second are shown in Figures 20 to 27. In order to obtain the highest possible level of accuracy from this converter at output data rates above 50 readings per second, the user is advised to maximize the power supply voltage used and to limit the maximum ambient operating temperature. The accuracy is also sensitive to the clock signal levels and edge rate as discussed in the section Digital Signal Levels. In certain circumstances, a reduction of the differential reference voltage may be beneficial. Input Bandwidth The combined effect of the internal sinc4 digital filter and of the analog and digital autocalibration circuits determines the LTC2430/LTC2431 input bandwidth. When the internal oscillator is used, the 3dB input bandwidth of the LTC2430/LTC2431 is 3.63Hz for 60Hz notch frequency (FO = LOW) and 3.02Hz for 50Hz notch frequency (FO = HIGH). If an external conversion clock generator of frequency fEOSC is connected to the FO pin, the 3dB input bandwidth is 2.36 * 10-5 * fEOSC. Due to the complex filtering and calibration algorithms utilized, the converter input bandwidth is not modeled very accurately by a first order filter with the pole located at the 3dB frequency. When the internal oscillator is used, the shape of the LTC2430/LTC2431 input bandwidth is shown in Figure 28. When an external oscillator of frequency fEOSC is used, the shape of the LTC2430/LTC2431 input bandwidth can be derived from Figure 28, FO = LOW curve of the LTC2411 in which the horizontal axis is scaled by fEOSC/153600. The conversion noise (2.8VRMS typical for VREF = 5V) can be modeled as a white noise source connected to a noise free converter. The noise spectral density is 67nV/Hz for
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27
LTC2430/LTC2431
APPLICATIO S I FOR ATIO
10 9 OFFSET ERROR (ppm OF VREF) 8 7 6 5 4 3 2 1 0 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
2431 F20
+FS ERROR (ppm OF VREF)
VINCM = VREFCM VCC = VREF = 5V VIN = 0V FO = EXT OSC
TA = 85C TA = 25C
Figure 20. Offset Error vs Output Data Rate and Temperature
30
VINCM = VREFCM V = VREF = 5V 25 F CC EXT OSC O= RESOLUTION (BITS) 20
-FS ERROR (ppm OF VREF)
15 10 5 TA = 25C 0 TA = 85C -5 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
2431 F22
Figure 22. - FS Error vs Output Data Rate and Temperature
22 OFFSET ERROR (ppm OF VREF) 21 RESOLUTION (BITS) 20 TA = 25C 19 18 TA = 85C
17 VINCM = VREFCM VCC = VREF = 5V F = EXT OSC 16 O - REF = GND RES = LOG2(VREF/INLMAX) 15 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
2430 F24
Figure 24. Resolution (INLRMS 1LSB) vs Output Data Rate and Temperature
28
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5 0 -5 -10 -15 -20 -25 -30 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
2431 F21
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TA = 25C TA = 85C
VINCM = VREFCM VCC = VREF = 5V FO = EXT OSC
Figure 21. + FS Error vs Output Data Rate and Temperature
22 21 20 19 18 VINCM = VREFCM VCC = VREF = 5V VIN = 0V FO = EXT OSC 16 REF - = GND RES = LOG2 (VREF/NOISERMS) 15 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 17
2431 F23
TA = 25C TA = 85C
Figure 23. Resolution (NoiseRMS 1LSB) vs Output Data Rate and Temperature
5 4 3 2 1 0 -1 -2 -3 -4 -5 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
2431 F25
VINCM = VREFCM VIN = 0V REF - = GND FO = EXT OSC TA = 25C VCC = VREF = 5V VCC = 2.7V VREF = 2.5V
Figure 25. Offset Error vs Output Data Rate and VCC
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APPLICATIO S I FOR ATIO
22 21 RESOLUTION (BITS) 20 19 18 VINCM = VREFCM 17 VIN = 0V FO = EXT OSC REF - = GND 16 TA = 25C RES = LOG2(VREF/NOISERMS) 15 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
2430 F26
VCC = VREF = 5V
RESOLUTION (BITS)
VCC = 2.7V VREF = 2.5V
Figure 26. Resolution (NoiseRMS 1LSB) vs Output Data Rate and VCC
0
INPUT SIGNAL ATTENUATION (dB)
INPUT REFERRED NOISE EQUIVALENT BANDWIDTH (Hz)
-1 -2 -3 -4 -5 -6 FO = HIGH FO = LOW
1 3 4 0 5 2 DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2431 F28
Figure 28. Input Signal Bandwidth Using the Internal Oscillator
an infinite bandwidth source and 216nV/Hz for a single 0.5MHz pole source. From these numbers, it is clear that particular attention must be given to the design of external amplification circuits. Such circuits face the simultaneous requirements of very low bandwidth (just a few Hz) in order to reduce the output referred noise and relatively high bandwidth (at least 500kHz) necessary to drive the input switched-capacitor network. A possible solution is a high gain, low bandwidth amplifier stage followed by a high bandwidth unity-gain buffer. When external amplifiers are driving the LTC2430/ LTC2431, the ADC input referred system noise calculation can be simplified by Figure 29. The noise of an amplifier driving the LTC2430/LTC2431 input pin can be modeled as a band-limited white noise source. Its bandwidth can be
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22 21 20 19 VCC = 2.7V VINCM = VREFCM VREF = 2.5V VIN = 0V 17 FO = EXT OSC REF - = GND 16 TA = 25C RES = LOG2(VREF/INLMAX) 15 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
2430 F27
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VCC = VREF = 5V
18
Figure 27. Resolution (INLMAX 1LSB) vs Output Data Rate and VCC
1000
100
10
FO = LOW FO = HIGH
1
0.1 0.1 10 100 1k 10k 100k 1 INPUT NOISE SOURCE SINGLE POLE EQUIVALENT BANDWIDTH (Hz) 1M
2431 G29
Figure 29. Input Referred Noise Equivalent Bandwidth of an Input Connected White Noise Source
approximated by the bandwidth of a single pole lowpass filter with a corner frequency fi. The amplifier noise spectral density is ni. From Figure 29, using fi as the x-axis selector, we can find on the y-axis the noise equivalent bandwidth freqi of the input driving amplifier. This bandwidth includes the band limiting effects of the ADC internal calibration and filtering. The noise of the driving amplifier referred to the converter input and including all these effects can be calculated as N = ni * freqi. The total system noise (referred to the LTC2430/LTC2431 input) can now be obtained by summing as square root of sum of squares the three ADC input referred noise sources: the LTC2430/ LTC2431 internal noise (2.8V), the noise of the IN + driving amplifier and the noise of the IN - driving amplifier.
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LTC2430/LTC2431
APPLICATIO S I FOR ATIO
If the FO pin is driven by an external oscillator of frequency fEOSC, Figure 29 can still be used for noise calculation if the x-axis is scaled by fEOSC/153600. For large values of the ratio fEOSC/153600, the Figure 29 plot accuracy begins to decrease, but in the same time the LTC2430/LTC2431 noise floor rises and the noise contribution of the driving amplifiers lose significance. Normal Mode Rejection and Antialiasing One of the advantages delta-sigma ADCs offer over conventional ADCs is on-chip digital filtering. Combined with a large oversampling ratio, the LTC2430/LTC2431 significantly simplifies antialiasing filter requirements. The sinc4 digital filter provides greater than 120dB normal mode rejection at all frequencies except DC and integer multiples of the modulator sampling frequency (fS). The LTC2430/LTC2431's autocalibration circuits further simplify the antialiasing requirements by additional normal mode signal filtering both in the analog and digital domain. Independent of the operating mode, fS = 256 * fN = 2048 * fOUTMAX where fN is the notch frequency and fOUTMAX is the maximum output data rate. In the internal oscillator mode, fS = 12,800Hz with a 50Hz notch setting and fS = 15,360Hz with a 60Hz notch setting. In the external oscillator mode, fS = fEOSC/10. The combined normal mode rejection performance is shown in Figure 30 for the internal oscillator with 50Hz notch setting (FO = HIGH) and in Figure 31 for the internal
0
INPUT NORMAL MODE REJECTION (dB)
-20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS11fS12fS DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2431 F30
INPUT NORMAL MODE REJECTION (dB)
-10
FO = HIGH
Figure 30. Input Normal Mode Rejection, Internal Oscillator and 50Hz Notch
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oscillator with FO = LOW and for the external oscillator mode. The regions of low rejection occurring at integer multiples of fS have a very narrow bandwidth. Magnified details of the normal mode rejection curves are shown in Figure 32 (rejection near DC) and Figure 33 (rejection at fS = 256fN) where fN represents the notch frequency. These curves have been derived for the external oscillator mode but they can be used in all operating modes by appropriately selecting the fN value. The user can expect to achieve in practice this level of performance using the internal oscillator as it is demonstrated by Figures 34 to 36. Typical measured values of the normal mode rejection of the LTC2430/LTC2431 operating with an internal oscillator and a 60Hz notch setting are shown in Figure 34 superimposed over the theoretical calculated curve. Similarly, typical measured values of the normal mode rejection of the LTC2430/LTC2431 operating with an internal oscillator and a 50Hz notch setting are shown in Figure 35 superimposed over the theoretical calculated curve. As a result of these remarkable normal mode specifications, minimal (if any) antialias filtering is required in front of the LTC2430/LTC2431. If passive RC components are placed in front of the LTC2430/LTC2431, the input dynamic current should be considered (see Input Current section). In cases where large effective RC time constants are used, an external buffer amplifier may be required to minimize the effects of dynamic input current.
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2431 F31
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FO = LOW OR FO = EXTERNAL OSCILLATOR, fEOSC = 10 * fS
Figure 31. Input Normal Mode Rejection, Internal Oscillator and FO = LOW or External Oscillator
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APPLICATIO S I FOR ATIO
0
INPUT NORMAL MODE REJECTION (dB)
-20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 fN 2fN 3fN 4fN 5fN 6fN 7fN INPUT SIGNAL FREQUENCY (Hz) 8fN
INPUT NORMAL MODE REJECTION (dB)
2431 F32
-10
Figure 32. Input Normal Mode Rejection
0 MEASURED DATA CALCULATED DATA VCC = 5V VREF = 5V VINCM = 2.5V VIN(P-P) = 5V FO = GND TA = 25C 0
NORMAL MODE REJECTION (dB)
NORMAL MODE REJECTION (dB)
-20 -40 - 60 -80 -100 -120
0
15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 INPUT FREQUENCY (Hz)
2431 F34
Figure 34. Input Normal Mode Rejection vs Input Frequency
Traditional high order delta-sigma modulators, while providing very good linearity and resolution, suffer from potential instabilities at large input signal levels. The proprietary architecture used for the LTC2430/LTC2431 third order modulator resolves this problem and guarantees a predictable stable behavior at input signal levels of up to 150% of full scale. In many industrial applications, it is not uncommon to have to measure microvolt level signals superimposed over volt level perturbations and LTC2430/LTC2431 are eminently suited for such tasks. When the perturbation is differential, the specification of interest is the normal mode rejection for large input signal levels. With a reference voltage VREF = 5V, the
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0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 250fN 252fN 254fN 256fN 258fN 260fN 262fN INPUT SIGNAL FREQUENCY (Hz)
2431 F33
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Figure 33. Input Normal Mode Rejection
MEASURED DATA CALCULATED DATA VCC = 5V VREF = 5V VINCM = 2.5V VIN(P-P) = 5V FO = 5V TA = 25C
-20 -40 - 60 -80 -100 -120
0
25
50
75 100 125 INPUT FREQUENCY (Hz)
150
175
200
2431 F35
Figure 35. Input Normal Mode Rejection vs Input Frequency
LTC2430/LTC2431 have a full-scale differential input range of 5V peak-to-peak. Figures 36 and 37 show measurement results for the LTC2430/LTC2431 normal mode rejection ratio with a 7.5V peak-to-peak (150% of full scale) input signal superimposed over the more traditional normal mode rejection ratio results obtained with a 5V peakto-peak (full scale) input signal. It is clear that the LTC2430/ LTC2431 rejection performance is maintained with no compromises in this extreme situation. When operating with large input signal levels, the user must observe that such signals do not violate the device absolute maximum ratings.
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LTC2430/LTC2431
APPLICATIO S I FOR ATIO
0 NORMAL MODE REJECTION (dB) -20 -40 - 60 -80 -100 -120 0 VIN(P-P) = 5V VIN(P-P) = 7.5V (150% OF FULL SCALE)
NORMAL MODE REJECTION (dB)
VCC = 5V VREF = 5V VINCM = 2.5V FO = GND TA = 25C
15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 INPUT FREQUENCY (Hz)
2431 F36
Figure 36. Measured Input Normal Mode Rejection vs Input Frequency
BRIDGE APPLICATIONS Typical strain gauge based bridges deliver only 2mV/Volt of excitation. As the maximum reference voltage of the LTC2430/LTC2431 is 5V, remote sensing of applied excitation without additional circuitry requires that excitation be limited to 5V. This gives only 10mV full scale, which can be resolved to 1 part in 3500 without averaging. For many solid state sensors, this is comparable to the sensor. Averaging 128 samples however reduces the noise level by a factor of eight, bringing the resolving power to 1 part in 40000, comparable to better weighing systems. Hysteresis and creep effects in the load cells are typically much greater than this. Most applications that require strain measurements to this level of accuracy are measuring slowly changing phenomena, hence the time required to average a large number of readings is usually not an issue. For those systems that require accurate measurement of a small incremental change on a significant tare weight, the lack of history effects in the LTC2400 family is of great benefit. For those applications that cannot be fulfilled by the LTC2430/LTC2431 alone, compensating for error in external amplification can be done effectively due to the "no latency" feature of the LTC2430/LTC2431. No latency operation allows samples of the amplifier offset and gain to be interleaved with weighing measurements. The use of correlated double sampling allows suppression of 1/f noise, offset and thermocouple effects within the bridge. Correlated double sampling involves alternating
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0 -20 -40 - 60 -80 -100 -120 VIN(P-P) = 5V VIN(P-P) = 7.5V (150% OF FULL SCALE) VCC = 5V VREF = 5V VINCM = 2.5V FO = 5V TA = 25C 0 25 50 75 100 125 INPUT FREQUENCY (Hz) 150 175 200
2431 F37
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Figure 37. Measured Input Normal Mode Rejection vs Input Frequency
the polarity of excitation and dealing with the reversal of input polarity mathematically. Alternatively, bridge excitation can be increased to as much as 10V, if one of several precision attenuation techniques is used to produce a precision divide operation on the reference signal. Another option is the use of a reference within the 5V input range of the LTC2430/LTC2431 and developing excitation via fixed gain, or LTC1043 based voltage multiplication, along with remote feedback in the excitation amplifiers, as shown in Figures 43 and 45. Figure 38 shows an example of a simple bridge connection. Note that it is suitable for any bridge application
+
R1 0.1F VCC SDO SCK CS 10F LT1019 0.1F
REF + 350 BRIDGE REF - IN +
LTC2430/ LTC2431 IN - GND R2 FO
2431 F38
R1 AND R2 CAN BE USED TO INCREASE TOLERABLE AC COMPONENT ON REF SIGNALS
Figure 38. Simple Bridge Connection
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APPLICATIO S I FOR ATIO
where measurement speed is not of the utmost importance. For many applications where large vessels are weighed, the average weight over an extended period of time is of concern and short term weight is not readily determined due to movement of contents, or mechanical resonance. Often, large weighing applications involve load cells located at each load bearing point, the output of which can be summed passively prior to the signal processing circuitry, actively with amplification prior to the ADC, or can be digitized via multiple ADC channels and summed mathematically. The mathematical summation of the output of multiple LTC2430/LTC2431's provide the benefit of a root square reduction in noise. The low power consumption of the LTC2430/LTC2431 make it attractive for multidrop communication schemes where the ADC is located within the load-cell housing. A direct connection to a load cell is perhaps best incorporated into the load-cell body, as minimizing the distance to the sensor largely eliminates the need for protection devices, RFI suppression and wiring. The LTC2430/ LTC2431 exhibit extremely low temperature dependent drift. As a result, exposure to external ambient temperature ranges does not compromise performance. The incorporation of any amplification considerably complicates
5V 3
+ -
8 U1A 1 2 0.1F 5V 8 U2A 1 REF + REF - IN + LTC2430/ LTC2431 U2B 5 7 IN - GND FO VCC SDO SCK CS 0.1F
2 350 BRIDGE
4 15 1 RN1 16 14 4 5 12
6
11 2 6
7
10 3
-
U1B 7
5
+
RN1 = 5k x 8 RESISTOR ARRAY U1A, U1B, U2A, U2B = 1/2 LTC1051
Figure 39. Using Autozero Amplifiers to Reduce Input Referred Noise
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thermal stability, as input offset voltages and currents, temperature coefficient of gain settling resistors all become factors. The circuit in Figure 39 shows an example of a simple amplification scheme. This example produces a differential output with a common mode voltage of 2.5V, as determined by the bridge. The use of a true three amplifier instrumentation amplifier is not necessary, as the LTC2430/ LTC2431 have common mode rejection far beyond that of most amplifiers. The LTC1051 is a dual autozero amplifier that can be used to produce a gain of 10 before its input referred noise dominates the LTC2430/LTC2431 noise. This example shows a gain of 34, that is determined by a feedback network built using a resistor array containing eight individual resistors. The resistors are organized to optimize temperature tracking in the presence of thermal gradients. The second LTC1051 buffers the low noise input stage from the transient load steps produced during conversion. The gain stability and accuracy of this approach is very good, due to a statistical improvement in resistor matching due to individual error contribution being reduced. A gain of 34 may seem low, when compared to common
5VREF 0.1F
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- +
3
4
8
9 13 6
- +
2431 F39
33
LTC2430/LTC2431
APPLICATIO S I FOR ATIO
practice in earlier generations of load-cell interfaces, however the accuracy of the LTC2430/LTC2431 changes the rationale. Achieving high gain accuracy and linearity at higher gains may prove difficult, while providing little benefit in terms of noise reduction. At a gain of 100, the gain error that could result from typical open-loop gain of 160dB is -1ppm, however, worst-case is at the minimum gain of 116dB, giving a gain error of -158ppm. Worst-case gain error at a gain of 34, is -54ppm. The use of the LTC1051A reduces the worstcase gain error to -33ppm. The advantage of gain higher than 34, then becomes dubious, as the input referred noise sees little improvement and gain accuracy is potentially compromised. Note that this 4-amplifier topology has advantages over the typical integrated 3-amplifier instrumentation amplifier in that it does not have the high noise level common in the output stage that usually dominates when an instrumentation amplifier is used at low gain. If this amplifier is used at a gain of 10, the gain error is only 10ppm and input referred noise is reduced to 0.28VRMS. The buffer stages can also be configured to provide gain of up to 50 with high gain stability and linearity. Figure 40 shows an example of a single amplifier used to produce single-ended gain. This topology is best used in
350 BRIDGE 3
+
1F R1 4.99k
AV = 9.95 =
R1 + R2 R1 + 175
Figure 40. Bridge Amplification Using a Single Amplifier
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applications where the gain setting resistor can be made to match the temperature coefficient of the strain gauges. If the bridge is composed of precision resistors, with only one or two variable elements, the reference arm of the bridge can be made to act in conjunction with the feedback resistor to determine the gain. If the feedback resistor is incorporated into the design of the load cell, using resistors which match the temperature coefficient of the loadcell elements, good results can be achieved without the need for resistors with a high degree of absolute accuracy. The common mode voltage in this case, is again a function of the bridge output. Differential gain as used with a 350 bridge is: A V = 9.95 = R1 + R2 R1 + 175 Common mode gain is half the differential gain. The maximum differential signal that can be used is 1/4 VREF, as opposed to 1/2 VREF in the 2-amplifier topology above. Remote Half Bridge Interface As opposed to full bridge applications, typical half bridge applications must contend with nonlinearity in the bridge output, as signal swing is often much greater. Applications include RTD's, thermistors and other resistive elements that undergo significant changes over their span. For
+
10F 5V 0.1V 6 175 REF + 0.1F 5V
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+ -
7
VCC
LTC1050 2 4
+
1F R2 46.4k 20k 20k
REF - IN + LTC2430/ LTC2431 IN - GND
2431 F40
LTC2430/LTC2431
APPLICATIO S I FOR ATIO
single variable element bridges, the nonlinearity of the half bridge output can be eliminated completely; if the reference arm of the bridge is used as the reference to the ADC, as shown in Figure 41. The LTC2430/LTC2431 can accept inputs up to 1/2 VREF. Hence, the reference resistor R1 must be at least 2x the highest value of the variable resistor. In the case of 100 platinum RTD's, this would suggest a value of 800 for R1. Such a low value for R1 is not advisable due to self-heating effects. A value of 25.5k is shown for R1, reducing self-heating effects to acceptable levels for most sensors. The basic circuit shown in Figure 41 shows connections for a full 4-wire connection to the sensor, which may be
VS 2.7V TO 5.5V
R1 25.5k 0.1% 24 PLATINUM 100 RTD 1 3
REF +
VCC
REF - LTC2430/ LTC2431 + IN IN - GND
2431 F41
Figure 41. Remote Half Bridge Interface
5V
R2 10k 0.1% R1 10k, 5%
24 PLATINUM 100 RTD 1 3
Figure 42. Remote Half Bridge Sensing with Noise Supression on Reference
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located remotely. The differential input connections will reject induced or coupled 60Hz interference, however, the reference inputs do not have the same rejection. If 60Hz or other noise is present on the RTD, a low pass filter is recommended as shown in Figure 42. Note that you cannot place a large capacitor directly at the junction of R1 and R2, as it will store charge from the sampling process. A better approach is to produce a low pass filter decoupled from the input lines with a high value resistor (R3). The use of a third resistor in the half bridge, between the variable and fixed elements gives essentially the same result as the two resistor version, but has a few benefits. If, for example, a 25k reference resistor is used to set the excitation current with a 100 RTD, the negative reference input is sampling the same external node as the positive input, but may result in errors if used with a long cable. For short cable applications, the errors may be acceptably low. If instead the single 25k resistor is replaced with a 10k 5% and a 10k 0.1% reference resistor, the noise level introduced at the reference, at least at higher frequencies, will be reduced. A filter can be introduced into the network, in the form of one or more capacitors, or ferrite beads, as long as the sampling pulses are not translated into an error. The reference voltage is also reduced, but this is not undesirable, as it will decrease the value of the LSB, although, not the input referred noise level.
5V R3 10k 5%
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+
1F LTC1050
560
REF + REF -
VCC
-
10k 10k
LTC2430/ LTC2431 IN + IN - GND
2431 F42
35
LTC2430/LTC2431
APPLICATIO S I FOR ATIO
The circuit shown in Figure 42 shows a more rigorous example of Figure 41, with increased noise suppression and more protection for remote applications. Figure 43 shows an example of gain in the excitation circuit and remote feedback from the bridge. The LTC1043s provide voltage multiplication, providing 10V from a 5V reference with only 1ppm error. The amplifiers are used at unity-gain and, hence, introduce a very little error due to gain error or due to offset voltages. A 1V/C offset voltage
15V 15V 7 Q1 2N3904 20 6
+ -
3 1F
LTC1150 2 4
33 1k 350 10V BRIDGE 0.1F
-15V
-10V 33
15V 7 Q2 2N3906 -15V 6 20 4 -15V 0.1F
+ -
3
LTC1150 2
1k
Figure 43. LTC1043 Provides Precise 4x Reference for Excitation Voltages
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drift translates into 0.05ppm/C gain error. Simpler alternatives, with the amplifiers providing gain using resistor arrays for feedback, can produce results that are similar to bridge sensing schemes via attenuators. Note that the amplifiers must have high open-loop gain or gain error will be a source of error. The fact that input offset voltage has relatively little effect on overall error may lead one to use low performance amplifiers for this application. Note that the gain of a device such as an LF156, (25V/mV over
15V U1 4 LTC1043 10V 200 8 * 11 47F 7 5V LT1236-5 10V 0.1F
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+
12 14 17 0.1F VCC LTC2430/ LTC2431 REF + REF - IN + IN - U2 LTC1043 5 * 2 6 GND 5V 13 10F
+
3 15 18 *FLYING CAPACITORS ARE 1F FILM (MKP OR EQUIVALENT) 7 * 1F FILM 200 -10V 17 -10V 11 SEE LTC1043 DATA SHEET FOR DETAILS ON UNUSED HALF OF U1
5V U2 4 LTC1043 8
12 14 13
2431 F43
LTC2430/LTC2431
APPLICATIO S I FOR ATIO
temperature) will produce a worst-case error of -180ppm at a noise gain of 3, such as would be encountered in an inverting gain of 2, to produce -10V from a 5V reference. The error associated with the 10V excitation would be -80ppm. Hence, overall reference error could be as high as 130ppm, the average of the two. Figure 45 shows a similar scheme to provide excitation using resistor arrays to produce precise gain. The circuit is configured to provide 10V and -5V excitation to the bridge, producing a common mode voltage at the input to the LTC2430/LTC2431 of 2.5V, maximizing the AC input range for applications where induced 60Hz could reach amplitudes up to 2VRMS. The circuits in Figures 43 and 45 could be used where multiple bridge circuits are involved and bridge output can be multiplexed onto a single LTC2430/LTC2431, via an inexpensive multiplexer such as the 74HC4052. Figure 44 shows the use of an LTC2430/LTC2431 with a differential multiplexer. This is an inexpensive multiplexer that will contribute some error due to leakage if used directly with the output from the bridge, or if resistors are inserted as a protection mechanism from overvoltage. Although the bridge output may be within the input range
5V
TO OTHER DEVICES
Figure 44. Use a Differential Mulitplexer to Expand Channel Capability
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of the A/D and multiplexer in normal operation, some thought should be given to fault conditions that could result in full excitation voltage at the inputs to the multiplexer or ADC. The use of amplification prior to the multiplexer will largely eliminate errors associated with channel leakage developing error voltages in the source impedance. Complete 20-Bit Data Acquistion System in 0.1 Inch2 The LTC2430/LTC2431 provide 20-bit accuracy while consuming a maximum of 300A. The MS package of the LTC2431 makes it especially attractive in applications where very limited space is available. A complete 20-bit data acquisition system in 0.1 inch2 is shown in Figure 46 where the LTC2431 is powered by the LT1790 reference family in an S6 package. A supply voltage from 0.25V above the LT1790 output level to 20V enables the LT1790 to source up to 1mA and ensure the solid performance of the LT2431. The 3V, 3.3V, 4.096V and 5V versions of the LT1790 can power the LTC2430/LTC2431 directly. Lower voltage versions will require a separate VCC supply of 2.7V to 5.5V for the LTC2430/LTC2431.
5V 16 12 14 15 11 1 5 2 4 8 9 10 A0 A1
2431 F44
W
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+
47F REF + REF - VCC
74HC4052 13 3 6
LTC2430/ LTC2431 IN + IN - GND
24301f
37
LTC2430/LTC2431
APPLICATIO S I FOR ATIO
15V Q1 2N3904 22
20
RN1 10k 10V 1 2 RN1 10k 5V 3 4 VCC LTC2430/ LTC2431 REF + REF - -5V 8 RN1 10k 5 6 7 RN1 10k IN + IN - GND
350 BRIDGE TWO ELEMENTS VARYING
33 x2 Q2, Q3 2N3906 x2 20 7
-15V
Figure 45. Use Resistor Arrays to Provide Precise Matching in Excitation Amplifier
38
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+
1 C1 0.1F 1/2 LT1112 3 5V
W
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+
2
LT1236-5 C3 47F C1 0.1F
-
C2 0.1F
15V RN1 IS CADDOCK T914 10K-010-02 8
- +
6
1/2 LT1112 4 -15V
5
2431 F45
24301f
LTC2430/LTC2431
PACKAGE DESCRIPTIO
.254 MIN
.0165 .0015
RECOMMENDED SOLDER PAD LAYOUT 1 .015 .004 x 45 (0.38 0.10) .007 - .0098 (0.178 - 0.249) .016 - .050 (0.406 - 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0 - 8 TYP .053 - .068 (1.351 - 1.727) 23 4 56 7 8 .004 - .0098 (0.102 - 0.249)
5.23 (.206) MIN
0.50 0.305 0.038 (.0197) (.0120 .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT
GAUGE PLANE 12345 0.53 0.01 (.021 .006) DETAIL "A" 0.18 (.007) SEATING PLANE 0.17 - 0.27 (.007 - .011) TYP 0.13 0.076 (.005 .003)
MSOP (MS) 0802
NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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GN Package 16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.045 .005 .189 - .196* (4.801 - 4.978) 16 15 14 13 12 11 10 9 .009 (0.229) REF .150 - .165 .229 - .244 (5.817 - 6.198) .150 - .157** (3.810 - 3.988) .0250 TYP .008 - .012 (0.203 - 0.305) .0250 (0.635) BSC
GN16 (SSOP) 0502
MS Package 10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
0.889 0.127 (.035 .005)
3.2 - 3.45 (.126 - .136) 3.00 0.102 (.118 .004) (NOTE 3) 10 9 8 7 6
0.497 0.076 (.0196 .003) REF
0.254 (.010)
DETAIL "A" 0 - 6 TYP
4.90 0.15 (1.93 .006)
3.00 0.102 (.118 .004) NOTE 4
1.10 (.043) MAX
0.86 (.034) REF
0.50 (.0197) BSC
24301f
39
LTC2430/LTC2431
TYPICAL APPLICATIO
Relative Size of Components
Figure 46. Complete 20-Bit Data Acquisition System in 0.1 inch2
RELATED PARTS
PART NUMBER LT(R)1019 LT1025 LTC1050 LT1236A-5 LT1460 LT1790 LTC2400 LTC2401/LTC2402 LTC2404/LTC2408 LTC2410 LTC2411 LTC2413 LTC2414/LTC2418 LTC2415 LTC2420 LTC2421/LTC2422 LTC2424/LTC2428 LTC2440 DESCRIPTION Precision Bandgap Reference, 2.5V, 5V Micropower Thermocouple Cold Junction Compensator Precision Chopper Stabilized Op Amp Precision Bandgap Reference, 5V Micropower Series Reference Micropower SOT23 Low Dropout Reference Family 24-Bit, No Latency ADC in SO-8 1-/2-Channel, 24-Bit, No Latency ADC in MSOP 4-/8-Channel, 24-Bit, No Latency ADC 24-Bit, Fully Differential, No Latency ADC 24-Bit, Fully Differential, No Latency ADC in MS10 24-Bit, Fully Differential, No Latency ADC 8-/16-Channel 24-Bit Differential, No Latency ADC 24-Bit, No Latency ADC with 15Hz Output Rate 20-Bit, No Latency ADC in SO-8 1-/2-Channel, 20-Bit, No Latency ADC in MSOP-10 4-/8-Channel, 20-Bit, No Latency ADC 24-Bit, High Speed, Low Noise ADC COMMENTS 3ppm/C Drift, 0.05% Max Initial Accuracy 80A Supply Current, 0.5C Initial Accuracy No External Components 5V Offset, 1.6VP-P Noise 0.05% Max Initial Accuracy, 5ppm/C Drift 0.075% Max Initial Accuracy, 10ppm/C Max Drift 0.05% Max Initial Accuracy, 10ppm/C Max Drift 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200A 0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200A 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200A 0.16ppm Noise, 2ppm INL, 10ppm Total Unadjusted Error, 200A 0.29ppm Noise, 2ppm INL, 10ppm Total Unadjusted Error, 200A Simultaneous 50Hz and 60Hz Rejection, 800nVRMS Noise 0.2ppm Noise, 2ppm INL, 10ppm Total Unadjusted Error Pin Compatible with the LTC2410 1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400 1.2ppm Noise, Low Power 2.7V to 5.5V Supply, 200A 1.2ppm Noise, Pin Compatible with LTC2404/LTC2408 200nVRMS Noise, 4000Hz Output Rate
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
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SUPPLY VOLTAGE RANGE: (VOUT + 0.25V) TO 20V LT1790 VOUT 4.7F 6 4 2 0.1F LT1790 1 0.1F VCC LTC2431 REF + REF - ANALOG INPUT RANGE -0.5VREF TO 0.5VREF IN + IN - GND
24301 TA05
VCC
FO
= INTERNAL OSC/50Hz REJECTION = EXTERNAL CLOCK SOURCE = INTERNAL OSC/60Hz REJECTION
SCK 3-WIRE SPI INTERFACE
SDO CS
THE LT1790 IS AVAILABLE WITH 1.25V, 2.048V, 2.5V, 3V, 3.3V, 4.096V AND 5V OUTPUTS THE LTC2431 MAY BE POWERED BY THE LT1790 3V, 3.3V, 4.096V AND 5V VERSIONS
24301f LT/TP 0303 2K * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2002

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