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HY57V561620(L)T 4Banks x 4M x 16Bit Synchronous DRAM DESCRIPTION The HY57V561620T is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V561620 is organized as 4 banks of 4,194,304x16. The HY57V561620T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline ( CAS latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a 2N rule.) FEATURES * * * Single 3.3V 0.3V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by UDQM and LDQM Internal four banks operation * * * * Auto refresh and self refresh 8192 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 and Full Page for Sequential Burst * - 1, 2, 4 and 8 for Interleave Burst Programmable CAS Latency ; 2, 3 Clocks * * ORDERING INFORMATION Part No. HY57V561620T-HP HY57V561620T-H HY57V561620T-8 HY57V561620T-P HY57V561620T-S HY57V561620LT-HP HY57V561620LT-H HY57V561620LT-8 HY57V561620LT-P HY57V561620LT-S Clock Frequency 133MHz 133MHz 125MHz 100MHz 100MHz 133MHz 133MHz 125MHz 100MHz 100MHz Power Organization Interface Package Normal 4Banks x 4Mbits x16 LVTTL 400mil 54pin TSOP II Lower Power This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Revision 1.8 / Apr.01 HY57V561620(L)T PIN CONFIGURATION VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM /WE /CAS /RAS /CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS 54pin TSOP II 400mil x 875mil 0.8mm pin pitch PIN DESCRIPTION PIN CLK Clock PIN NAME DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CLK, CKE, UDQM and LDQM Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA8 Auto-precharge flag : A10 RAS, CAS and WE define the operation Refer function truth table for details Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Power supply for internal circuits and input buffers Power supply for output buffers No connection CKE CS BA0, BA1 Clock Enable Chip Select Bank Address A0 ~ A12 Address Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground No Connection RAS, CAS, WE UDQM, LDQM DQ0 ~ DQ15 VDD/VSS VDDQ/VSSQ NC Revision 1.8 / Apr.01 HY57V561620(L)T FUNCTIONAL BLOCK DIAGRAM 4Mbit x 4banks x16 I/O Synchronous DRAM Self Refresh Logic & Timer Internal Row Counter CLK Row Active 4Mx16 Bank 3 Row Pre Decoders 4Mx16 Bank 2 X decoders 4Mx16 Bank 1 X decoders 4Mx16 Bank 0 DQ0 DQ1 I/O Buffer & Logic Sense AMP & I/O Gate CKE CS RAS CAS WE UDQM LDQM State Machine Column Active X decoders Memory Cell Array Column Pre Decoders Y decoders DQ14 DQ15 Bank Select Column Add Counter A0 A1 Address buffers A12 BA0 BA1 Address Register Burst Counter Mode Registers CAS Latency Data Out Control Pipe Line Control Revision 1.8 / Apr.01 HY57V561620(L)T ABSOLUTE MAXIMUM RATINGS Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Short Circuit Output Current Power Dissipation Soldering Temperature Time TA TSTG VIN, VOUT VDD, VDDQ IOS PD TSOLDER Symbol 0 ~ 70 -55 ~ 125 -1.0 ~ 4.6 -1.0 ~ 4.6 50 1 260 10 Rating C C V V mA W C Sec Unit Note : Operation at above absolute maximum rating can adversely affect device reliability DC OPERATING CONDITION (TA=0 to 70C) Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VDD, VDDQ VIH VIL Min 3.0 2.0 VSSQ-2.0 Typ. 3.3 3.0 0 Max 3.6 VDDQ + 0.3 0.8 Unit V V V Note 1 1,2 1,3 Note : 1. All voltages are referenced to VSS = 0V 2. VIH (max) is acceptable 5.6V AC pulse width with 3ns of duration 3. VIL (max) is acceptable -2.0V AC pulse width with 3ns of duration AC OPERATING CONDITION (TA=0 to 70C, VDD=3.3 0.3V, VSS=0V) Parameter AC Input High / Low Level Voltage Input Timing Measurement Reference Level Voltage Input Rise / Fall Time Output Timing Measurement Reference Level Output Load Capacitance for Access Time Measurement Symbol VIH / VIL Vtrip tR / tF Voutref CL Value 2.4/0.4 1.4 1 1.4 50 Unit V V ns V pF 1 Note Note : 1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF) For details, refer to AC/DC output circuit Revision 1.8 / Apr.01 HY57V561620(L)T CAPACITANCE (TA=25C, f=1MHz) -H Parameter Input capacitance CLK A0 ~ A12, BA0, BA1, CKE, CS, RAS, CAS, WE, UDQM, LDQM Data input / output capacitance DQ0 ~ DQ15 Pin Symbol Min CI1 CI2 CI/O 2.5 2.5 4.0 Max 3.5 3.8 6.5 Min 2.5 2.5 4.0 Max 4.0 5.0 6.5 pF pF pF -8/P/S Unit OUTPUT LOAD CIRCUIT Vtt=1.4V RT=250 Output Output 50pF 50pF DC Output Load Circuit AC Output Load Circuit DC CHARACTERISTICS I Parameter Input leakage current Output leakage current Output high voltage Output low voltage ILI ILO VOH VOL (TA=0 to 70C, VDD=3.30.3V) Symbol Min. -1 -1 2.4 - Max 1 1 0.4 Unit uA uA V V Note 1 2 IOH = -4mA IOL =+4mA Note : 1. VIN = 0 to 3.6V, All other pins are not under test = 0V 2. DOUT is disabled, VOUT=0 to 3.6V Revision 1.8 / Apr.01 HY57V561620(L)T DC CHARACTERISTICS II (TA=0C to 70C, VDD=3.3V 0.3V, VSS=0V) Speed Parameter Symbol Test Condition -HP Operating Current IDD1 IDD2P IDD2PS Burst Length=1, One bank active tRAS tRAS(min),tRP tRP(min), IO=0mA CKE VIL(max), tCK = min. CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = min Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable. CKE VIL(max), tCK = min CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = min Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable tCK tCK(min), tRAS tRAS(min), IO=0mA All banks active tRRC tRRC(min), All banks active CKE 0.2V 120 -H 120 -8 110 2 mA 2 -P 100 -S 100 mA 1 Unit Note Precharge Standby Current in power down mode IDD2N Precharge Standby Current in non power down mode IDD2NS IDD3P IDD3PS 20 mA 10 3 mA 3 Active Standby Current in power down mode IDD3N Active Standby Current in non power down mode IDD3NS 25 mA 15 Burst Mode Operating Current Auto Refresh Current IDD4 150 150 140 120 120 mA 1 IDD5 260 260 260 3 1.5 250 250 mA mA mA 2 3 4 Self Refresh Current IDD6 Note : 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open. 2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3. HY57V561620T-HP/H/8/P/S 4. HY57V561620LT-HP/H/8/P/S Revision 1.8 / Apr.01 HY57V561620(L)T AC CHARACTERISTICS I -HP Parameter Symbol Min System clock cycle time Clock high pulse width Clock low pulse width Access time from clock Data-out hold time Data-Input setup time Data-Input hold time Address setup time Address hold time CKE setup time CKE hold time Command setup time Command hold time CLK to data output in low Z-time CLK to data output in high Z-time CAS Latency = 3 CAS Latency = 2 CAS Latency = 3 CAS Latency = 2 CAS Latency = 3 CAS Latency = 2 tCK3 tCK2 tCHW tCLW tAC3 tAC2 tOH tDS tDH tAS tAH tCKS tCKH tCS tCH tOLZ tOHZ3 tOHZ2 7.5 1000 10 2.5 2.5 2.7 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1 2.7 3 5.4 6 5.4 6 10 2.5 2.5 2.7 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1 2.7 3 5.4 6 5.4 6 Max Min 7.5 1000 10 3 3 3 2 1 2 1 2 1 2 1 1 3 3 6 6 6 6 3 2 1 2 1 2 1 2 1 1 3 3 Max Min 8 1000 10 3 3 6 6 6 6 3 2 1 2 1 2 1 2 1 1 3 3 Max Min 10 1000 12 3 3 6 6 6 6 Max Min 10 1000 ns ns ns ns 2 ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 1 1 1 1 1 1 1 Max ns -H -8 -P -S Unit Note Note : 1. Assume tR / tF (input rise and fall time ) is 1ns. 2. Access times to be measured with input signals of 1v/ns slew rate, 0.8v to 2.0v Revision 1.8 / Apr.01 HY57V561620(L)T AC CHARACTERISTICS II -HP Parameter Symbol Min Operation RAS cycle time Auto Refresh RAS to CAS delay RAS active time RAS precharge time RAS to RAS bank active delay CAS to CAS delay Write command to data-in delay Data-in to precharge command Data-in to active command DQM to data-out Hi-Z DQM to data-in mask MRS to new command Precharge to data output Hi-Z Power down exit time Self refresh exit time Refresh Time CAS Latency = 3 CAS Latency = 2 tRRC tRCD tRAS tRP tRRD tCCD tWTL tDPL tDAL tDQZ tDQM tMRD tPROZ3 tPROZ2 tPDE tSRE tREF 65 20 45 20 15 1 0 2 5 2 0 2 3 1 1 100K 64 65 20 45 20 15 1 0 2 5 2 0 2 3 1 1 100K 64 68 20 48 20 16 1 0 2 5 2 0 2 3 1 1 100K 64 70 20 50 20 20 1 0 2 4 2 0 2 3 2 1 1 100K 64 70 20 50 20 20 1 0 2 4 2 0 2 3 2 1 1 100K 64 ns ns ns ns ns CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK ms 1 tRC 65 Max Min 65 Max Min 68 Max Min 70 Max Min 70 Max ns -H -8 -P -S Unit Note Note : 1. A new command can be given tRRC after self refresh exit. Revision 1.8 / Apr.01 HY57V561620(L)T IBIS SPECIFICATION IOH Characteristics (Pull-up) Voltage (V) 3.45 3.3 3.0 2.6 2.4 2.0 1.8 1.65 1.5 1.4 1.0 0.0 0.0 -21.1 -34.1 -58.7 -67.3 -73.0 -77.9 -80.8 -88.6 -93.0 100MHz Min I (mA) 100MHz Max I (mA) -2.4 -27.3 66MHz Min 66MHz and 100MHz Pull-up 0 0 I (mA) 0.5 1 1.5 2 2.5 3 3.5 -100 -200 I (mA) -0.7 -7.5 -13.3 -27.5 -35.5 -41.1 -47.9 -52.4 -74.1 -129.2 -153.3 -197.0 -226.2 -248.0 -269.7 -284.3 -344.5 -502.4 -300 -400 -500 -600 Voltage (V) Ioh Min (100MHz) -72.5 -93.0 Ioh Min (66MHz) Ioh Min (66 and 100MHz) IOL Characteristics (Pull-down) Voltage (V) 0.0 0.4 0.65 0.85 1.0 1.4 1.5 1.65 1.8 1.95 3.0 3.45 100MHz Min I (mA) 0.0 27.5 41.8 51.6 58.0 70.7 72.9 75.4 77.0 77.6 80.3 81.4 100MHz Max I (mA) 0.0 70.2 107.5 133.8 151.2 187.7 194.4 202.5 208.6 212.0 219.6 222.6 66MHz Min I (mA) 0.0 66MHz and 100MHz Pull-down 250 200 26.9 33.3 37.6 46.6 48.0 49.5 50.7 51.5 54.2 54.9 I (mA) 17.7 150 100 50 0 0 0.5 1 1.5 2 Voltage (V) 2.5 3 3.5 I (mA) 100 min I (mA) 66 min I (mA) 100 max ** IBIS spec. is also applied to 133MHz device. Revision 1.8 / Apr.01 HY57V561620(L)T VDD Clamp @ CLK, CKE, CS, DQM & DQ VDD (V) 0.0 0.2 0.4 0.6 0.7 0.8 0.9 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 I(mA) 0.0 0.0 0.0 0.0 Minimum VDD clamp current (Referenced to VDD) 20 15 mA 0.0 0.0 0.0 0.23 1.34 3.02 5.06 7.35 9.83 12.48 15.30 18.31 10 5 0 0 1 2 3 Voltage I (mA) VSS Clamp @ CLK, CKE, CS, DQM & DQ VSS (V) -2.6 -2.4 -2.2 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.9 -0.8 -0.7 -0.6 -0.4 -0.2 0.0 I (mA) -57.23 -45.77 -38.26 -31.22 Minimum VSS clamp current -3 0 -10 -20 -2.5 -2 -1.5 -1 -0.5 0 mA -24.58 -18.37 -12.56 -7.57 -3.37 -1.75 -0.58 -0.05 0.0 0.0 0.0 0.0 -30 -40 -50 -60 Voltage I (mA) Revision 1.8 / Apr.01 HY57V561620(L)T DEVICE OPERATING OPTION TABLE HY57V561620(L)T-HP CAS Latency 133MHz(7.5ns) 125MHz(8ns) 100MHz(10ns) 3CLKs 3CLKs 2CLKs tRCD 3CLKs 3CLKs 2CLKs tRAS 6CLKs 6CLKs 5CLKs tRC 9CLKs 9CLKs 7CLKs tRP 3CLKs 3CLKs 2CLKs tAC 5.4ns 6ns 6ns tOH 2.7ns 3ns 3ns HY57V561620(L)T-H CAS Latency 133MHz(7.5ns) 125MHz(8ns) 100MHz(10ns) 3CLKs 3CLKs 3CLKs tRCD 3CLKs 3CLKs 3CLKs tRAS 6CLKs 6CLKs 6CLKs tRC 9CLKs 9CLKs 9CLKs tRP 3CLKs 3CLKs 3CLKs tAC 5.4ns 6ns 6ns tOH 2.7ns 3ns 3ns HY57V561620(L)T-8 CAS Latency 125MHz(8ns) 100MHz(10ns) 83MHz(12ns) 3CLKs 3CLKs 2CLKs tRCD 3CLKs 3CLKs 2CLKs tRAS 6CLKs 6CLKs 4CLKs tRC 9CLKs 9CLKs 6CLKs tRP 3CLKs 3CLKs 2CLKs tAC 6ns 6ns 6ns tOH 3ns 3ns 3ns HY57V561620(L)T-P CAS Latency 100MHz(10ns) 83MHz(12ns) 66MHz(15ns) 2CLKs 2CLKs 2CLKs tRCD 2CLKs 2CLKs 2CLKs tRAS 5CLKs 5CLKs 4CLKs tRC 7CLKs 7CLKs 6CLKs tRP 2CLKs 2CLKs 2CLKs tAC 6ns 6ns 6ns tOH 3ns 3ns 3ns HY57V561620(L)T-S CAS Latency 100MHz(10.0ns) 83MHz(12.0ns) 66MHz(15.0ns) 3CLKs 2CLKs 2CLKs tRCD 2CLKs 2CLKs 2CLKs tRAS 5CLKs 5CLKs 4CLKs tRC 7CLKs 7CLKs 6CLKs tRP 2CLKs 2CLKs 2CLKs tAC 6ns 6ns 6ns tOH 3ns 3ns 3ns Revision 1.8 / Apr.01 HY57V561620(L)T COMMAND TRUTH TABLE Command Mode Register Set No Operation Bank Active Read H Read with Autoprecharge Write H Write with Autoprecharge Precharge All Banks H Precharge selected Bank Burst Stop UDQM, LDQM Auto Refresh Entry Self Refresh Exit L H L H Entry Precharge power down Exit L H L H Clock Suspend Entry Exit H L L L H V X V V X H X H X H X X X H L L H H X H X H X X X H X H X H X X H H H H H L L L H X L H X L L X L L X H H X X H L X V X X X X L L H L X X L X X X V X L H L L X CA H H X X L H L H X CA H L V CKEn-1 H H H CKEn X X L X L H L H H H H X RA L V V CS L H RAS L X CAS L X WE L X X X DQM X ADDR A10/ AP OP code BA Note 1 Note : 1. OP Code : Operand Code 2. V = Valid, X = Don' care, H = Logic High, L= Logic Low, RA = Row Address, CA = Column Address. t Revision 1.8 / Apr.01 HY57V561620(L)T PACKAGE INFORMATION 400mil 54pin Thin Small Outline Package Unit : mm(Inch) Revision 1.8 / Apr.01 |
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