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SM5847AF
NIPPON PRECISION CIRCUITS INC.
High-fidelity Digital Audio, Multi-function Digital Filter
OVERVIEW
The SM5847AF is a 4/8-times oversampling (interpolation), 2-channel, linear-phase FIR, multi-function digital filter for digital audio reproduction equipment. It features independent left and rightchannel digital deemphasis filters and soft muting function. The input/output interface supports input data in 16/18/20/24-bit words, and output data in 18/20/22/24-bit words in either 4-times or 8-times oversampling selectable output mode. The internal system clock operates at either 192fs or 256fs selectable speed (where fs is the audio sampling frequency). Plus, the divide-by 1, 2, or 4 counter settings means that external clocks of 768fs/ 384fs/192fs (192fs input) and 1024fs/512fs/256fs (256fs input) are supported. The SM5847AF operates from a single 3 to 5 V supply, and is available in 44-pin QFP packages.
FEATURES
s s
s
s s s
s
Left/right-channel (2-channel processing) 4-times/8-times oversampling (interpolation) * 8-times interpolation filter - 3-stage linear-phase FIR configuration 1st stage (fs to 2fs): 169-tap 2nd stage (2fs to 4fs): 29-tap 3rd stage (4fs to 8fs): 17-tap - 0.00002 dB passband ripple (0 to 0.4535fs) - 117 dB stopband attenuation (0.5465fs to 7.4535fs) * 4-times interpolation filter - 2-stage linear-phase FIR configuration 1st stage (fs to 2fs): 169-tap 2nd stage (2fs to 4fs): 29-tap - 0.00002 dB passband ripple (0 to 0.4535fs) - 116 dB stopband attenuation (0.5465fs to 3.4535fs) Digital deemphasis * IIR filter configuration * fs = 32kHz, 44.1kHz, 48kHz * 2-channel independent ON/OFF control 26 x 24-bit parallel multiplier/32-bit accumulator Overflow limiter Soft muting * 2-channel independent ON/OFF control Input data format
s
s
s s
s
s s s s
* 2s complement, MSB first * 3 selectable formats - LR alternating, 16/18/20/24-bit serial, rightjustified data - LR alternating, 24-bit serial, left-justified data - LR simultaneous, 24-bit serial, left-justified data Output data format * 2s complement, MSB first, LR simultaneous * 18/20/22/24-bit serial * BCKO burst (NPC format) Dither round-off processing * Dither round-off ON/OFF selectable 25-bit internal data word length Internal system clock * 192fs/256fs selectable * Maximum operating frequency 192fs mode: 37 MHz max (5 V) 20.7 MHz max (3 V) 256fs mode: 27.6 MHz max (5 V) 25 MHz max (3 V) Jitter-free function * Jitter-free/Sync mode selectable Crystal oscillator circuit built-in 3 to 5 V supply 44-pin plastic QFP CMOS process
ORDERING INFORMATION
D e vice SM5847AF P ackag e 44-pin QFP
NIPPON PRECISION CIRCUITS--1
SM5847AF
PINOUT
(Top View)
MUTER
MUTEL
DEMPR
36
DITHN
DEMPL
CKDV2
35
44
43
42
41
40
39
38
37
OMD DOR DOL WCKO BCKO VSS VSSAC VDDAC VDD DG NC
34
CKDV1
FSEL2
FSEL1
VDD
VSS
1
33
RSTN SYNCN OW2N OW1N VDD VSS IW2N/DIR IW1N/DIL INF1N CKSLN NC
SM 5 8 4 7 A F
2 3 4 5 6 7 8 9 10 11 12 13 14 15
32 31 30 29 28 27 26 25 24 23
16
17
18
19
20
21
CKO
VDD
VDD
VSS
VSS
DI/INF2N
BCKI
LRCI
PACKAGE DIMENSIONS
(Unit: mm)
44-pin plastic QFP
+ 12.80 - 0.30 + 10.00 - 0.30
XTO
XTI
+ 0.17 - 0.05
(1.40)
12.80 + 0.30 -
10.00 + 0.30 -
NC
22
4
+ 0.35 - 0.10
-
C
+ 0.60 - 0.20
0.
7
0.20 M (1.40)
+ 0.17 - 0.05
+ 0.15 - 0.05
0.80 0.15
+ 0.20 1.50 - 0.10
NIPPON PRECISION CIRCUITS--2
0 to 10
SM5847AF
BLOCK DIAGRAM
DI/INF2N
XTI XTO CKO CKSLN CKDV1 CKDV2 SYNCN RSTN DEMPL DEMPR FSEL1 FSEL2 IW1N/DIL
System Clock
Input Data Interface
BCKI
LRCI
IW2N/DIR INF1N
DITHN VDD VSS VDDAC
Timing Controller
Filter and Attenuation Arithmetic Block
Deemphasis Controller Output Data Interface Block
VSSAC
OMD OW1N OW2N DG
MUTEL MUTER
Mute Controller
WCKO
BCKO
DOR
NIPPON PRECISION CIRCUITS--3
DOL
SM5847AF
PIN DESCRIPTION
Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Name OMD DOR DOL W C KO B C KO VSS VSSAC V D DAC VDD DG NC C KO VSS VDD X TO XTI VSS VDD LRCI DI/INF2N BCKI NC NC CKSLN INF1N IW1N/DIL IW2N/DIR VSS VDD OW1N OW2N SYNCN RSTN C K DV 1 C K DV 2 DEMPR DEMPL VDD VSS FSEL1 FSEL2 MUTEL MUTER DITHN I/O Ip 1 O2 O2 O2 O2 - - - - O2 - O2 - - O I - - I1 I1 I1 - - Ip 2 Ip 2 Ip 1 Ip 1 - - Ip 2 Ip 2 Ip 2 Ip 1 Ip 1 Ip 1 Ip 1 Ip 1 - - Ip 1 Ip 1 Ip 1 Ip 1 Ip 1 Output data rate (4fs/8fs) select pin Right-channel data output Left-channel data output W ord clock output Bit clock output Ground Ground Supply voltage Supply voltage Deglitched signal output No internal connection (must be open) Master clock output Ground Supply voltage Oscillator output Oscillator input/master clock input Ground Supply voltage Input data sample rate (fs) clock input Data input/input format select pin 2 Bit clock input No internal connection (must be open) No internal connection (must be open) Master clock frequency (192fs/256fs) select pin Input format select pin 1 Input data word length select pin 1/left-channel data input Input data word length select pin 2/right-channel data input Ground Supply voltage Output data word length select pin 1 Output data word length select pin 2 Sync mode select pin Reset input Internal system clock frequency divider set pin 1 Internal system clock frequency divider set pin 2 Right-channel deemphasis ON/OFF pin Left-channel deemphasis ON/OFF pin Supply voltage Ground Deemphasis filter sample rate (fs) select pin 1 Deemphasis filter sample rate (fs) select pin 2 Left-channel mute ON/OFF pin Right-channel mute ON/OFF pin Output data dither ON/OFF pin Description
1. Schmitt input, TTL level 2. TTL level Ip = Pull-up input
NIPPON PRECISION CIRCUITS--4
SM5847AF
SPECIFICATIONS
Absolute Maximum Ratings
VSS = VSSAC = 0 V, VDD = VDDAC
P arameter Supply voltage range 1 Symbol V D D, V D D A C VI T stg PD 70 C 85 C Condition Rating -0.3 to 6.5 V S S - 0.3 to V D D + 0.3 -55 to 125 900 mW 700 Unit V V C
Input voltage range Storage temperature range Pow er dissipation
1. Supply lines for VDD and V D D A C , and ground lines for VSS and V S S A C , should be connected on the printed circuit board to prevent device breakdown due to potential difference when the pow er is applied.
Recommended Operating Conditions
VSS = VSSAC = 0 V, VDD = VDDAC
P arameter Supply voltage range 1 Operating temperature range Symbol V D D, V D D A C Ta Rating 3.00 to 5.25 -40 to 85 Unit V C
1. The minimum required operating voltage and consequent operating temperature vary with the maximum operating frequency and sampling mode selected, as shown in the following table.
VSS = VSSAC = 0 V, VDD = VDDAC
Internal system clock Sampling frequency fs (kHz) Mode1 192fs 192 256fs 108 2 192fs 256fs 192fs 96 256fs 55.2 3 192fs 256fs 25 10.6 14.2 Not guaranteed 20.7 27.6 18.5 M a x i m um operating frequency (MHz) 37 M i n i mu m s u p p ly voltag e V D D , V D D A C (V) 4.75 (5.0 - 5%) Not guaranteed 3.00 (3.3 - 10%) 4.50 (5.0 - 10%) 3.00 (3.3 - 10%) 3.00 (3.3 - 10%) 3.00 (3.3 - 10%) 3.00 (3.3 - 10%) -40 to 85 Operating temperature T a (C) -40 to 70 Not guaranteed
1. Mode with internal frequency divider ratio set to 1 (CKDV 1 = C K DV2 = LOW). 2. 96 kHz + 12.5% variable pitch 3. 48 kHz + 15% variable pitch
NIPPON PRECISION CIRCUITS--5
SM5847AF
DC Electrical Characteristics
VDD = VDDAC = 3.00 to 5.25 V, VSS = VSSAC = 0 V, Ta = -40 to 85 C
Rating P arameter HIGH-level input voltage 1 HIGH-level input voltage 2 ,4 Symbol V IH1 V IH2 V IH3 V D D = V D D A C = 4.75 to 5.25 V V D D = V D D A C = 3.00 to 4.75 V V D D = V D D A C = 4.75 to 5.25 V V D D = V D D A C = 3.00 to 4.75 V V D D = V D D A C = 4.75 to 5.25 V V D D = V D D A C = 3.00 to 4.75 V V D D = V D D A C = 4.75 to 5.25 V V D D = V D D A C = 3.00 to 4.75 V V IN = 0 to 5.25 V V IN = 0 V IO H = -4 m A IO L = 4 mA Condition min 0.7V D D 2.0 2.4 2.0 - - - - - - -10 -10 2.4 - typ - - - - - - - - - - - -50 - - max - - - V - 0.3V D D 0.2V D D 0.8 V 0.2V D D 0.8 V 0.2V D D 10 -120 - 0.4 A A V V V V V Unit
HIGH-level input voltage 3
L O W -level input voltage 1
V IL1
L O W -level input voltage 2,4
V IL2
L O W -level input voltage 3 Input leakage current 1,2 Input current 3,4 voltage 5 voltage 5
V IL3 IIL1 IIL2 VOH VOL
HIGH-level output L O W -level output 1. 2. 3. 4. 5.
Pin XTI Pins LRCI, DI/INF2N, BCKI Pins IW1N/DIL, IW2N/DIR P i n s O M D, CKSLN, INF1N, OW 1 N , OW 2 N , S Y N C N , R S T N , C K DV1, CKDV2, DEMPR, DEMPL, FSEL1, FSEL2, MUTEL, MUTER, DITHN Pins DOR, DOL, W C K O , BCKO , DG, CKO
VDD = VDDAC = 4.75 to 5.25 V, VSS = VSSAC = 0 V, Ta = -40 to 85 C, XTI = external input, no output load
Rating P arameter Symbol Condition min ID D 1 ID D 2 Current consumption ID D 3 ID D 4 ID D 5 192fs, XTI = 27 ns (37 MHz), fs = 192 kHz,Ta = -40 to 70 C 256fs, XTI = 40 ns (25 MHz), fs = 96 k H z 384fs, XTI = 27 ns (37 MHz), fs = 96 kHz, estimated value 192fs, XTI = 54 ns (18.5 MHz), fs = 96 kHz, estimated value 384fs, XTI = 54 ns (18.5 MHz), fs = 48 kHz, estimated value - - - - - typ - - - - - max 166 115 105 95 65 mA mA mA mA mA Unit
VDD = VDDAC = 3.00 to 3.60 V, VSS = VSSAC = 0 V, Ta = -40 to 85 C, XTI = external input, no output load
Rating P arameter Symbol Condition min ID D 6 Current consumption ID D 7 384fs, XTI = 54 ns (18.5 MHz), fs = 48 kHz, estimated value - - 28 mA 256fs, XTI = 81 ns (12.3 MHz), fs = 48 kHz, estimated value - typ - max 27 mA Unit
NIPPON PRECISION CIRCUITS--6
SM5847AF
AC Electrical Characteristics
Crystal oscillator (XTI, XTO) VDD = VDDAC = 3.00 to 5.25 V, VSS = VSSAC = 0 V, Ta = -40 to 85 C
Rating P arameter Oscillator frequency 1 Symbol fO S C Condition min - typ - max 50 MHz Unit
1. External circuit components should be matched for the crystal oscillator element used.
External clock input (XTI) VDD = VDDAC = 3.00 to 5.25 V, VSS = VSSAC = 0 V, Ta = -40 to 85 C
Rating P arameter Master clock frequency Master clock duty Symbol fXTI 1/2V D D thresholds Condition min - 40 typ - - max 60 60 MHz % Unit
Internal system clock The crystal oscillator frequency or external clock input master clock frequency ratings are described in the preceding tables, but it is the internal system clock frequency rating, set by the internal frequency divider (CKDV1, CKDV2), that must be satisfied. The master clock frequency is a multiple of the sampling frequency fs. CKDV1 = CKDV2 = LOW (internal system clock frequency = XTI input frequency), VSS = VSSAC = 0 V, Ta = -40 to 85 C
Rating P arameter Symbol Condition min 256fs (CKSLN = LOW , CKDV1 = LOW , CKDV2 = LOW ) System clock frequency fS Y S 1 V D D = V D D A C = 4.50 to 5.25 V V D D = V D D A C = 3.00 to 5.25 V 0.256 0.256 - - 27.6 MHz 25 typ max Unit
192fs (CKSLN = HIGH, CKDV1 = LOW , CKDV2 = LOW ) V D D = V D D A C = 4.75 to 5.25 V, T a = -40 to 70 C V D D = V D D A C = 3.00 to 5.25 V 0.384 0.384 - - 37 MHz 20.7
System clock frequency
fS Y S 2
NIPPON PRECISION CIRCUITS--7
SM5847AF
Serial input timing (BCKI, LRCI, DI/INF2N, IW1N/DIL, IW2N/DIR)
VSS = VSSAC = 0 V, Ta = -40 to 85 C
Rating P arameter Symbol Note 1 BCKI pulse cycle tI B C Y Note 2 Note 3 Note 1 BCKI HIGH-level pulsewidth tB C W H Note 2 Note 3 Note 1 B C K I L OW -level pulsewidth tB C W L Note 2 Note 3 Note 1 DI, DIL, DIR setup time tD S Note 2 Note 3 Note 1 DI, DIL, DIR hold time tD H Note 2 Note 3 Note 1 Last BCKI rising edge to LRCI edge tB L Note 2 Note 3 Note 1 LRCI edge to first BCKI rising edge tL B Note 2 Note 3 1. CKSLN = HIGH 2. C K S L N = L OW CKSLN = HIGH 3. C K S L N = L OW (192fs), V D D = V D D A C = 4.75 to 5.25 V, T a = -40 to 70 C (256fs), V D D = V D D A C = 4.50 to 5.25 V (192fs), V D D = V D D A C = 3.00 to 4.75 V (256fs), V D D = V D D A C = 3.00 to 4.50 V Condition min 55 80 100 25 35 45 25 35 45 10 20 30 10 20 30 10 20 30 10 20 30 typ - - - - - - - - - - - - - - - - - - - - - max - - - - - - - - - - - - - - - - - - - - - ns ns ns ns ns ns ns Unit
tIBCY
BCKI 1.5V
tBCWH
DI DIL DIR
tBCWL
1.5V
tDS
tDH tBL tLB
1.5V
LRCI
NIPPON PRECISION CIRCUITS--8
SM5847AF Reset timing (RSTN) VDD = VDDAC = 3.00 to 5.25 V, VSS = VSSAC = 0 V, Ta = -40 to 85 C
Rating P arameter R S T N L OW -level reset pulsewidth Symbol tR S T Condition min1 2t M C K Unit typ - max - ns
1. tM C K is equal to 1/f XTI or 1/f O S C . For example, tR S T = 54 ns when f XTI = 37 MHz.
RSTN
1.5V
tRST
Output timing (CKO, BCKO, WCKO, DOL, DOR, DG) VDD = VDDAC = 4.75 to 5.25 V, VSS = VSSAC = 0 V, Ta = -40 to 70 C, CL = 50 pF
Rating P arameter Symbol Condition min 4 XTI falling edge to CKO falling edge delay tX TO V D D = V D D A C = 3.00 to 5.25 V, T a = -40 to 85 C 4 -4 8 Output mode: 8fs OMD = HIGH (fs = 192 kHz) External clock input: XTI = 27 ns (37 MHz), C K S L N = HIGH (192fs) Divider ratio: 1 C K DV 1 = C K DV2 = LOW Output data length: 24 bits O W 1 N = OW 2 N = L OW 8 27 7 7 7 7 17 Output mode: 4fs O M D = L OW (fs = 192 kHz) External clock input: XTI = 27 ns (37 MHz), C K S L N = HIGH (192fs) Divider ratio: 1 C K DV 1 = C K DV2 = LOW Output data length: 24 bits O W 1 N = OW 2 N = L OW 17 54 18 18 18 18 typ - - - - - - - - - - - - - - - - - max 9 11 2 - - - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
B C K O falling edge to W C K O , DOL, DOR, DG delay B C K O rising edge to W C K O falling edge W C K O falling edge to BCKO rising edge B C K O period B C K O HIGH-level pulsewidth B C K O L OW -level pulsewidth DOL, DOR setup time DOL, DOR hold time B C K O rising edge to W C K O falling edge W C K O falling edge to BCKO rising edge B C K O period B C K O HIGH-level pulsewidth B C K O L OW -level pulsewidth DOL, DOR setup time DOL, DOR hold time
tB D O tW O H tW O S tO B C Y tO B C H tO B C L tO D S tO D H tW O H tW O S tO B C Y tO B C H tO B C L tO D S tO D H
NIPPON PRECISION CIRCUITS--9
SM5847AF VDD = VDDAC = 4.50 to 5.25 V, VSS = VSSAC = 0 V, Ta = -40 to 85 C, CL = 50 pF
Rating P arameter B C K O HIGH-level pulsewidth B C K O L OW -level pulsewidth DOL, DOR setup time DOL, DOR hold time B C K O HIGH-level pulsewidth B C K O L OW -level pulsewidth DOL, DOR setup time DOL, DOR hold time Symbol tO B C H tO B C L tO D S tO D H tO B C H tO B C L tO D S tO D H Condition min External clock input: XTI = 36 ns (27.6 MHz), CKSLN = L O W (256fs), fs = 108 k H z Divider ratio: 1 C K DV 1 = C K DV2 = LOW Output mode: 8fs, OMD = H I G H External clock input: XTI = 36 ns (27.6 MHz), CKSLN = L O W (256fs), fs = 108 k H z Divider ratio: 1 C K DV 1 = C K DV2 = LOW Output mode: 4fs, OMD = L O W 10 10 11 11 26 26 27 27 typ - - - - - - - - max - - - - - - - - ns ns ns ns ns ns ns ns Unit
XTI
1.5V
CKO
tXTO
1.5V
BCKO 1.5V
WCKO DOL DOR DG
1.5V
tBDO
WCKO 1.5V
tWOH
BCKO
tWOS
1.5V
tOBCH tOBCY
DOL DOR
tOBCL
1.5V
tODS
tODH
NIPPON PRECISION CIRCUITS--10
SM5847AF
Filter Characteristics
8-times interpolation filter
P arameter P assband Stopband P assband ripple Stopband attenuation Group delay Rating 0 to 0.4535fs 0.5465fs to 7.4535fs 0.00002 dB 117 dB Constant
8fs filter response with deemphasis OFF
0 20 40 60 80 100 120 140 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
Attenuation (dB)
Frequency (x fs)
8fs filter band transition response with deemphasis OFF
Attenuation (dB)
-0.00008 -0.00004 0.00000 0.00004 0.00008 0.000 0.125 0.250 0.375 0.500
Frequency (x fs)
8fs filter passband response with deemphasis OFF
0 20
Attenuation (dB)
40 60 80 100 120 140 0.440
0.465
0.490
0.515
0.540
0.565
0.590
0.615
0.640
Frequency (x fs)
NIPPON PRECISION CIRCUITS--11
SM5847AF 4-times interpolation filter
P arameter P assband Stopband P assband ripple Stopband attenuation Group delay Rating 0 to 0.4535fs 0.5465fs to 3.4535fs 0.00002 dB 116 dB Constant
4fs filter response with deemphasis OFF
0
Attenuation (dB)
20 40 60 80 100 120 140 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Frequency (x fs)
4fs filter band transition response with deemphasis OFF
Attenuation (dB)
-0.00008 -0.00004 0.00000 0.00004 0.00008 0.000 0.125 0.250 0.375 0.500
Frequency (x fs)
4fs filter passband response with deemphasis OFF
0 20
Attenuation (dB)
40 60 80 100 120 140 0.440 0.465 0.490 0.515 0.540 0.565 0.590 0.615 0.640
Frequency (x fs)
NIPPON PRECISION CIRCUITS--12
SM5847AF Deemphasis filter
Sampling frequency (fs) P arameter 32 kHz P assband bandwidth (kHz) Attenuation D e viation from ideal characteristic P h a s e, 0 to 14.5 44.1 kHz 0 to 20.0 0.01 dB 0 to 1.5 48 kHz 0 to 21.7
Passband response with deemphasis ON
2
32kHz Phase 44.1kHz 48kHz
-20 -40 -60
Attenuation (dB)
4 6 8 10
Attenuation
32kHz 44.1kHz 48kHz
10 20 50 100 200 500 1k 2k 5k 10k 20k [Hz]
Frequency (Hz)
NIPPON PRECISION CIRCUITS--13
Phase (degrees)
0
0
SM5847AF
FUNCTIONAL DESCRIPTION
Oversampling (Interpolation)
The interpolation arithmetic block is comprised of 3 cascaded, 2-times FIR interpolation filters, as shown in figure 1. The input signal is sampled at rate fs, and then either 4-times or 8-times oversampling data is output. Sampling noise in the 0.5465fs to 3.4535fs (4fs output) or 0.5465fs to 7.4535fs (8fs output) region is removed.
Input fs 2-times interpolator 1st FIR 169-tap 2fs 2-times interpolator 2nd FIR 29-tap 4fs
Deemphasis IIR filter Deemphasis OFF Deemphasis ON
4fs Soft mute
4fs 2 -times interpolator 3rd FIR 17-tap 8fs 4fs
Output
Figure 1. Arithmetic operating block
NIPPON PRECISION CIRCUITS--14
SM5847AF
Digital Deemphasis (DEMPL, DEMPR, FSEL1, FSEL2)
Most deemphasis filters are constructed using analog circuit techniques. Here, an IIR filter is employed to faithfully reproduce the gain and phase characteristics of standard analog deemphasis filters, corresponding to analog 50s/15s frequency characteristics. Three sets of filter coefficients for the three fs = 32/44.1/48 kHz sampling frequencies are supported. Deemphasis for other values of fs are not supported. Deemphasis ON/OFF (DEMPL, DEMPR) Deemphasis for the left and right-channel can be controlled independently.
Table 1. Deemphasis control
DEMPL LOW HIGH x x DEMPR x x LOW HIGH Deemphasis Left-channel OFF Left-channel ON Right-channel OFF Right-channel ON
Filter coefficient select (FSEL1, FSEL2)
Table 2. Deemphasis filter coefficient select
FSEL1 LOW LOW HIGH HIGH FSEL2 LOW HIGH LOW HIGH Sampling frequency (fs) 44.1 kHz 48 kHz Prohibited mode 32 kHz
Soft Muting (MUTEL, MUTER)
The muting function controls the muting of left and right-channel independently. Input data continues to be accepted even when mute is operating. Mute ON/OFF When MUTEL (MUTER) goes HIGH, the attenuation changes smoothly from 0 to - dB. Similarly, when MUTEL (MUTER) goes LOW, muting is released and the attenuation changes smoothly from - to 0 dB. This operation is termed soft muting. Soft muting takes an interval of approximately 512/fs, or about 11.6 ms when fs = 44.1 kHz.
Table 3. Mute control
MUTEL LOW HIGH x x MUTER x x LOW HIGH Soft muting Left-channel OFF Left-channel ON Right-channel OFF Right-channel ON
Mute operation at reset When RSTN goes LOW, the DOL and DOR outputs are immediately muted to - dB. When RSTN goes HIGH, reset is released and the outputs are immediately set to 0 dB attenuation. Note that even when either MUTEL or MUTER or both are HIGH, the reset operation takes precedence.
NIPPON PRECISION CIRCUITS--15
SM5847AF
Analog Output Click Noise
Under the following conditions, a click noise may be output from the DAC (digital-to-analog converter) connected to the SM5847AF.
s s s
s
When a system reset on RSTN occurs When the internal system clock mode, set by CKSLN, CKDV1, and CKDV2, is switched When the deemphasis mode, set by DEMPL, DEMPR, FSEL1, and FSEL2, is switched
s
When the audio data input mode, set by INF1N, DI/INF2N, IW1N/DIL, and IW2N/DIR, is switched When the SYNCN jitter-free mode switch timing exceeds the internal timing delay limit
An external muting circuit connected to the analog output may be required to eliminate this noise.
DI/INF2N, IW1N/DIL, IW2N/DIR
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Normal operation
H soft mute L H soft mute 512/fs 0dB H L reset H L reset L
MUTEL/MUTER
RSTN
512/fs
Gain
-
+FS
External DAC analog output (full scale signal) click noise FS: full scale
zero -FS
Figure 2. Soft muting/reset operation
NIPPON PRECISION CIRCUITS--16
SM5847AF
Internal System Clock (XTI, XTO, CKO, CKSLN, CKDV1, CKDV2)
The SM5847AF supports two system clock frequencies selected by CKSLN, 192fs and 256fs, where fs is the sampling frequency. The master clock can be provided either by a crystal oscillator connected between XTI and XTO, or by an external master clock input on XTI. Note that the feedback resistor required by the oscillator option is not built-in. External components should be selected to match the crystal oscillator element. Note also that XTO must be left open (floating) for the external master clock input option. Note that even though it is necessary that the master clock and LRCI clock (sampling frequency fs) be in sync, it is not necessary that they be exactly in-phase (see jitter-free mode description). The SM5847AF features independent divide-by 1, 2, or 4counter, selected by CKDV1 and CKDV2. This provides the 192fs or 256fs system clock with the necessary divider ratios to support master clocks with frequencies of 768fs, 384fs, 192fs, 1024fs, 512fs or 256fs. Normal sampling frequencies 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz and 192 kHz are supported. However, some combinations of sampling frequency and master clock frequency are not supported, as follows.
s s
Table 4. Internal system clock select
CKSLN LOW HIGH System clock 256fs 192fs
Table 5. System clock frequency divider ratio select
C K DV1 LOW LOW HIGH HIGH C K DV2 LOW HIGH LOW HIGH Divider ratio 1 - 4 2 Master clock 192fs, 256fs Prohibited mode 768fs, 1024fs 384fs,512fs
Divider
16 15 12 XTI R1 XTO CKO
SM5847AF
s
768fs and 1024fs at 88.2 and 96 kHz 768fs, 384fs, 1024fs, 512fs, and 256fs at 176.4 kHz 768fs, 384fs, 1024fs, 512fs and 256fs at 192 kHz
C1
XTAL
Master Clock Buffer output C2
Figure 3. Crystal oscillator connection
Note also that the internal crystal oscillator circuit cannot operate at frequencies 50 MHz. The master clock input on XTI is output on CKO. Master clock stop operation The master clock is input after power is applied. But if, after the XTI and LRCI clocks are input and power-ON reset occurs with all-zero input audio data, the master clock input on XTI is held either HIGH or LOW level, operation effectively stops. Note also that a reset signal is not accepted when the master clock and LRCI clock stop.
16 XTI External Clock 15 XTO XTO : open 12 CKO Master Clock Buffer output SM5847AF Divider
Figure 4. External clock connection
NIPPON PRECISION CIRCUITS--17
SM5847AF
Table 6. Master clock frequency example
XTI system clock frequency (MHz) CKSLN = HIGH (192fs) Sampling frequency fs (kHz) C K D V1 L OW 192fs 32 44.1 48 88.2 96 176.4 192 6.144 8.4627 9.216 16.9344 18.432 33.8688 36.864 C K D V2 L OW C K D V1 HIGH C K D V2 HIGH 384fs 12.288 16.9344 18.432 33.8688 36.864 Not guaranteed Not guaranteed Not C K D V1 HIGH 768fs 24.576 33.8688 36.864 guaranteed 1 C K D V2 L OW C K D V1 L OW 256fs 8.192 11.2896 12.288 22.5792 24.576 Not guaranteed Not guaranteed C K D V2 L OW C K S L N = L OW (256fs) C K D V1 HIGH C K D V2 HIGH 512fs 16.384 22.5792 24.576 45.1584 49.152 Not guaranteed Not guaranteed C K D V1 HIGH C K D V2 L OW
1024fs 32.768 45.1584 49.152 Not guaranteed Not guaranteed Not guaranteed Not guaranteed
Not guaranteed Not guaranteed Not guaranteed 1
1. Refer to the AC characteristics system clock ratings.
System Reset (RSTN)
During normal device operation, reset signals are not required. However, the SM5847AF must be reset under the following conditions.
s s
When RSTN is LOW, the DOL and DOR outputs are tied LOW, muting the output signal to an attenuation level of -. After system reset, when RSTN goes HIGH, the arithmetic and output timing counters are reset on the first LRCI start edge, assuming that the XTI and LRCI input clocks have already stabilized. The LRCI start edge is determined by the state of INF1N and INF2N. When INF1N is LOW or when both INF1N and INF2N are HIGH, the start edge is the rising edge. When INF1N is HIGH and INF2N is LOW, the start edge is the falling edge.
s
At power-ON When the LRCI clock and internal operation timing need to be resynchronized in jitter-free mode. After the LRCI or XTI clocks, or both, stop and are subsequently started.
The system is reset by applying a LOW-level pulse on RSTN.
RSTN LRCI Internal reset
OMD=H 8fs
RSTN=L
WCKO
OMD=L 4fs
DOL/DOR
zero
Figure 5. System reset timing and output muting (INF1N = LOW or INF1N = INF2N = HIGH)
NIPPON PRECISION CIRCUITS--18
SM5847AF
Audio Data Input (INF1N, DI/INF2N, IW1N/DIL, IW2N/DIR, BCKI, LRCI)
The input data format and input pin functions are selected by the state of INF1N and INF2N. When INF1N is LOW, the inputs are left and right-channel Input data format select
Table 7. Input settings and functions
Pin function selection INF1N LOW LOW HIGH HIGH DI/INF2N - - LOW HIGH Input format DI/INF2N LR alternating 1 , right-justified data LR alternating, left-justified data LR simultaneous 2 , left-justified data INF2N DIL DIR DI IW1N/DIL IW1N IW2N/DIR IW2N
data inputs, and when INF1N is HIGH, the DI/INF2N input is an input format select pin, and DIL and DIR are the audio data inputs.
1. Alternating left-channel and right-channel data input on a single input DI. 2. S i multaneous left-channel and right-channel data input on two inputs, DIL and DIR, respectively.
Input data word length The input data word length is selected by the state of IW1N and IW2N when INF1N is LOW. 20-bit is selected when INF1N is HIGH.
Table 8. Input data word length select
INF1N IW1N/DIL LOW HIGH LOW LOW HIGH HIGH - HIGH HIGH - 18 bits 16 bits 24 bits IW2N/DIR LOW LOW Input word length 24 bits 20 bits
Jitter-free Function (SYNCN)
The arithmetic circuit and output control timing is derived from the system clock, and is therefore independent of the input LRCI and BCKI clocks. Accordingly, any jitter in the data input clock (LRCI and BCKI) does not cause jitter in the output. Generally, the internal timing is synchronized to the LRCI input timing after a system reset release, when RSTN goes from LOW to HIGH, on the first LRCI clock start edge. If the input timing and LRCI start edge timing subsequently drift, the input timing is automatically resynchronized when the timing error exceeds a certain value. There are 2 timing error values at which resynchronization occurs, selected by the state of SYNCN. Jitter-free mode (SYNCN = HIGH) When SYNCN is HIGH, the timing error value is 3/8 x (LRCI clock period). When the difference between the input timing and LRCI start edge position do not exceed this value, internal timing is not resynchronized and all functions continue to operate normally. Sync mode (SYNCN = LOW) When SYNCN is LOW, the timing error value is 1 x (XTI master clock period), which is a much smaller timing error tolerance than in jitter-free mode. In this mode, the internal timing is guaranteed to follow the LRCI clock timing within this tolerance, making this mode useful for systems constructed from a multiple number of SM5847AF devices.
NIPPON PRECISION CIRCUITS--19
SM5847AF
Audio Data Output (DOL, DOR, BCKO, WCKO, DG, OW1N, OW2N, OMD, DITHN)
Output data format The output data is in serial, simultaneous left and right-channel, 2s complement, MSB first, BCKO burst (NPC format) format. Left-channel data is output on DOL, and right-channel data is output on DOR. Output data word length The output data word length is selected by the state of OW1N and OW2N.
Table 9. Output data word length select
OW1N LOW HIGH LOW HIGH OW2N LOW LOW HIGH HIGH Output word length 24 bits 22 bits 20 bits 18 bits
Output timing The output timing is dependent on the CKSLN level and output data word length. When CKSLN is LOW, the output timing does not change with the output data word length. However, when CKSLN is HIGH, the DOL and DOR output timing for 24-bit output data length (OW1N = OW2N = LOW) start 1 clock cycle earlier than for 18, 20, or 22-bit output data length.
Table 10. Output timing
P arameter Bit clock rate Symbol TB CKSLN HIGH LOW HIGH Data word length TDW LOW OMD = HIGH 1/192fs 1/256fs 24t S Y S 32t S Y S O M D = L OW 1/96fs 1/128fs 48t S Y S 64t S Y S
Output mode The output mode, either 4fs oversampling or 8fs oversampling, is selected by the level on OMD, where fs is the input sampling rate.
Table 11. Output mode select
OMD LOW HIGH Output mode 4fs 8fs
Output dither processing The output data word length is set by OW1N and OW2N, whereas the SM5847AF performs all internal calculations in 25-bit words. As a consequence, dither processing is provided to round-off errors. The SM5847AF uses triangular dither processing (triangular probability density function or TPDF) and can be turned ON or OFF. Simple round-off processing occurs when dither is OFF (DITHN = HIGH).
Table 12. Dither select
DITHN LOW HIGH Dither ON OFF
NIPPON PRECISION CIRCUITS--20
SM5847AF
Group Delay
The data input to data output group delay is the delay which occurs due to the digital filter calculations. It is the time between the serial input data is completely read in (at rate fs) until the serial data is output (at rate 8fs or 4fs, depending on the mode selected).
Table 13. Group delay
Mode CKSLN LOW L O W (256fs) HIGH LOW HIGH (192fs) HIGH Jitter-free mode Jitter-free mode After reset, or sync mode SYNCN After reset, or sync mode G roup delay t O U T P U T - tI N P U T 48.625/fs 48.25/fs - 49.0/fs sec 48.75/fs 48.375/fs - 49.125/fs Unit
tINPUT represents the LRCI clock rising edge after the serial input data has been read in at rate fs. tOUTPUT represents the WCKO clock falling edge at the start of serial data output at rate 8fs or 4fs.
1/fs LRCI serial data input (DI/INF2N, IW1N/DIL, IW2N/DIR) 48/fs
t INPUT
LRCI 1/fs
WCKO 8fs OMD=H CKSLN=L (256fs) WCKO 4fs OMD=L
t OUTPUT
serial data output (DOL,DOR)
t OUTPUT
WCKO 8fs OMD=H CKSLN=H (192fs)
serial data output (DOL,DOR)
t OUTPUT
WCKO 4fs OMD=L
serial data output (DOL,DOR)
t OUTPUT
Figure 6. Group delay timing (SYNCN = LOW)
serial data output (DOL,DOR)
NIPPON PRECISION CIRCUITS--21
SM5847AF
TIMING DIAGRAMS
Input Timing Examples
1 / fs Lch *1 BCKI 16bit
MSB LSB MSB LSB
LRCI
Rch
1 16 1 16
DI/ INF2N
Don't care
Don't care
IW1N/DIL = H, IW2N/DIR = H
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
1
18
1
18
BCKI 18bit DI/ INF2N
MSB LSB MSB LSB
Don't care
Don't care
IW1N/DIL = L, IW2N/DIR = H
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
1
20
1
20
BCKI 20bit DI/ INF2N
MSB LSB MSB LSB
Don't care
Don't care
IW1N/DIL = H, IW2N/DIR = L
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
1
24
1
24
BCKI 24bit DI/ INF2N
MSB LSB MSB LSB
Don't care
Don't care
IW1N/DIL = L, IW2N/DIR = L
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
*1: Optional BCKI clock cycles
Figure 7. LR alternating, right-justified data, 2s complement, MSB first, INF1N = L
NIPPON PRECISION CIRCUITS--22
SM5847AF
1 / fs Lch *1 Rch
LRCI
1
24
1
24
BCKI
MSB LSB
IW1N/DIL
Don't care
Don't care
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
MSB
LSB
IW2N/DIR
Don't care
Don't care
*1: There must be a minimum of 24 BCKI clock cycles. Data input after the LSB is ignored.
Figure 8. LR alternating, left-justified data, 2s complement, MSB first, INF1N = H, DI/INF2N = L, 24-bit
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
1 / fs
LRCI 1 BCKI
MSB LSB
Don't care
24
*1
IW1N/DIL
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 MSB LSB 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
IW2N/DIR
Don't care
*1: There must be a minimum of 24 BCKI clock cycles. Data input after the LSB is ignored.
Figure 9. LR simultaneous, left-justified data, 2s complement, MSB first, INF1N = H, DI/INF2N = H, 24-bit
NIPPON PRECISION CIRCUITS--23
SM5847AF
Output Timing Examples
1 / 8fs
WCKO 1 BCKO 18bit OW1N = H OW2N = H
MSB LSB
18
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
DOL
MSB
LSB
DOR
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
1 BCKO 20bit OW1N = L OW2N = H
MSB
20
LSB
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
DOL
MSB
LSB
DOR
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
1 BCKO 22bit OW1N = H OW2N = L
MSB
22
LSB
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
DOL
MSB
LSB
DOR
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
1 BCKO 24bit OW1N = L OW2N = L
MSB
24
LSB
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 MSB LSB 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
DOL
DOR
DG 192fs internal system clock 1 10 12 22 24
TB TDW
Figure 10. 2s complement, MSB first, CKSLN = H, OMD = H
NIPPON PRECISION CIRCUITS--24
SM5847AF
1 / 4fs
WCKO 1 BCKO 18bit OW1N = H OW2N = H
MSB LSB
18
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
DOL
MSB
LSB
DOR
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
1 BCKO 20bit OW1N = L OW2N = H
MSB
20
LSB
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
DOL
MSB
LSB
DOR
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
1 BCKO 22bit OW1N = H OW2N = L
MSB
22
LSB
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
DOL
MSB
LSB
DOR
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
1 BCKO 24bit OW1N = L OW2N = L
MSB
24
LSB
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 MSB LSB 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
DOL
DOR
DG 192fs internal system clock 2 20 24
44 48
TB TDW
Figure 11. 2s complement, MSB first, CKSLN = H, OMD = L
NIPPON PRECISION CIRCUITS--25
SM5847AF
1 / 8fs
WCKO 1 BCKO 18bit OW1N = H OW2N = H
MSB LSB
18
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
DOL
MSB
LSB
DOR
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
1 BCKO 20bit OW1N = L OW2N = H
MSB
20
LSB
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
DOL
MSB
LSB
DOR
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
1 BCKO 22bit OW1N = H OW2N = L
MSB
22
LSB
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
DOL
MSB
LSB
DOR
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
1 BCKO 24bit OW1N = L OW2N = L
MSB
24
LSB
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
DOL
MSB
LSB
DOR
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
DG 256fs internal system clock 1 14 16 25 30 32
TB TDW
Figure 12. 2s complement, MSB first, CKSLN = L, OMD = H
NIPPON PRECISION CIRCUITS--26
SM5847AF
1 / 4fs
WCKO 1 BCKO 18bit OW1N = H OW2N = H
MSB LSB
18
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
DOL
MSB
LSB
DOR
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
1 BCKO 20bit OW1N = L OW2N = H
MSB
20
LSB
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
DOL
MSB
LSB
DOR
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
1 BCKO 22bit OW1N = H OW2N = L
MSB
22
LSB
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
DOL
MSB
LSB
DOR
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
1 BCKO 24bit OW1N = L OW2N = L
MSB
24
LSB
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
DOL
MSB
LSB
DOR
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
DG 256fs internal system clock 2 28 32 50 60 64
TB TDW
Figure 13. 2s complement, MSB first, CKSLN = L, OMD = L
NIPPON PRECISION CIRCUITS--27
SM5847AF
TYPICAL APPLICATION (1)
This circuit shows a basic connection to a 24-bit input DAC (SM5865BM). 36.864 MHz external clock, 48/96/192 kHz sampling rate fs, 24-bit data, 8fs oversampling operation (Note that certain circuit details required for good DAC analog output characteristics have been omitted.)
+5V 36.864MHz fs 24-bit Data Bit Clock +5V
1 2 3 4 22 23 21 20 19 18 17 16 15 14 13 12 11 10 VDD VDDAC VSSAC 9 8 7 6 5 4 3 2 1 1 2 3 4 5 6
DVSS DI BCKI AVSSA RAP IOUTA
SM5865BM
DVSS DI BCKI AVSSA RAP IOUTA
24 23 22 21 20 19 18
I/V Converter
WCKI IOUTAN IWSL RSTN TSTN TO DVDD RAN AVDDA AVDDB
5 6 7 8 9
VSS
BCKI
DI/INF2N
LRCI
VDD
XTO
24 CKSLN 25 INF1N 26 IW1N/DIL 27 IW2N/DIR 28 VSS 29 VDD 30 OW1N 31 OW2N
VDD
VSS
XTI
RBP 17 IOUTB IOUTBN RBN
16 15 14
I/V Converter
10 CKI 11 CKDVN 12 CVSS
SM5847AF
VSS BCKO WCKO DOL DOR
AVSSB 13
24 23 22 21 20 19 18
CKDV1
CKDV2
32 33
VDD
VSS
OMD 40 41 42 43 44
I/V Converter
34
35
36
37
38
39
WCKI IOUTAN IWSL RSTN TSTN TO DVDD RAN AVDDA AVDDB
CKDV1 CKDV2 OMD RSTN
7 8 9
RBP 17 IOUTB IOUTBN RBN
16 15 14
I/V Converter
10 CKI 11 CKDVN 12 CVSS
AVSSB 13
SM5865BM
Figure 14. SM5847AF and SM5865BM connection
Table 14. Operating mode select
Internal system clock frequency divider ratio select Sampling frequency fs (kHz) Mode 48 96 192 768fs 384fs 192fs Output mode select CKSLN = HIGH (192fs) C K DV1 HIGH HIGH LOW C K DV2 LOW HIGH LOW Divider 4 2 1 OMD HIGH HIGH HIGH Output mode 8fs 8fs 8fs 36.864 External clock XTI (MHz)
NIPPON PRECISION CIRCUITS--28
SM5847AF
TYPICAL APPLICATION (2)
This circuit shows a basic connection to a 24-bit input DAC (Burr-Brown PCM1704U). 36.864 MHz external clock, 48/96/192 kHz sampling rate fs, 24-bit data, 8fs or 4fs oversampling operation (Note that certain circuit details required for good DAC analog output characteristics have been omitted.)
36.864MHz fs 24-bit Data Bit Clock +5V -5V
1 22 23 21 BCKI 20 DI/INF2N 19 LRCI 18 VDD 17 VSS 16 XTI 15 XTO 14 VDD 13 VSS 12 11 10 VDD VDDAC VSSAC 9 8 7 6 5 4 3 2 1 1 2 3 4 5 2 3 4 5 6 7 8 9
DATA BCLK
-VCC 20 19 18 17 AGND 16 AGND 15 IOUT 14 13
PCM1704U
-V DD DGND +V DD WCLK
24 CKSLN 25 INF1N 26 IW1N/DIL 27 IW2N/DIR 28 VSS 29 VDD 30 OW1N 31 OW2N CKDV1 CKDV2 32 33
I/V Converter
SM5847AF
VSS BCKO WCKO DOL DOR
20BIT
12
10 INVERT +VCC 11
DATA BCLK
-VCC 20 19 18 17 AGND 16 AGND 15 IOUT 14 13
VDD
VSS
OMD 40 41 42 43 44
34
35
36
37
38
39
PCM1704U
-VDD DGND +VDD WCLK
CKDV1 CKDV2 OMD RSTN +5V
6 7 8 9 10
I/V Converter
20BIT
12
INVERT +VCC 11
Figure 15. SM5847AF and Burr-Brown PCM1704U connection
Table 15. Operating mode select
Internal system clock frequency divider ratio select Sampling frequency fs (kHz) Mode 48 96 192 768fs 384fs 192fs Output mode select CKSLN = HIGH (192fs) C K DV1 HIGH HIGH LOW C K DV2 LOW HIGH LOW Divider 4 2 1 OMD HIGH HIGH LOW Output mode 8fs 8fs 4fs 36.864 External clock XTI (MHz)
NIPPON PRECISION CIRCUITS--29

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