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DAC716
16-Bit DIGITAL-TO-ANALOG CONVERTER with Serial Data Interface
FEATURES:
q SERIAL DIGITAL INTERFACE q VOLTAGE OUTPUT: 0 to +10V q 2 LSB INTEGRAL LINEARITY q PRECISION INTERNAL REFERENCE q LOW NOISE: 120nV/Hz Including Reference q 16-LEAD PLASTIC SKINNY DIP AND PLASTIC SOIC PACKAGES
DESCRIPTION
The DAC716 is a complete monolithic D/A converter including a +10V temperature compensated voltage reference, current-to-voltage amplifier, a high-speed synchronous serial interface, a serial output which allows cascading multiple converters, and an asynchronous clear function which immediately sets the output voltage to zero. The output voltage range is 0 to +10V while operating from 12V to 15V supplies, and the gain and bipolar offset adjustments are designed so that they can be set via external potentiometers or external D/A converters. The output amplifier is protected against shortcircuiting to ground. The 16-pin DAC716 is available in a plastic 0.3" DIP and a wide-body plastic SOIC package. The DAC716P, U, PB, and UB are specified over the -40C to +85C range while the DAC716UK and PK are specified over the 0C to +70C range.
A0 A1 SDI CLK CLR 16 Input Shift Register 16 SDO
D/A Latch
Reference Circuit
16-Bit D/A Converter VOUT Offset Adjust
Gain Adjust
VREF OUT +10V
International Airport Industrial Park * Mailing Address: PO Box 11400, Tucson, AZ 85734 * Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 * Tel: (520) 746-1111 * Twx: 910-952-1111 Internet: http://www.burr-brown.com/ * FAXLine: (800) 548-6133 (US/Canada Only) * Cable: BBRCORP * Telex: 066-6491 * FAX: (520) 889-1510 * Immediate Product Info: (800) 548-6132
(c) 1996 Burr-Brown Corporation
PDS-1324B
Printed in U.S.A. March, 1998
SPECIFICATIONS
At TA = +25C, +VCC = +15V, -VCC = -15V, unless otherwise noted. DAC716P, U PARAMETER TRANSFER CHARACTERISTICS ACCURACY Linearity Error TMIN to TMAX Differential Linearity Error TMIN to TMAX Monotonicity Monotonicity Over Spec Temp Range Gain Error(3) TMIN to TMAX Unipolar Zero Error (3) TMIN to TMAX Power Supply Sensitivity of Gain DYNAMIC PERFORMANCE Settling Time (to 0.003%FSR, 5kW || 500pF Load)(4) 20V Output Step 1LSB Output Step(5) Output Slew Rate Total Harmonic Distortion 0dB, 1001Hz, fS = 100kHz -20dB, 1001Hz, fS = 100kHz -60dB, 1001Hz, fS = 100kHz SINAD: 1001Hz, f S = 100kHz Digital Feedthrough(5) Digital-to-Analog Glitch Impulse(5) Output Noise Voltage (includes reference) ANALOG OUTPUT Output Voltage Range +VCC, -VCC = 11.4V Output Current Output Impedance Short Circuit to ACOM Duration REFERENCE VOLTAGE Voltage TMIN to TMAX Output Resistance Source Current Short Circuit to ACOM Duration INTERFACE RESOLUTION DIGITAL INPUTS Serial Data Input Code Logic Levels(1) VIH VIL IIH (VI = +2.7V) IIL (VI = +0.4V) DIGITAL OUTPUT Serial Data VOL (ISINK = 1.6mA) VOH (ISOURCE = 500A),TMIN to TMAX POWER SUPPLY REQUIREMENTS Voltage +VCC -VCC Current (No Load, 15V Supplies)(6) +VCC -VCC Power Dissipation(7) TEMPERATURE RANGES Specification All Grades Storage Thermal Coefficient, JA T Specifications are the same as the grade to the left. NOTES: (1) Digital inputs are TTL and +5V CMOS compatible over the specification temperature range. (2) FSR means Full Scale Range. For example, for 0 to +10V output, FSR = 10V. (3) Errors externally adjustable to zero. (4) Maximum represents the 3 limit. Not 100% tested for this parameter. (5) For the worst-case Straight Binary code changes: 7FFF to 8000 and 8000 to 7FFF. (6) During power supply turn on, the transient supply current may approach 3x the maximum quiescent specification. (7) Typical (i.e. rated) supply voltages times maximum currents.
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DAC716PB, UB MAX MIN TYP MAX MIN
DAC716PK, UK TYP MAX UNITS
MIN
TYP
4 8 4 8 14 13 0.1 0.25 0.1 0.2 0.003 30 15 14
2 4 2 4 15 15 T T T T T T
2 2 2 2
T T T T T T
LSB LSB LSB LSB Bits Bits % % % of FSR(2) % of FSR %FSR/%VCC ppm FSR/%VCC
6 4 10 0.005 0.03 3.0 87 2 15 120
10
T T T T T T T T T T
T
T T T T T T T T T T
T
s s V/s % % % dB nV-s nV-s nV/Hz
+10 5 0.1 Indefinite +9.975 +9.960 2 Indefinite 16 +10.000 1 +10.025 +10.040
T T T T T T T T T T T T T
T T T T T T T T T T T T T
V mA W
V V W mA
Bits
Srih Bnr tagt iay +2.0 0 (VCC -1.4) +0.8 10 10 T T T T T T T T T T T T V V A A
0 +2.4
+0.4 +5
T T
T T
T T
T T
V V
+11.4 -11.4
+15 -15 13 22
+16.5 -16.5 16 26 625
T T
T T T T
T T T T T
T T
T T T T
T T T T T
V V mA mA mW
-40 -60 75
+85 +150
T T T
T T
0 T T
+70 T
C C C/W
DAC716
2
PIN CONFIGURATION
Top View SOIC/DIP
PIN DESCRIPTIONS
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 LABEL CLK A0 A1 SDI SDO DCOM +VCC ACOM VOUT NC NC VREF OUT Offset Adjust Gain Adjust -VCC CLR DESCRIPTION Serial Data Clock Enable for Input Register (Active Low) Enable for D/A Latch (Active Low) Serial Data Input Serial Data Output Digital Supply Ground Positive Power Supply Analog Supply Ground D/A Output No Connection No Connection Voltage Reference Output Offset Adjust Gain Adjust Negative Power Supply Clear
CLK A0 A1 SDI SDO DCOM +VCC ACOM
1 2 3 4 DAC716 5 6 7 8
16 CLR 15 -VCC 14 Gain Adjust 13 Offset Adjust 12 VREF OUT 11 NC 10 NC 9 VOUT
ELECTROSTATIC DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. BurrBrown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. ABSOLUTE MAXIMUM RATINGS(1)
+VCC to Common .................................................................... 0V to +17V -VCC to Common .................................................................... 0V to -17V +VCC to -VCC ....................................................................................... 34V ACOM to DCOM ............................................................................... 0.5V Digital Inputs to Common ............................................. -1V to (VCC -0.7V) External Voltage Applied to BPO and Range Resistors ..................... VCC VREF OUT ......................................................... Indefinite Short to Common VOUT ............................................................... Indefinite Short to Common SDO ............................................................... Indefinite Short to Common Power Dissipation .......................................................................... 750mW Storage Temperature ...................................................... -60C to +150C Lead Temperature (soldering, 10s) ................................................ +300C NOTE: (1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability.
ORDERING INFORMATION
DIFFERENTIAL LINEARITY ERROR TMIN to TMAX 8 8 4 4 2 2 LSB LSB LSB LSB LSB LSB TEMPERATURE RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C 0C to +70C 0C to +70C
PRODUCT DAC716P DAC716U DAC716PB DAC716UB DAC716PK DAC716UK
PACKAGE Plastic DIP Plastic SOIC Plastic DIP Plastic SOIC Plastic DIP Plastic SOIC
PACKAGE INFORMATION
PRODUCT DAC716P DAC716U PACKAGE Plastic DIP Plastic SOIC PACKAGE DRAWING NUMBER(1) 180 211
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
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3
DAC716
TIMING SPECIFICATIONS
TA = -40C to +85C, +VCC = +15V, -VCC = -15V. SYMBOL tCLK tCL tCH tA0S tA1S tAOH tA1H tDS tDH tDSOP tCP PARAMETER Data Clock Period Clock LOW Clock HIGH Setup Time for A0 Setup Time for A1 Hold Time for A0 Hold Time for A1 Setup Time for DATA Hold Time for DATA Output Propagation Delay Clear Pulsewidth MIN 100 50 50 50 50 10 10 50 10 140 200 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns
TRUTH TABLE
A0 0 1 1 0 X X A1 1 0 1 0 X X CLK 101 101 101 101 1 X CLR 1 1 1 1 1 0 DESCRIPTION Shift Serial Data into SDI Load D/A Latch No Change Two Wire Operation(1) No Change Reset D/A Latch
NOTES: X = Don't Care. (1) All digital input changes will appear at the D/A output.
TIMING DIAGRAMS Serial Data In
tCLK tCH CLK tA A0 tDS Serial Data Input MSB First SDI D15 tDH D14 D0 tA Latch Data In D/A Latch A1 tCP CLR
1S
tCL
0S
tA
0H
tA
1H
Serial Data Out
tCLK tCH CLK tA A0
0S
tCL
tA
0H
tDS Serial Data Out SDO tDSOP D15 D14 tDSOP D0
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DAC716
4
TYPICAL PERFORMANCE CURVES
At TA = +25C, VCC = 15V, unless otherwise noted.
[Change in FSR]/[Change in Supply Voltage] (ppm of FSR/ %)
POWER SUPPLY REJECTION vs POWER SUPPLY RIPPLE FREQUENCY 1k
LOGIC vs V LEVEL 2.0
-VCC
+VCC 10
I Digital Input (A)
100
1.0
A0, A1 CLR
0 SDI -1.0
1
0.1 10 100 1k 10k 100k 1M Frequency (Hz)
-2.0 -0.85
0
0.85 1.7 2.55
3.4 4.25
5.1 5.95
6.8
V Digital Input
FULL SCALE OUTPUT SWING
2500 2000 1500
SETTLING TIME, +10V TO 0V +5V 0V
A1
(R)
10
Around 0 (V)
1000 500 0 -500 -1000 -1500
VOUT (V)
FPO
0 Time (10s/div)
-2000 -2500 Time (1s/div)
SETTLING TIME, 0V TO +10V 2500
1000
VOUT SPECTRAL NOISE DENSITY
1500
-0V
Around +10V (V)
1000
A1
2000
+5V
100
0 -500 -1000 -1500 -2000 -2500 Time (1s/div)
nV/Hz
10 1 1 10 100 1k 10k 100k 1M 10M Frequency (Hz)
500
5
DAC716
DISCUSSION OF SPECIFICATIONS
LINEARITY ERROR Linearity error is defined as the deviation of the analog output from a straight line drawn between the end points of the transfer characteristic. DIFFERENTIAL LINEARITY ERROR Differential linearity error (DLE) is the deviation from 1LSB of an output change from one adjacent state to the next. A DLE specification of 1/2LSB means that the output step size can range from 1/2LSB to 3/2LSB when the digital input code changes from one code word to the adjacent code word. If the DLE is more positive than -1LSB, the D/A is said to be monotonic. MONOTONICITY A D/A converter is monotonic if the output either increases or remains the same for increasing digital input values. Monotonicity of the K grade is guaranteed over the specification temperature range to 15 bits. SETTLING TIME Settling time is the total time (including slew time) for the D/A output to settle to within an error band around its final value after a change in input. Settling times are specified to within 0.003% of Full Scale Range (FSR) for an output step change of 10V and 1LSB. The 1LSB change is measured at the Major Carry (7FFF to 8000, and 8000 to 7FFF: Straight Binary codes), the input transition at which worstcase settling time occurs. TOTAL HARMONIC DISTORTION + NOISE Total harmonic distortion + noise is defined as the ratio of the square root of the sum of the squares of the values of the harmonics and noise to the value of the fundamental frequency. It is expressed in % of the fundamental frequency amplitude at sampling rate fS. SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) SINAD includes all the harmonic and outstanding spurious components in the definition of output noise power in addition to quantizing and internal random noise power. SINAD is expressed in dB at a specified input frequency and sampling rate, fS. DIGITAL-TO-ANALOG GLITCH IMPULSE The amount of charge injected into the analog output from the digital inputs when the inputs change state. It is measured at half scale at the input codes where as many as possible switches change state--from 8000 to 7FFF.
DIGITAL FEEDTHROUGH When the A/D is not selected, high frequency logic activity on the digital inputs is coupled through the device and shows up as output noise. This noise is digital feedthrough.
OPERATION
The DAC716 is a monolithic integrated-circuit 16-bit D/A converter complete with 16-bit D/A switches and ladder network, voltage reference, output amplifier and a serial interface. INTERFACE LOGIC The DAC716 has double-buffered data latches. The input data latch holds a 16-bit data word before loading it into the second latch, the D/A latch. This double-buffered organization permits simultaneous update of several D/A converters. All digital control inputs are active low. Refer to block diagram of Figure 1. All latches are level-triggered. Data present when the enable inputs are logic "0" will enter the latch. When the enable inputs return to logic "1", the data is latched. The CLR input resets both the input latch and the D/A latch to give an output voltage of 0V (code 0000). LOGIC INPUT COMPATIBILITY DAC716 digital inputs are TTL compatible (1.4V switching level) with low leakage, high impedance inputs. Thus the inputs are suitable for being driven by any type of 5V logic such as 5V CMOS logic. An equivalent circuit of a digital input is shown in Figure 2. Data inputs will float to logic "0" and control inputs will float to logic "0" if left unconnected. It is recommended that any unused inputs be connected to DCOM to improve noise immunity. Digital inputs remain high impedance when power is off. INPUT CODING The DAC716 is designed to accept Straight Binary (SB) input codes. The serial input format is MSB first. INTERNAL REFERENCE DAC716 contains a +10V reference. The reference output may be used to drive external loads, sourcing up to 2mA. The load current should be constant, otherwise the gain and unipolar offset of the converter will vary. OUTPUT VOLTAGE SWING The output amplifier of DAC716 is designed to achieve a +10V output range. DAC716 will provide a +10V output swing while operating on 11.4V or higher voltage supplies.
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DAC716
6
Gain Adjust 14
VREF OUT 12
+VCC 7
- VCC 15
180 +10V Reference
10 11
NC NC
15k
13 9.75k +2.5V -VCC D/A Switches CLK 1 9 DAC Latch 16 Shift Register 5k
Offset Adjust
VOUT
A1 CLR A0 SDI SDO
3 16 2 4 5
8 ACOM
6 DCOM
FIGURE 1. DAC716 Block Diagram.
+VCC
ESD Protection Circuit R = 1k: A0, A1, CLK, CLR, SDI R
Full Scale Range Gain Adjust Rotates the Line + Full Scale 1LSB Range of Gain Adjust 0.3%
Digital Input
6.8V -VCC
5pF
FIGURE 2. Equivalent Circuit of Digital Inputs. GAIN AND OFFSET ADJUSTMENTS Figure 3 illustrates the relationship of offset and gain adjustments for a unipolar connected D/A converter. Offset should be adjusted first to avoid interaction of adjustments. See Table I for calibration values and codes. These adjustments have a minimum range of 0.3%. Offset Adjustment Apply the digital input code, 0000, that produces 0V and adjust the offset potentiometer or the offset adjust D/A converter for 0V.
Range of Offset Adjust Offset Adj. Translates the Line 0.3% Zero
Analog Output
0000H
8000H Digital Input
FFFFH
FIGURE 3. Relationship of Offset and Gain Adjustments. Gain Adjustment Apply the digital input that gives the maximum positive voltage output. Adjust the gain potentiometer or the gain adjust D/A converter for this positive full scale voltage.
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7
DAC716
DAC716 CALIBRATION VALUES 1 LEAST SIGNIFICANT BIT = 152V DIGITAL INPUT CODE STRAIGHT BINARY FFFFH | 8000H 0000H ANALOG OUTPUT (V) UNIPOLAR 10V RANGE +9.999695 +5.000000 0.000000 DESCRIPTION + Full Scale -1LSB Half Scale
1 2 3 4 DAC716 5 Unipolar Zero 6 +12V to +15V 7 1F + 8 +VCC ACOM DCOM
16 -12V to -15V -VCC 15 14 13 12 11 10 9 + 1F
TABLE I. Digital Input and Analog Output Voltage Calibration Values.
INSTALLATION
GENERAL CONSIDERATIONS Due to the high precision of these D/A converters, system design problems such as grounding and contact resistance become very important. A 16-bit converter with a 10V fullscale range has a 1LSB value of 152V. With a load current of 5mA, series wiring and connector resistance of only 60m will cause a voltage drop of 300V. To understand what this means in terms of a system layout, the resistivity of a typical 1 ounce copper-clad printed circuit board is 1/2 m per square. For a 5mA load, a 0.1 inch wide printed circuit conductor 0.6 inches long will result in a voltage drop of 150V. The analog output of DAC716 has an LSB size of 152V (-96dB). The rms noise floor of the D/A should remain below this level in the frequency range of interest. The DAC716's output noise spectral density (which includes the noise contributed by the internal reference) is shown in the Typical Performance Curves section. Wiring to high-resolution D/A converters should be routed to provide optimum isolation from sources of RFI and EMI. The key to elimination of RF radiation or pickup is small loop area. Signal leads and their return conductors should be kept close together such that they present a small capture cross-section for any external field. Wire-wrap construction is not recommended. POWER SUPPLY AND REFERENCE CONNECTIONS Power supply decoupling capacitors should be added as shown in Figure 4. Best performance occurs using a 1 to 10F tantalum capacitor at -VCC. Applications with less critical settling time may be able to use 0.01F at -VCC as well as at +V CC. The capacitors should be located close to the package. The DAC716 has separate ANALOG COMMON and DIGITAL COMMON pins. The current through DCOM is mostly switching transients and are up to 1mA peak in amplitude. The current through ACOM is typically 5A for all codes. Use separate analog and digital ground planes with a single interconnection point to minimize ground loops. The analog FIGURE 4. Power Supply Connections. pins are located adjacent to each other to help isolate analog from digital signals. Analog signals should be routed as far as possible from digital signals and should cross them at right angles. A solid analog ground plane around the D/A package, as well as under it in the vicinity of the analog and power supply pins, will isolate the D/A from switching currents. It is recommended that DCOM and ACOM be connected directly to the ground planes under the package. If several DAC716s are used or if the DAC716 shares supplies with other components, connecting the ACOM and DCOM lines together at the power supplies only rather than at each chip, may give better results. LOAD CONNECTIONS Since the reference point for VOUT and VREF OUT is the ACOM pin, it is important to connect the D/A converter load directly to the ACOM pin. Refer to Figure 5. Lead and contact resistances are represented by R1 through R3. As long as the load resistance RL is constant, R1 simply introduces a gain error and can be removed by gain adjustment of the D/A or system-wide gain calibration. R2 is part of RL if the output voltage is sensed at ACOM. In some applications it is impractical to return the load to the ACOM pin of the D/A converter. Sensing the output voltage at the SYSTEM GROUND point is reasonable, because there is no change in DAC716 ACOM current, provided that R3 is a low-resistance ground plane or conductor. In this case you may wish to connect DCOM to SYSTEM GROUND as well. GAIN AND OFFSET ADJUST Connections Using Potentiometers GAIN and OFFSET adjust pins provide for trim using external potentiometers. 15-turn potentiometers provide sufficient resolution. Range of adjustment of these trims is at least 0.3% of Full Scale Range. Refer to Figure 6.
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DAC716
8
Using D/A Converters The GAIN ADJUST and OFFSET ADJUST circuits of DAC716 have been arranged so that these points may be easily driven by external D/A converters. Refer to Figure 7. 12-bit D/A converters provide a nominal OFFSET adjust and GAIN adjust resolution of 25V and 15V per LSB step, respectively. Nominal values of GAIN and OFFSET occur when the D/A converters outputs are at approximately half scale, 0V. OUTPUT VOLTAGE RANGE CONNECTIONS The DAC716 output amplifier is connected internally for 10V output range.
DIGITAL INTERFACE
SERIAL INTERFACE The DAC716 has a serial interface with two data buffers which can be used for either synchronous or asynchronous updating of multiple D/A converters. A0 is the enable control for the Data Input Latch. A1 is the enable for the D/A Latch. CLK is used to strobe data into the latches enabled by A0 and A1. A CLR function is also provided and when enabled it sets both the Data Latch and the D/A Latch to all zeros . Multiple DAC716s can be connected to the same CLK and data lines in two ways. The output of the serial loaded data latch is available as SDO so that any number of DAC716s can be cascaded on the same input bit stream as shown in Figure 8 and 9. This configuration allows all D/A converters to be updated simultaneously and requires a minimum number of control signal inputs. These configurations do require 16N CLK cycles to load any given D/A converter, where N is the number of D/A converters. The DAC716 can also be connected in parallel as shown in Figure 10. This configuration allows any D/A converter in the system to be updated in a maximum of 16 CLK cycles.
DAC716 SDI A0 A1 CLR
VREF OUT Offset Adjust
VREF
9.75k
5k
Bus Interface
VOUT R1
RL
Sense Output
DCOM
ACOM R2
R3
Alternate Ground Sense Connection To +VCC 0.01F(1) 0.01F Analog Power Supply
System Ground
To -VCC NOTE: (1) Locate close to DAC716 package.
FIGURE 5. System Ground Considerations for High-Resolution D/A Converters.
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9
DAC716
Internal +10V Reference
VREF OUT 12
P1 1k 180 R1 100 Gain Adjust Offset Adjust 14 13 R2 1M +VCC
P2 10k to 100k
15k
9.75k 5k
R3 27k
-VCC
IDAC 0-2mA 8 ACOM
9
10V VOUT
For no external adjustments, pins 13 and 14 are not connected. External resistors R1 - R3 are standard 1% values. Range of adjustment at least 0.3% FSR.
FIGURE 6. Manual Offset and Gain Adjust Circuits.
Internal +10V Reference
VREF OUT 12
180
R1 392 Gain Adjust 14
Offset Adjust 13 15k 9.75k R2 33k 5k R3 1M -10 to +10V DAC 10V
IDAC 0-2mA
9 +10V VOUT
-10 to +10V
DAC 10V
DAC716
For no external adjustments, pins 13 and 14 are not connected. External resistors R1 - R3 tolerance: 1%. Range of adjustment at least 0.3% FSR.
FIGURE 7. Gain and Offset Adjustment Using D/A Converters.
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DAC716
10
Data Data Latch Up Date CLK
4 2 3 1 +5V 16
SDI A0 DAC716 A1 DAC 1 CLK CLR SDO 5
4 2 3 1 +5V 16
SDI A0 DAC716 A1 DAC 2 CLK CLR SDO 5
4 2 3 1 +5V 16
SDI A0 A1 CLK CLR DAC716 DAC 3 SDO 5 To other DACs
FIGURE 8a. Cascaded Serial Bus Connection with Synchronous Update.
DAC 3
DAC 2
DAC 1
Clock Data Data Latch
FEDCBA9 8 7 6 5 4 3210FEDCBA9876543 21 0 FEDCBA 9 8 7 6 5 4 3 2 1 0
Update
FIGURE 8b. Timing Diagram For Figure 8a.
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11
DAC716
Data Data Latch Up Date
4 2 3 1 16 +5V
SDI A0 DAC716 A1 DAC 1 CLK CLR SDO 5
4 2 3 1 16 +5V
SDI A0 DAC716 A1 DAC 2 CLK CLR SDO 5
4 2 3 1 16 +5V
SDI A0 DAC716 A1 DAC 3 CLK CLR SDO 5 To other DACs
FIGURE 9a. Cascaded Serial Bus Connection with Asynchronous Update.
DAC 3
DAC 2
DAC 1
Data Latch Data Update
FEDCBA9 8 7 6 5 4 3210FEDCBA9876543 21 0 FEDCBA 9 8 7 6 5 4 3 2 1 0
FIGURE 9b. Timing Diagram For Figure 9a.
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DAC716
12
Data Data Latch 1 Up Date CLK
4 2 3 1 16
SDI A0 DAC716 A1 DAC 1 CLK CLR SDO 5
CLR
4 Data Latch 2 2 3 1 16
SDI A0 DAC716 A1 DAC 2 CLK CLR SDO 5
4 Data Latch 3 2 3 1 16
SDI A0 DAC716 A1 DAC 3 CLK CLR SDO 5
FIGURE 10a. Parallel Bus Connection.
DAC 1
DAC 2
DAC 3
Clock Data Data Latch 1 Data Latch 2 Data Latch 3 Update
FEDCBA9 8 7 6 5 4 3210FEDCBA9876543 21 0 FEDCBA 9 8 7 6 5 4 3 2 1 0
FIGURE 10b. Timing Diagram For Figure 10a.
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13
DAC716

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