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| CCD Delay Line Series MN3885S NTSC-Compatible CCD Video Signal Delay Element Overview The MN3885S is a CCD signal delay element for video signal processing applications. It contains such components as a shift register clock driver, charge I/O blocks, two CCD delay elements, a clamp bias circuit, resampling output amplifiers, and booster circuits. The MN3885S samples the input using the supplied clock signal with a frequency 7.15909 MHz of twice the NTSC color signal subcarrier frequency, and after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period) each for the two lines. Pin Assignment VOC VDD VSS VOY 1 2 3 4 8 7 6 5 VINC XI VBB VINY ( TOP VIEW ) SOP008-P-0225A Features Single 5.0 V power supply Single chip combining luminance signal delay line and delay line for color signal converted to the low frequency. Low EMI levels from clock during driving Applications VCRs, Video cameras Structure and Operation The MN3885S consists of the operational blocks shown in the block diagram. The shift register has the structure shown in the supplementary diagram. Shift register clock driver This block generates two transfer clock signals, o1 and o2, synchronized with the 7.15909 MHz input clock signal. It also generates the sampling clock signals oS and oS', resampling clock signal oSH, and reset clock signal oR based on the timing control. Charge Input blocks These blocks alter the analog input signals from the VINC and VINY pins on their way to the shift registers. One adds the bias voltage specified with the bias circuit to the analog signal from the VINC pin. The other applies an "L" level clamp voltage from the clamp circuit to the analog signal from the VINY pin. Analog shift registers These blocks sample the shift register input signals with the sampling clock, and convert the results to charges, and use transfer clocks o1 and o2 to transfer the results to the following block. Charge detection blocks These convert the signal charges from the final stage of the analog shift registers into voltage signals. Resampling output amplifiers In the output stage of this blocks, the voltage signal is executed Sample-and-Hold by resampling, and is outputted at signal output pin of VOC (1-pin) and VOY (4-pin). Bias circuit This circuit applies a bias voltage to the analog signal from VINC (pin 8) to optimize it for the shift register. Clamp circuit This circuit applies an "L" level clamp to the analog signal from VINY (pin 5) to optimize it for the shift register. Booster circuits These generate reset drain voltages. 1 MN3885S Block Diagram CCD Delay Line Series Bias circuit VINC 8 Charge input block CCD 454 stages Charge detection block 2V DD 3V SS Resampling output amplifier 1 VOC oS driver o1 driver o2 driver oR driver oSH driver oSH driver Timing adjustment XI 7 Waveform amplifier adjustment block oS' driver VINY 5 Charge input block Clamp circuit Substrate bias generator CCD 453.5 stages Charge detection block Resampling output amplifier 4 VOY 2 VBB 6 CCD Delay Line Series Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 Symbol VOC VDD VSS VOY VINY VBB XI VINC Pin Name Signal output (C) Power supply Ground Signal output (Y) Signal input (Y) Substrate connection Clock input Signal input (C) MN3885S Remarks Negative voltage pin Operating Conditions Parameter Power supply Input clock frequency Input clock amplitude (sine wave) Ambient temperature Symbol VDD fck vck Ta 0.2 -20 min 4.75 typ 5.00 7.15909 0.3 1.5 60 max 5.25 Unit V MHz VP-P C Electrical Characteristics VDD=5.0V, Vck=0.3VP-P (sine wave), Vin=0.5VP-P (sine wave), fck=7.15909MHz, Ta=25C Parameter Power supply voltage Signal bandwidth (Y signal) Signal bandwidth (C signal) Insertion gain (Y signal) Insertion gain (C signal) Total harmonic distortion Signal-to-noise ratio Clock leak Crosstalk Delay (Y signal) Delay (C signal) VO pin output impedance Input bias voltage Input clamp voltage Output bias voltage Output clamp voltage Substrate voltage Symbol Conditions min 1.8 1.8 0.0 -1.0 48 IDD BWY -3 dB for 200 kHz value BWC -3 dB for 200 kHz value IGY IGC S/N NC CT DY DC ZOY ZOC VBIN Applied to input from C signal input pin VCLIN Applied to input from Y signal input pin VBO -VBB Applied to output from C signal output pin typ 18 2.8 2.8 3.0 2.0 1.0 56 -30 -50 63.38 63.46 0.5 0.5 2.86 2.70 2.70 2.40 -2.80 max 36 Unit mA MHz fsig=200kHz fsig=200kHz Signal output (Vp-p)/noise output (rms) 7.16 MHz components for both Y and C signals fsig=200kHz 6.0 5.0 4.5 dB % dB THD fsig=200kHz -10 -35 dB dB s 0.9 0.9 k V V V V V VCLO Applied to output from Y signal output pin 3 MN3885S VINY Shift Register Configuration CCD Delay Line Series Clamp circuit Booster circuit Voltage generator oS' o1 o2 oR 2 VDD ....... ....... oSH VINY 5 Output amplifier 4 VOY 3 VSS 4 CCD Delay Line Series Application Circuit Example MN3885S 10F - + Bias circuit VINC 8 0.01F Charge input block CCD 454 stages Charge detection block 2 VDD 3 VSS 0.1F 330 Resampling output amplifier 1 VOC 2SA564 oS driver o1 driver o2 driver oR driver oSH driver oSH driver Timing adjustment XI 7 1000pF Waveform amplifier adjustment block oS' driver VINY 5 0.47F Charge input block Clamp circuit Substrate bias generator CCD 453.5 stages Charge detection block 330 Resampling output amplifier 4 VOY 2SA564 VBB 0.01F Note: If the external capacitor attached to pin 6 is a electrolytic capacitor, connect the negative pole to pin 6. 6 5 MN3885S Package Dimensions (Unit:mm) SOP008-P-0225A CCD Delay Line Series 0.4 0.40.25 1 8 5.00.3 1.27 4 5 0.10.1 0.3 4.20.3 6.50.3 6 0.15 0.65 1.50.2 |
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