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ESDA14V2-4BF1
QUAD BIDIRECTIONAL TRANSILTM ARRAY FOR ESD PROTECTION
ASDTM
APPLICATION Where transient overvoltage protection in ESD sensitive equipment is required, such as :

Computers Printers Communication systems and cellular phones Video equipment This device is particularly adapted to the protection of symmetrical signals. DESCRIPTION The ESDA14V2-4BF1 is a monolithic array designed to protect up to 4 lines in a bidirectional way against ESD transients. The device is ideal for situations where board space saving is requested. FEATURES 4 Bidirectional TransilTM functions ESD Protection: IEC61000-4-2 level 4 Stand off voltage: 12 V MIN. Low leakage current < 1 A 50W Peak pulse power (8/20s)
Flip-Chip (5 bumps) FUNCTIONAL DIAGRAM
A1 A3 C1 C3
GND
BENEFITS High ESD protection level High integration Suitable for high density boards
PIN CONFIGURATION (Ball Side)
3 2 1 A B C
COMPLIES WITH THE FOLLOWING STANDARDS: - IEC61000-4-2: 15kV (air discharge) 8kV (contact discharge) - MIL STD 883E- Method 3015-7: class3 25kV (human body model) Order Codes Part Number ESDA14V2-4BF1
Marking EA
May 2004
REV. 2
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ABSOLUTE MAXIMUM RATING (Tamb = 25C) Symbol VPP ESD discharge Parameter MIL STD 883E - Method 3015-7 IEC61000-4-2 air discharge IEC61000-4-2 contact discharge Value 25 15 8 50 125 -55 to +150 260 -40 to +125 Unit kV W C C C C
PPP Tj Tstg TL Top
Peak pulse power (8/20s) Junction temperature Storage temperature range Lead solder temperature (10 seconds duration) Operating temperature range
ELECTRICAL CHARACTERISTICS (Tamb = 25C) Symbol VRM VBR VCL IRM IPP C Rd Parameter Stand-off voltage Breakdown voltage Clamping voltage Leakage current Peak pulse current Capacitance Dynamic resistance
Slope = 1/Rd
I
VBR VCL V RM I RM V
I PP
VBR Part Number min.
V
@ IR max. V 18 mA 1
IRM max. A 1 0.1
@
VRM
Rd typ. note 1
T max. note 2 10 /C 10
-4
C max. 0V bias pF 15
V 12 3
3.2
ESDA14V2-4BF1
14.2
Note 1: Square pulse, IPP = 3A, tp = 2.5s.
Note 2: VBR = T (Tamb -25C) x VBR (25C)
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Fig. 1: Clamping voltage versus peak pulse current (Tj initial = 25C) (Rectangular waveform).
IPP(A)
10.0
tp = 2.5s
Fig. 2: Capacitance versus reverse applied voltage (typical values).
C(pF)
14 12 10 8
F=1MHz VOSC=30mVRMS Tj=25C
1.0 6 4 2
VCL(V)
0.1 0 10 20 30 40 50 60 0 0 2 4 6
VR(V)
8 10 12 14
Fig. 3: Relative variation of leakage current versus junction temperature (typical values).
IR[Tj] / IR[Tj=25C]
1000
100
10
Tj(C)
1 25 50 75 100 125
APPLICATION EXAMPLE
A1
Connector
A3 C1 C3
IC to be protected
B2
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TECHNICAL INFORMATION 1. ESD protection by ESDA14V2-4BF1 With the focus of lowering the operation levels, the problem of malfunction caused by the environment is critical. Electrostatic discharge (ESD) is a major cause of failure in electronic systems. As a transient voltage suppressor, ESDA14V2-4BF1 is an ideal choice for ESD protection by suppressing ESD events. It is capable of clamping the incoming transient to a low enough level such that any damage is prevented on the device protected by ESDA14V2-4BF1. ESDA14V2-4BF1 serves as a parallel protection elements, connected between the signal line and ground. As the transient rises above the operating voltage of the device, the ESDA14V2-4BF1 becomes a low impedance path diverting the transient current to ground. The clamping voltage is given by the following formula: VCL = VBR + Rd.IPP As shown in figure A1, the ESD strikes are clamped by the transient voltage suppressor. Fig. A1: ESD clamping behavior.
Rg Ip Rd Vg VBR Device to be protected V(i/o) R load
ESD Surge
ESDA14V2-4BF1
To have a good approximation of the remaining voltages at both Vi/o side, we provide the typical dynamical resistance value Rd. By taking into account the following hypothesis:
R G > R d ""and""R load > R d
we have:
VG V ( i o ) = V BR + R d x ------RG
The results of the calculation done VG = 8kV, RG = 330 (IEC61000-4-2 standard), VBR = 14.2V (typ.) and Rd = 3.2 (typ.) give:
V ( i o ) = 91.8 Volts
This confirms the very low remaining voltage across the device to be protected. It is also important to note that in this approximation the parasitic inductance effect was not taken into account. This could be a few tenths of volts during a few ns at the Vi/o side.
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Fig. A2: ESD test board.
Fig. A3: ESD test condition.
TEST BOARD
V(i/o)
A1, C1, A3 or C3
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EB14 15
15kV ESD Air discharge
V(i/o)
B2
The measurements done here after show very clearly (figure A4) the high efficiency of the ESD protection: the clamping voltage V(i/o) becomes very close to VBR (positive way, figure A4a) and -VBR (negative way, figure A4b). Fig. A4: Remaining voltage during ESD surge.
V(i/o)
V(i/o)
a: Response in the positive way
b: Response in the negative way
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2. Crosstalk behavior Fig. A5: Crosstalk phenomenon.
RG1
Line 1
VG1 RG2
Line 2
RL1
1VG1 + 12VG2
VG2
RL2
2VG2 + 21VG1
DRIVERS
RECEIVERS
The crosstalk phenomena are due to the coupling between 2 lines. Coupling factors ( 12 or 21 ) increase when the gap across lines decreases, particularly in silicon dice. In the example above, the expected signal on load R L2 is 2VG2, in fact the real voltage at this point has got an extra value 21VG2. This part of the VG1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals. The perturbed line will be more affected if it works with low voltage signal or high load impedance (few k). Fig. A6: Analog crosstalk test configuration. Fig. A7: Typical analog crosstalk response.
Typical crosstalk response of ESDA14V2-4BF1 (A1/A3 line)
0.00 -10.00 -20.00
TEST BOARD
Connected to the port1 of the Network Analyser
A1
-30.00 -40.00
EB14 15
-50.00
Connected to the port2 of the Network Analyser
C3
-60.00 -70.00 -80.00 -90.00 -100.0 100.0k 1.0M 10.0M 100.0M 1.0G
f/Hz
Figure A6 gives the measurement circuit for the analog crosstalk application. In figure A7, the curve shows the effect of the line A1on the line A3. In usual frequency range of analog signals (up to 100 MHz) the effect on disturbed line is less than -30dB.
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Fig. A8: Digital crosstalk test configuration.
A1 0 - 3V Pulse generator f = 5MHz risetime = 3ns unloaded VG1 B2 = GND 21VG1 unloaded C3
Fig. A9: Typical digital crosstalk response.
VG1
rise time: t10-90% = 3ns
21VG1
crosstalk
Figure A8 shows the measurement circuit used to quantify the crosstalk effect in a classical digital application. Figure A9 shows that in such a condition, the impact on the disturbed line is less than 5 mV peak to peak. No data disturbance was noted on the concerned line. The measurements performed with falling edges give an impact within the same range. Fig. A10: Aplac model.
A1 1.2pF 100m 1.2pF 100m A3 1.2pF 100m C1 C3
1.2pF 100m
D02_r BV = 16 IBV = 1m CJO = 200p M = 0.3333 RS = 1 VJ = 0.6 TT = 100n
D02_r
D02_f BV = 16 IBV = 1m CJO = 10.4p M = 0.3333 RS = 2 VJ = 0.6 TT = 100n
B2 B2 50pH 50m 160pH 1.8
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ORDER CODE
ESDA
ESD ARRAY
14V2
VBR min
-
4
B
F
1
Pitch & bump
Nb of lines Flip-Chip Bidirectional
PACKAGE MECHANICAL DATA
315 50 650 65 700 50
1150 50
FOOT PRINT RECOMMENDATIONS
1150 50
49
5
50
MARKING
265
200
Copper pad Diameter : 250m recommended , 300m max
Dot, ST logo xx = marking z = back-end plant yww = datecode (y = year ww = week)
275
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diam 230
1150
Solder stencil opening : 330m
Solder mask opening recommendation : 340m min for 315m copper pad diameter
XXZ YWW
1150
220 40
All dimensions in m
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FLIP-CHIP TAPE AND REEL SPECIFICATION
Dot identifying Pin A1 location 4 +/- 0.1 O 1.5 +/- 0.1
1.75 +/- 0.1 3.5 +/- 0.1
0.73 +/- 0.05
All dimensions in mm
ORDERING INFORMATION Part Number ESDA14V2-4VF1 Marking EA Package Flip Chip Weight 2.1 mg Base qty 5000 Delivery mode Tape & reel
Note: More packing informations are available in the application notes - AN1235: ''Flip-Chip: Package description and recommandations for use'' - AN1751: "EMI Filters: Recommendations and measurements"
8 +/- 0.3
ST
ST
ST
xxz yww
xxz yww
xxz yww
4 +/- 0.1
User direction of unreeling
REVISION HISTORY Table 1: Revision history Date July-2002 27-May-2004 Revision 1 2 First issue Die clearance optimization Description of Changes
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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