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Features
* * * * *
Available in Gate Array or Embedded Array High-speed, 100 ps Gate Delay, 2-input NAND, FO = 2 (nominal) Up to 6.9 Million Used Gates and 976 Pins 0.25 Geometry in up to Five-level Metal System-level Integration Technology - Cores: ARM7TDMITM, ARM920TTM, ARM946E-STM and MIPS64TM 5KfTM RISC Microprocessors; AVR (R) RISC Microcontroller; OakDSPCoreTM, TeakTM and PalmDSPCoreTM Digital Signal Processors; 10/100 Ethernet MAC, USB, 1394, 1284, CAN and Other Assorted Processor Peripherals - Analog Functions: DACs, ADCs, OPAMPs, Comparators, PLLs and PORs - Soft Macro Memory: Gate Array SRAM -- ROM -- DPSRAM -- FIFO - Hard Macro Memory: Embedded Array SRAM -- ROM -- DPSRAM -- FIFO -- Stacked E2 -- Stacked Flash - I/O Interfaces: CMOS, LVTTL, LVDS, PCI, USB; Output Currents up to 16 mA @2.5V; 2.5V Native I/O, 3.3V Tolerant/Compliant I/O, 5.0V Tolerant I/O
ASIC ATL25 Series
Description
The ATL25 Series ASIC family is fabricated on a 0.25 CMOS process with up to five levels of metal. This family features arrays with up to 6.9 million routable gates and 976 pins. The high density and high pin count capabilities of the ATL25 family, coupled with the ability to add embedded microprocessor cores, DSP engines and memory on the same silicon, make the ATL25 series of ASICs an ideal choice for system-level integration. Figure 1. ATL25 Gate Array ASIC
Standard Gate Array Architecture
Figure 2. ATL25 Embedded Array ASIC
Standard Gate Array Architecture
Analog
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Table 1. ATL25 Array Organization
Device Number ATL25/44 ATL25/68 ATL25/84 ATL25/100 ATL25/120 ATL25/132 ATL25/144 ATL25/160 ATL25/184 ATL25/208 ATL25/228 ATL25/256 ATL25/304 ATL25/352 ATL25/388 ATL25/432 ATL25/484 ATL25/540 ATL25/600 ATL25/700 ATL25/800 ATL25/900 ATL25/976 Notes: 4LM Routable Gates(1) 9,535 30,096 50,410 75,472 106,278 131,670 159,778 200,998 270,663 329,281 401,010 512,398 733,635 925,815 1,133,594 1,417,125 1,651,406 2,069,052 2,567,790 3,520,954 4,231,979 5,378,257 5,765,320 5LM Routable Gates(1) 10,727 33,858 56,712 84,906 120,449 149,226 181,081 227,797 306,751 376,321 458,298 585,598 838,440 1,068,248 1,307,994 1,635,145 1,926,640 2,413,894 2,995,755 4,107,780 5,001,430 6,356,122 6,918,384 Available Routing Sites(2) 15,892 50,161 84,018 125,788 188,940 234,080 284,050 357,330 481,179 627,203 763,830 975,998 1,397,400 1,899,108 2,325,323 2,906,925 3,669,792 4,597,895 5,706,200 7,824,344 10,259,344 13,038,200 15,374,188 Max Pad Count 44 68 84 100 120 132 144 160 184 208 228 256 304 352 388 432 484 540 600 700 800 900 976 Max I/O Count 36 60 76 92 112 124 136 152 176 200 220 248 296 344 380 424 476 532 592 692 792 892 968 Gate Speed (3) 100 ps 100 ps 100 ps 100 ps 100 ps 100 ps 100 ps 100 ps 100 ps 100 ps 100 ps 100 ps 100 ps 100 ps 100 ps 100 ps 100 ps 100 ps 100 ps 100 ps 100 ps 100 ps 100 ps
1. One gate = NAND2 2. Routing site = 4 transistors 3. Nominal 2-input NAND gate FO = 2 at 2.5V
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ATL25 Series ASIC
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ATL25 Series ASIC
Design
Atmel supports several major software systems for design with complete cell libraries, as well as utilities for netlist verification, test vector verification and accurate delay simulations Table 2. Design Systems Supported
System Cadence Design Systems, Inc.
(R)
Tools Opus - Schematic and Layout NC VerilogTM - Verilog Simulator PearlTM - Static Path Verilog-XL TM - Verilog Simulator BuildGatesTM - Synthesis (Ambit) ModelSim (R) - Verilog and VHDL (VITAL) Simulator Leonardo Spectrum TM - Logic Synthesis Design CompilerTM - Synthesis DFT Compiler - 1-Pass Test Synthesis BSD Compiler - Boundary Scan Synthesis TetraMax(R) - Automatic Test Pattern Generation PrimeTimeTM - Static Path VCSTM - Verilog Simulator Floorplan ManagerTM Debussy(R) First Encounter(R)
TM
Version 4.46 3.3-s008 4.3-s095 3.3-s006 4.0-p003 5.5e 2001.1d 01.01-SP1 01.08-SP1 01.08-SP1 01.08 01.08-SP1 5.2 01.08-SP1 5.1 v2001.2.3
Mentor Graphics(R) Synopsys(R)
Novas Software, Inc.(R) Silicon PerspectiveTM
Atmel's ASIC design flow is structured to allow the designer to consolidate the greatest number of system components onto the same silicon chip, using widely available third-party design tools. Atmel's cell library reflects silicon performance over extremes of temperature, voltage and process, and includes the effects of metal loading, interlevel capacitance, and edge rise and fall times. The design flow includes clock tree synthesis to customer-specified skew and latency goals. RC extraction is performed on the final design database and incorporated into the timing analysis. The ASIC design flow, shown on page 4, provides a pictorial description of the typical interaction between Atmel's design staff and the customer. Atmel will deliver design kits to support the customer's synthesis, verification, floorplanning and scan insertion activities. Leadingedge tools from vendors such as Synopsys and Cadence are fully supported in our design flow. In the case of an embedded array design, Atmel will conduct a design review with the customer to define the partition of the embedded array ASIC and to define the location of the memory blocks and/or cores so an underlayer layout model can be created. Following database acceptance, automated test pattern generation (ATPG) is performed, if required, on scan paths using Synopsys tools; the design is routed; and post-route RC data is extracted. After post-route verification and a final design review, the design is taped out for fabrication.
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Table 3. Design Flow
Deliver Design Kit
Kickoff Meeting
If Embedded Array
Define Underlayer
Synthesis/ Design Entry
Scan/JTAG
Simulation/ Static Path
Floorplan
If Embedded Array (Preliminary Netlist)
Create Underlayer
Database Handoff
Tape Out Underlayer
Database Acceptance
Fabricate Underlayer
Place and Route/ Clock Tree
Verification/ Resimulation
Final Design Review If Standard Cell If Embedded/Gate Array
Tape Out Full Mask Set
Tape Out Metal Masks
Fabricate
Fabricate Personality
Customer Atmel Joint
Proto Assembly and Test Rev. 2.2-03/02
Proto Shipment
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ATL25 Series ASIC
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ATL25 Series ASIC
Pin Definition Requirements
The corner pads are reserved for power and ground only. All other pads are fully programmable as input, output, bidirectional, power, or ground. When implementing a design with 3.3V compliant buffers, an appropriate number of pad sites must be reserved for the V DD 3 pins, which are used to distribute 3.3V power to the compliant buffers.
Design Options
Logic Synthesis
Atmel can accept RTL designs in Verilog or VHDL HDL formats. Atmel fully supports Synopsys for Verilog or VHDL simulation as well as synthesis. Of the two HDL formats, Verilog and VHDL, Atmel's preferred HDL format for ASIC design is Verilog. Atmel has successfully translated existing designs from most major ASIC vendors into Atmel ASICs. These designs have been optimized for speed and gate count and modified to add logic or memory, or replicated as a pin-for-pin compatible, drop-in replacement. Atmel has successfully translated existing FPGA/PLD designs from most major vendors into Atmel ASICs. There are four primary reasons to convert from an FPGA/PLD to an ASIC: * * * * Conversion of high-volume devices for a single or combined design is cost effective. Performance can often be optimized for speed or low power consumption. Several FPGA/PLDs can be combined onto a single chip to minimize cost while reducing on-board space requirements. In situations where an FPGA/PLD was used for fast cycle time prototyping, an ASIC may provide a lower cost answer for long-term volume production.
ASIC Design Translation FPGA and PLD Conversions
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Macro Cores
AVR 8-bit RISC Microcontroller Core
The AVR RISC microcontroller is a true 8-bit RISC architecture, ideally suited for embedded control applications. The AVR is offered as a gate level, synthesizable macro core in the ATL25 family. The AVR supports a powerful set of 120 instructions. The AVR prefetches an instruction during a prior instruction execution, enabling the execution of one instruction per clock cycle. The Fast Access RISC register file consists of 32 general purpose working registers. These 32 registers eliminate the data transfer delay in the traditional program code intensive accumulator architectures. The AVR can incorporate up to 64 x 16K program memory (ROM) and 64 x 8K data memory (SRAM). Among the peripheral options offered are: UART, 8-bit timer/counter, 16-bit timer/counter, programmable watchdog timer and SPI. Figure 3. AVR 8-bit RISC Microcontroller Core
16 bit
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8-bit Data Bus
ATL25 Series ASIC
ARM7TDMITM 32-bit RISC Microprocessor Core
The ARM7TDMI is a powerful 32-bit processor offered as a hard macro core in the ATL25 family. The ARM7TDMI is a member of the Advanced RISC Machines (ARM) family of general purpose 32-bit microprocessors, which offer high performance with very low power consumption. Additionally, the ARM7T offers users a "thumb" mode (for higher code density using 16-bit instructions The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers (CISC). This simplicity results in a high instruction throughput and an impressive real-time interrupt response from a small and costeffective chip. Pipelining is employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM memory interface has been designed to allow the performance potential to be realized without incurring high costs in the memory system. Speed-critical control signals are pipelined to allow system control functions to be implemented in standard low-power logic, and these control signals facilitate the exploitation of the fast local access modes offered by industry standard SRAMs. The ARM7TDMI core interfaces to several optional peripheral macros. Among the peripheral options offered are real-time clock, peripheral data controller, USART, external bus interface, interrupt controller, timer counter and watchdog timer. Figure 4. ARM7TDMI 32-bit RISC Microprocessor Core
Address Incrementor Register Bank (31 X 32-bit Registers) (6 Status Registers)
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ARM920TTM 32-bit RISC Microprocessor Core ARM946E-STM 32-bit RISC Microprocessor Core
The ARM920T extends the capabilities of the popular ARM7TDMI, while maintaining code compatibility and Thumb instruction compression. Enhancements include Harvard architecture and a memory management unit with virtual addressing support (allowing the use of advanced platform operating systems such as Windows CETM, Linux (R), Symbian OS TM and VxWorksTM). 16 Kbyte data and instruction caches are included. The ARM946E-S is a synthesizable version of the ARM9E-S core, with similar features to the ARM920T. The ARM9E-S instruction set adds saturation logic to enhance DSP implementation, as well as double-word data moves. Additional DSP features include a single cycle 16 x 32 Multiply Accumulate (MAC) Unit. A memory protection unit is provided, but without full virtual memory support. As a result, the ARM946E-S is more suited to deeply embedded tasks that do not require extended-platform OS support. Cache sizes can be tailored to the application, resulting in a (potentially) smaller die size compared to the ARM920T. Atmel's hard macro OakDSPCore is a 16-bit, general purpose, low-power, low-voltage and high-speed Digital Signal Processor (DSP). Oak is designed for mid-to-high-end telecommunications and consumer electronics applications, where low-power and portability are major requirements. Among the applications supported are digital cellular telephones, fast modems, advanced facsimile machines and hard disk drives. Oak is available as a DSP core in Atmel's ASIC cell library, to be utilized as an engine for a DSP-based ASIC. It is specified with several levels of modularity in SRAM, ROM and I/O blocks, allowing efficient DSP-based ASIC development. Oak is aimed at achieving the best cost-performance factor for a given (small) silicon area. As a key element of a system-on-chip, it takes into account such requirements as program size, data memory size, glue logic and power management. The Oak core consists of three main execution units operating in parallel: the Computation/BitManipulation Unit (CBU), the Data Addressing Arithmetic Unit (DAAU) and the Program Control Unit (PCU). The core also contains ROM and SRAM addressing units, and Program Control Logic (PCL). All other peripheral blocks that are application specific are defined as part of the user-specific logic and implemented around the DSP core on the same silicon die. Oak has an enhanced set of DSP and general microprocessor functions to meet most application requirements. The Oak programming model and instruction set are aimed at the straightforward generation of efficient and compact code.
OakDSPCore(R) Digital Signal Processing Core
MIPS64TM 5KfTM 64-bit RISC Microprocessor Core
The MIPS64 5Kf is a synthesizable MIPS64 5K family core that provides 64-bit address and data paths along with an onboard IEEE 754-compliant Floating Point Unit. A built-in memory management unit with virtual addressing support allows the use of platform operating systems such as Windows CE and others. Also provided are configurable instruction and data caches, as well as a multiply divide unit capable of single cycle 32 x 16 Multiply Accumulate (MAC) operations. The Teak and Palm are synthesizable dual-MAC DSP cores from DSP Group, Inc. The Teak is a fixed-point 16-bit DSP, whereas the Palm can be configured for 16-bit, 20-bit or 24-bit fixed-point math. Both cores are optimized for high MIPs per mW, with performance targeted to handling filtering, voice compression/decompression and modem functions for portable and wireless applications such as 3G digital cellular. Hardware support is also provided for implementing Viterbi forward error correction.
Teak and PalmDSPCore(R) Digital Signal Processing Cores
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ATL25 Series ASIC
The Teak and Palm cores both have a comprehensive suite of development tools that are easy to learn and are intended to support rapid code development. A C compiler that supports in-line assembly language and provides language extensions to enhance C code optimization is provided. An assembler and linker are also provided. Both emulation (using test silicon) and source-level simulation of C and assembly language enhance software verification.
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ATL25 Series Cell Library
Atmel's ATL25 Series ASICs make use of an extensive library of cell structures, including logic cells, buffers and inverters, multiplexers, decoders and I/O options. Soft macros are also available. These cells are characterized by use of SPICE modeling at the transistor level, with performance verified on manufactured test silicon. Characterization is performed over the rated temperature and voltage ranges to ensure that the simulation accurately predicts the performance of the finished product. Absolute Maximum Ratings*
Parameter Operating Ambient Temperature Storage Temperature Maximum Input Volutage: Inputs 3.3V Compliant 3.3V/5V Tolerant Maximum Operating Voltage (V DD) Maximum Operating Voltage (V DD3) Note: Rating -55C to +125C -65C to +150C VDD + 0.5V VDD3 + 0.5V 5.5V 2.7V 3.6V
* Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 4. 2.5-volt DC Characteristics Applicable over recommended operating temperature and voltage range unless otherwise noted.
Symbol TA VDD IIH IIL IOZ IOS VIH VIL VHYS VOH VOL Note: Parameter Operating Temperature Supply Voltage High-level Input Current Low-level Input Current High-impedance State Output Current Output Short-circuit Current High-level Input Voltage Low-level Input Voltage Hysteresis High-level Output Voltage (Standard and Tolerant Low-level Output Voltage (Standard and Tolerant) All I/Os 2.5V Compliant Buffer All All CMOS CMOS VIN = VDD, VDD = VDD (max) VIN = VSS, VDD = VDD (max) Pull-up = 620 K VIN = VDD or VSS, VDD = VDD (max), No pull-up or pull-down VOUT = VDD, VDD = VDD (max) VOUT = VSS, VDD = VDD (max) 0.7VDD 0.7VDD 1.3 0.3VDD 1.1 0.4 IOH = 2 mA, VDD = V DD (max) IOH = 2 mA IOL = 2 mA, VDD = VDD (max) 0.7VDD 0.7VDD 0.3VDD V 0.3VDD -10 -10 6 -4 10 Test Condition Min -55 2.3 2.5 Typ Max 125 2.7 10 Units C V A A
All PO11 PO11 CMOS CMOS Schmitt CMOS CMOS Schmitt CMOS Schmitt PO11 3.3V Tolerant PO11
A
mA V V V
V
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ATL25 Series ASIC
Table 5. 3.3-volt DC Characteristics Applicable over recommended operating temperature and voltage range unless otherwise noted.
Symbol TA VDD VDD3 IIH Parameter Operating Temperature Supply Voltage Supply Voltage High-level Input Current Low-level Input Current High-impedance State Output Current Buffer All All Except 3.3V Compliant I/O 3.3V Compliant I/O CMOS VIN = VDD, VDD = VDD (max) VIN = VSS, VDD = VDD (max) Pull-up = 620 K VIN = VDD or VSS VDD = VDD (max) No pull-up VOUT = V DD, VDD = VDD (max) VOUT = V SS, VDD = VDD (max) 2.0 0.475V DD3 2.0 1.7 0.8 0.325VDD3 1.1 0.6 IOH = 2 mA, VDD3 = VDD (min) IOH = 500 A IOL = 2 mA, VDD3 = VDD (min) IOL = 1.5 mA 0.8VDD3 0.9VDD3 0.2VDD 0.1VDD V 0.8 V V V -10 Test Condition Min -55 2.3 3.0 2.5 3.3 Typ Max 125 2.7 3.6 10 Units C V V A
IIL
CMOS
A
IOZ
All
-10
10
A
2 mA Buffer IOS Output Short-circuit Current 2 mA Buffer CMOS, LVTTL VIH High-level Input Voltage PCI CMOS/TTL-level Schmitt CMOS VIL Low-level Input Voltage PCI CMOS/TTL-level Schmitt TTL-level Schmitt PO11 PCI Low-level Output Voltage PO11 PCI Note: All I/Os 3.3V Tolerant/Compliant
10 mA -9
VHYS VOH
Hysteresis High-level Output Voltage
V
VOL
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Table 6. I/O Buffer DC Characteristics
Symbol CIN COUT CI/O Parameter Capacitance, Input Buffer (die) Capacitance, Output Buffer (die) Capacitance, Bidirectional Test Condition 3.3V 3.3V 3.3V Typical 2.4 5.6 6.6 Units pF pF pF
Testability Techniques
For complex designs involving blocks of memory and/or cores, careful attention must be given to design-for-test techniques. The sheer size of complex designs requires the use of more efficient testability techniques. Combinations of SCAN paths, multiplexed access to memory and/or core blocks, and built-in self-test logic (in addition to functional test patterns) must be employed to provide both the user and Atmel with the ability to test the finished product. An example of a highly complex design could include a PLL for clock management or synthesis, a microprocessor or DSP engine or both, SRAM to support the microprocessor or DSP engine, and glue logic to support the interconnectivity of each of these blocks. The design of each of these blocks must take into consideration the fact that the manufactured device will be tested on a high-performance digital tester. Combinations of parametric, functional and structural tests, defined for digital testers, should be employed to create a suite of manufacturing tests. The type of block dictates the type of testability technique to be employed. The PLL will, by construction, provide access to key nodes so that functional and/or parametric testing can be performed. Since a digital tester must control all the clocks during the testing of an ASIC, provisions must be made for the VCO to be bypassed. Atmel's PLLs include a multiplexing capability for just this purpose. The addition of a few pins will allow other portions of the PLL to be isolated for test without impinging upon the normal functionality. In a similar vein, access to microprocessor, DSP and SRAM blocks must be provided so that controllability and observability of the inputs and outputs to the blocks are achieved with the minimum amount of preconditioning. The ARM and MIPS microprocessors, AVR microcontroller and OakDSPCore/TeakDSPCore/PalmDSPCore digital signal processors all support SCAN testing. SRAM blocks need to provide access to both address and data ports so that comprehensive memory tests can be performed. Multiplexing I/O pins is a method for providing this accessibility. The glue logic can be designed using full SCAN techniques to enhance its testability. It should be noted that in almost all of these cases, the purpose of the testability technique is to assure all embedded circuit blocks are functional. All of the techniques described above should be considered supplemental to a set of patterns that exercise the functionality of the design in its anticipated operating modes.
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ATL25 Series ASIC
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ATL25 Series ASIC
Advanced Packaging
The ATL25 Series ASICs are offered in a wide variety of standard packages, including plastic and ceramic quad flatpacks, thin quad flatpacks, ceramic pin grid arrays and ball grid arrays. High-volume onshore and offshore contractors provide assembly and test for commercial product, with prototype capability in Colorado Springs. Custom package designs are also available as required to meet a customer's specific needs, and are supported through Atmel's package design center. If a standard package cannot meet a customer's needs, a package can be designed to precisely fit the customer-specific application and to maintain the performance obtained in silicon. Atmel has delivered custom-designed packages in a wide variety of configurations.
Table 7. Packaging Options-Partial List
Package Type PQFP Power Quad L/TQFP PLCC CPGA CQFP PBGA Super BGA Low-profile Mini BGA Chip-scale BGA Flex-tape BGA FCBGA(1) Note: Pin Count 44, 52, 64, 80, 100, 120, 128, 132, 144, 160, 184, 208, 240, 304 144, 160, 208, 240, 304 32, 44, 48, 64, 80, 100, 120, 128, 144, 160, 176, 216 20, 28, 32, 44, 52, 68, 84 64, 68, 84, 100, 124, 144, 155, 180, 223, 224, 299, 391 64, 68, 84, 100, 120, 132, 144, 160, 224, 340 121, 169, 208, 217, 225, 240, 256, 272, 300, 304, 313, 316, 329, 352, 388, 420, 456 168, 204, 240, 256, 304, 352, 432, 560, 600 40, 48, 49, 56, 60, 64, 80, 81, 84, 96, 100, 108, 128, 132, 144, 160, 176, 192, 208, 224, 228 32, 36, 40, 48, 49, 56, 64, 81, 84, 100, 108, 121, 128, 144, 160, 169, 176, 192, 208, 224, 256, 288, 324 48, 49, 64, 80, 81, 84, 96, 100, 112, 132, 144, 156, 160, 180, 192, 196, 204, 208, 220, 225, 228, 256, 280 416, 480, 564, 672, 788, 896, 960, 1032, 1152, 1157, 1292, 1357, 1413, 1500, 1517, 1557, 1677, 1728, 1932
1. Require customer design substrate.
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(c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. Atmel(R) and AVR (R) are registered trademarks of Atmel. ARM7TDMI TM, ARM920T TM and ARM946E-S TM are trademarks of ARM Limited; MIPS64 TM5KfTM are trademarks of MIPS Technologies, Inc.; Teak TM and PalmDSPCore TM are trademarks of DSP Group; Cadence (R) is a registered trademark and Opus TM, NC Verilog TM, Pearl TM, Verilog-XLTM and BuildGatesTM are trademarks of Cadence Design Systems, Inc.; Mentor Graphics (R) and ModelSim (R) are registered trademarks and Leonardo Spectrum TM is a trademark of Mentor Graphics; Design CompilerTM , PrimeTimeTM , VCSTM and Floorplan Manager TM are trademarks and Synopsys (R) and TetraMax (R) are registered trademarks of Synopsys; Novas Software (R) and Debussy (R) are registered trademarks of Novas Software, Inc.; Silicon PerspectiveTM is a trademark and First Encounter(R) is Printed on recycled paper. a registered trademark of Silicon Perspective; Windows CETM is a trademark of Microsoft Corp.; Linux TM is a trademark of Linus Torvalds; Symbian OS TM is a trademark of Symbian Limited; VxWorks TM is a trademark of 1414C-ASIC-ASIC-08/02 Wind River Systems, Inc. Other terms and product names may be the trademarks of others.

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