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SN54GTL16612, SN74GTL16612 18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
www.ti.com
SCBS480K - JUNE 1994 - REVISED JULY 2005
FEATURES
* * Members of Texas Instruments WidebusTM Family UBTTM Transceivers Combine D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Modes OECTM Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Translate Between GTL/GTL+ Signal Levels and LVTTL Logic Levels Support Mixed-Mode (3.3 V and 5 V) Signal Operation on A-Port and Control Inputs Identical to '16601 Function Ioff Supports Partial-Power-Down Mode Operation Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors on A Port Distributed VCC and GND Pins Minimize High-Speed Switching Noise Latch-Up Performance Exceeds 500 mA Per JESD 17
SN54GTL16612 . . . WD PACKAGE SN74GTL16612 . . . DGG OR DL PACKAGE (TOP VIEW)
* * * * * *
* *
OEAB LEAB A1 GND A2 A3 VCC (3.3 V) A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC (3.3 V) A16 A17 GND A18 OEBA LEBA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
CEAB CLKAB B1 GND B2 B3 VCC (5 V) B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VREF B16 B17 GND B18 CLKBA CEBA
DESCRIPTION/ORDERING INFORMATION
The 'GTL16612 devices are 18-bit UBTTM transceivers that provide LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL signal-level translation. They combine D-type flip-flops and D-type latches to allow for transparent, latched, clocked, and clock-enabled modes of data transfer identical to the '16601 function. The devices provide an interface between cards operating at LVTTL logic levels and a backplane operating at GTL/GTL+ signal levels. Higher-speed operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and OECTM circuitry. The user has the flexibility of using these devices at either GTL (VTT = 1.2 V and VREF = 0.8 V) or the preferred higher noise margin GTL+ (VTT = 1.5 V and VREF = 1 V) signal levels. GTL+ is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V tolerant. VREF is the reference input voltage for the B port. VCC (5 V) supplies the internal and GTL circuitry while VCC (3.3 V) supplies the LVTTL output buffers.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus, UBT, OEC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1994-2005, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
SN54GTL16612, SN74GTL16612 18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
SCBS480K - JUNE 1994 - REVISED JULY 2005
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable(LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CEAB and CEBA) inputs. For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CEAB is low and CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB if CEAB also is low. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that for A to B, but uses OEBA, LEBA, CLKBA, and CEBA. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. ORDERING INFORMATION
TA -40C to 85C -55C to 125C (1) SSOP - DL TSSOP - DGG CFP - WD PACKAGE (1) Tube Tape and reel Tape and reel Tube ORDERABLE PART NUMBER SN74GTL16612DL SN74GTL16612DLR SN74GTL16612DGGR SNJ54GTL16612WD TOP-SIDE MARKING GTL16612 GTL16612 SNJ54GTL16612WD
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE (1)
A X X X L H L H X
INPUTS CEAB X L L X X L L H (1) (2) (3) OEAB H L L L L L L L LEAB X L L H H L L L CLKAB X H L X X X
OUTPUT B Z B0 (2) B0 (3) L H L H B0 (3)
MODE Isolation Latched storage of A data Transparent Clocked storage of A data Clock inhibit
A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA, LEBA, CLKBA, and CEBA. Output level before the indicated steady-state input conditions were established, provided that CLKAB was high before LEAB went low Output level before the indicated steady-state input conditions were established
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SN54GTL16612, SN74GTL16612 18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
SCBS480K - JUNE 1994 - REVISED JULY 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
35 VREF 1 OEAB CEAB 56
55 CLKAB 2 LEAB 28 LEBA 30 CLKBA CEBA 29
27 OEBA 3 A1 CE 1D C1 CLK CE 1D C1 CLK 54
B1
To 17 Other Channels
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SN54GTL16612, SN74GTL16612 18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
SCBS480K - JUNE 1994 - REVISED JULY 2005
www.ti.com
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN VCC VI VO IO IO IIK IOK JA Tstg (1) (2) (3) (4) Supply voltage range Input voltage range (2) Voltage range applied to any output in the high or power-off state (2) Current into any output in the low state Current into any A-port output in the high state (3) Continuous current through each VCC or GND Input clamp current Output clamp current Package thermal impedance (4) Storage temperature range VI < 0 VO < 0 DGG package DL package -65 3.3 V 5V A-port and control inputs B port and VREF A port B port A port B port -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 MAX 4.6 7 7 4.6 7 4.6 128 80 64 100 -50 -50 64 56 150 UNIT V V V mA mA mA mA mA C/W C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This current flows only when the output is in the high state and VO > VCC. The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions (1) (2) (3) (4)
SN54GTL16612 MIN VCC VTT VREF VI VIH VIL IIK IOH IOL TA (1) (2) (3) (4) Supply voltage Termination voltage Reference voltage Input voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current A port A port B port -55 3.3 V 5V GTL GTL+ GTL GTL+ B port Except B port B port Except B port B port Except B port VREF + 50 mV 2 VREF - 50 mV 0.8 -18 -32 64 40 125 -40 3.15 4.75 1.14 1.35 0.74 0.87 NOM 3.3 5 1.2 1.5 0.8 1 MAX 3.45 5.25 1.26 1.65 0.87 1.1 VTT 5.5 VREF + 50 mV 2 VREF - 50 mV 0.8 -18 -32 64 40 85 SN74GTL16612 MIN 3.15 4.75 1.14 1.35 0.74 0.87 NOM 3.3 5 1.2 1.5 0.8 1 MAX 3.45 5.25 1.26 1.65 0.87 1.1 VTT 5.5 UNIT V V V V V V mA mA mA C
Operating free-air temperature
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Normal connection sequence is GND first, VCC = 5 V second, and VCC = 3.3 V, I/O, control inputs, VTT and VREF (any order) last. VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded. VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT.
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SN54GTL16612, SN74GTL16612 18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
SCBS480K - JUNE 1994 - REVISED JULY 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK TEST CONDITIONS VCC (3.3 V) = 3.15 V, VCC (5 V) = 4.75 V VCC (3.3 V) = 3.15 V to 3.45 V, VCC (5 V) = 4.75 V to 5.25 V VCC (3.3 V) = 3.15 V, VCC (5 V) = 4.75 V II = -18 mA IOH = -100 A IOH = -8 mA IOH = -32 mA IOL = 100 A A port VOL B port Control inputs A port VCC (3.3 V) = 3.15 V, VCC (5 V) = 4.75 V IOL = 16 mA IOL = 32 mA IOL = 64 mA VCC (3.3 V) = 3.15 V, VCC (5 V) = 4.75 V, IOL = 40 mA VCC (3.3 V) = 0 or 3.45 V, VCC (5 V) = 0 or 5.25 V VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V VCC = 0, VCC (3.3 V) = 3.15 V, VCC (5 V) = 4.75 V VI = 5.5 V VI = 5.5 V VI = VCC (3.3 V) VI = 0 VI = VCC (3.3 V) VI = 0 VI or VO = 0 to 4.5 V VI = 0.8 V II(hold) A port VI = 2 V VI = 0 to VCC (3.3 V) (2) 75 -75 500 1 10 -1 -10 1 5 1 120 120 120 1 3.5 12 12 18 10 3.5 12 5 VCC (3.3 V) - 0.2 2.4 2 0.2 0.4 0.5 0.6 0.5 10 1000 1 -30 5 -5 1000 75 -75 500 1 10 -1 -10 1 5 1 120 120 120 1 mA pF pF mA mA A A A SN54GTL16612 MIN TYP (1) MAX -1.2 VCC (3.3 V) - 0.2 V 2.4 2 0.2 0.4 0.5 0.55 0.4 10 20 1 -30 5 -5 100 A A V SN74GTL16612 MIN TYP (1) MAX -1.2 UNIT V
VOH
A port
II
B port Ioff
IOZH IOZL
A port B port A port B port
VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, VO = 3 V VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, VO = 1.2 V VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, VO = 0.5 V VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, VO = 0.4 V VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, IO = 0, VI = VCC (3.3 V) or GND VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, IO = 0, VI = VCC (3.3 V) or GND Outputs high Outputs low Outputs disabled Outputs high Outputs low Outputs disabled
ICC A or B (3.3 V) port
ICC (5 V)
A or B port
ICC (3) Ci Cio (1) (2) (3) Control inputs A port B port
VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V, A-port or control inputs at VCC (3.3 V) or GND, One input at 2.7 V VI = 3.15 V or 0 VO = 3.15 V or 0
All typical values are at VCC (3.3 V) = 3.3 V, VCC (5 V) = 5 V, TA = 25C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
5
SN54GTL16612, SN74GTL16612 18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
SCBS480K - JUNE 1994 - REVISED JULY 2005
www.ti.com
Timing Requirements
over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.2 V and VREF = 0.8 V for GTL (unless otherwise noted) (see Figure 1)
SN54GTL16612 MIN fclock tw Clock frequency Pulse duration LEAB or LEBA high CLKAB or CLKBA high or low A before CLKAB B before CLKBA tsu Setup time A before LEAB B before LEBA CEAB before CLKAB CEBA before CLKBA A after CLKAB B after CLKBA th Hold time A after LEAB B after LEBA CEAB after CLKAB CEBA after CLKBA 3.3 5.6 1.3 3.4 1.2 1 2.1 2.6 2.9 4.1 4.5 4.3 2 1.1 MAX 95 3.3 5.6 1.3 2.5 0 1 2 2.2 1.6 0.3 4 3.6 0.8 1.1 ns ns SN74GTL16612 MIN MAX 95 UNIT MHz ns
Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.2 V and VREF = 0.8 V for GTL (see Figure 1)
PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL ten tdis tr tf tPLH tPHL tPLH tPHL tPLH tPHL ten tdis (1) A LEAB CLKAB OEAB B B B B FROM (INPUT) TO (OUTPUT) SN54GTL16612 MIN TYP (1) 95 1 1 1 1 1 1 1 1 2.8 2.5 3.6 3.5 3.7 3.4 3.3 3.4 1.3 0.5 2 1 2 1 2 2 1 2 4.1 2.9 3.7 3 3.8 3.3 5 4.3 6.9 5.1 6.1 5.1 6.4 5.6 7.5 6.9 2.1 1.2 2.3 1.8 2.5 2.3 2.3 2.5 4.5 4.5 5.5 6 5.5 5.5 5.5 5.5 MAX SN74GTL16612 MIN TYP (1) 95 1.5 1.3 2 1.9 2.3 1.9 2 2 2.8 2.5 3.6 3.5 3.7 3.4 3.3 3.4 1.3 0.5 4.1 2.9 3.7 3 3.8 3.3 5 4.3 6.3 4.6 5.7 4.8 6.1 5.2 7.4 6.4 4.1 4 5.3 5.4 5.3 5.4 5.5 5.1 MAX UNIT MHz ns ns ns ns ns ns ns ns ns ns
Transition time, B outputs (0.5 V to 1 V) Transition time, B outputs (1 V to 0.5 V) B LEBA CLKBA OEBA A A A A
All typical values are at VCC (3.3 V) = 3.3 V, VCC (5 V) = 5 V, TA = 25C.
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SN54GTL16612, SN74GTL16612 18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
SCBS480K - JUNE 1994 - REVISED JULY 2005
Timing Requirements
over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTL+ (unless otherwise noted) (see Figure 1)
SN54GTL16612 MIN fclock tw Clock frequency Pulse duration LEAB or LEBA high CLKAB or CLKBA high or low A before CLKAB B before CLKBA tsu Setup time A before LEAB B before LEBA CEAB before CLKAB CEBA before CLKBA A after CLKAB B after CLKBA th Hold time A after LEAB B after LEBA CEAB after CLKAB CEBA after CLKBA 3.3 5.6 1.3 3.2 1.2 1.3 2.1 2.6 2.9 4.4 4.5 4.3 2 1.1 MAX 95 3.3 5.6 1.3 2.3 0 1.3 2 2.2 1.6 0.3 4 3.6 0.8 1.1 ns ns SN74GTL16612 MIN MAX 95 UNIT MHz ns
Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTL+ (see Figure 1)
PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tr tf tPLH tPHL tPLH tPHL tPLH tPHL ten tdis (1) A LEAB CLKAB OEAB B B B B FROM (INPUT) TO (OUTPUT) SN54GTL16612 MIN TYP (1) 95 1 1 1 1 1 1 1 1 2.8 2.5 3.6 3.5 3.7 3.4 3.4 3.3 1.5 0.8 1.9 0.9 2 1 2 2 1 2 4 2.8 3.7 3 3.8 3.3 5 4.3 6.9 4.9 6.1 5.1 6.4 5.6 7.5 6.9 2 1.1 2.3 1.8 2.5 2.3 2.3 2.5 4.5 4.6 5.5 6.1 5.5 5.6 5.5 5.6 MAX SN74GTL16612 MIN TYP (1) 95 1.5 1.3 2 1.9 2.3 1.9 2 2 2.8 2.5 3.6 3.5 3.7 3.4 3.4 3.3 1.5 0.8 4 2.8 3.7 3 3.8 3.3 5 4.3 6.3 4.4 5.7 4.8 6.1 5.2 7.4 6.4 4.1 4.1 5.3 5.5 5.3 5.5 5.1 5.6 MAX UNIT MHz ns ns ns ns ns ns ns ns ns ns
Transition time, B outputs (0.5 V to 1 V) Transition time, B outputs (1 V to 0.5 V) B LEBA CLKBA OEBA A A A A
All typical values are at VCC (3.3 V) = 3.3 V, VCC (5 V) = 5 V, TA = 25C.
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SN54GTL16612, SN74GTL16612 18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
SCBS480K - JUNE 1994 - REVISED JULY 2005
www.ti.com
PARAMETER MEASUREMENT INFORMATION VTT = 1.2 V, VREF = 0.8 V for GTL and VTT = 1.5 V, VREF = 1 V for GTL+
6V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND VTT 25 From Output Under Test CL = 30 pF (see Note A) Test Point
LOAD CIRCUIT FOR A OUTPUTS tw 3V Input VM V VM V 0V VOLTAGE WAVEFORMS PULSE DURATION (VM = 1.5 V for A port and VREF for B port)(1) Input (see Note B) 3V 1.5 V 1.5 V 0V tPLH Output tPHL VTT VREF VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (A port to B port)(1) Input (see Note B) VTT VREF VREF 0V tPLH Output 1.5 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (B port to A port)(1)
(1)
LOAD CIRCUIT FOR B OUTPUTS 3V 1.5 V 0V tsu Data Input A Port 1.5 V 0V VTT VREF VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VREF 0V th 3V
Timing Input
Data Input B Port
VREF VOL
Output Control (see Note B) tPZL Output Waveform 1 S1 at 6 V (see Note C) tPZH
3V 1.5 V 1.5 V 0V tPLZ 3V 1.5 V VOL + 0.3 V VOL tPHZ VOH 1.5 V VOH - 0.3 V 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES (A port)
tPHL VOH 1.5 V VOL Output Waveform 2 S1 at GND (see Note C)
All control inputs are TTL levels. NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. D. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
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PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device 5962-9689001QXA 74GTL16612DGGRE4 SN74GTL16612DGGR SN74GTL16612DL SN74GTL16612DLR SNJ54GTL16612WD
(1)
Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type CFP TSSOP TSSOP SSOP SSOP CFP
Package Drawing WD DGG DGG DL DL WD
Pins Package Eco Plan (2) Qty 56 56 56 56 56 56 1 TBD 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 20 Green (RoHS & no Sb/Br)
Lead/Ball Finish Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI
MSL Peak Temp (3) Level-NC-NC-NC Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-NC-NC-NC
1000 Green (RoHS & no Sb/Br) 1 TBD
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MCFP010B - JANUARY 1995 - REVISED NOVEMBER 1997
WD (R-GDFP-F**)
48 LEADS SHOWN 0.120 (3,05) 0.075 (1,91)
CERAMIC DUAL FLATPACK
0.009 (0,23) 0.004 (0,10)
1.130 (28,70) 0.870 (22,10) 0.370 (9,40) 0.250 (6,35) 1 0.390 (9,91) 0.370 (9,40) 48 0.025 (0,635) 0.370 (9,40) 0.250 (6,35)
A 0.014 (0,36) 0.008 (0,20)
24
25
NO. OF LEADS** A MAX A MIN
48 0.640 (16,26) 0.610 (15,49)
56 0.740 (18,80) 0.710 (18,03) 4040176 / D 10/97
NOTES: A. B. C. D. E.
All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only Falls within MIL STD 1835: GDFP1-F48 and JEDEC MO -146AA GDFP1-F56 and JEDEC MO -146AB
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C - JANUARY 1995 - REVISED DECEMBER 2001
DL (R-PDSO-G**)
48 PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0.025 (0,635)
0.0135 (0,343) 0.008 (0,203) 25
0.005 (0,13) M
48
0.010 (0,25) 0.005 (0,13)
0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03)
Gage Plane 0.010 (0,25)
1 A
24
0- 8 0.040 (1,02) 0.020 (0,51)
Seating Plane 0.110 (2,79) MAX 0.008 (0,20) MIN 0.004 (0,10)
PINS ** DIM A MAX
28 0.380 (9,65) 0.370 (9,40)
48 0.630 (16,00) 0.620 (15,75)
56 0.730 (18,54) 0.720 (18,29) 4040048 / E 12/01
A MIN
NOTES: A. B. C. D.
All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO-118
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D - JANUARY 1995 - REVISED JANUARY 1998
DGG (R-PDSO-G**)
48 PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,50 48
0,27 0,17 25
0,08 M
6,20 6,00
8,30 7,90
0,15 NOM
Gage Plane 0,25 0- 8 A 0,75 0,50
1
24
Seating Plane 1,20 MAX 0,15 0,05 0,10
PINS ** DIM A MAX
48
56
64
12,60
14,10
17,10
A MIN
12,40
13,90
16,90 4040078 / F 12/97
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153
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