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| PSN1000A 9939 Via Pasar * San Diego, CA 92126 TEL (858) 621-2700 FAX (858) 621-2722 PHASE LOCKED LOOP Rev A PHASE NOISE (1 Hz BW, typical) Unknown container object FEATURES * Frequency Range: 988 - 1028 MHz * Step Size: 1000 KHz * PLL - Style Package APPLICATIONS * Basestations * Mobile Radios * Satellite Communications PERFORMANCE SPECIFICATIONS Frequency Range VALUE 988 - 1028 -101 -20 -70 0.52.5 50 1000 250 2 5 -40 to +85 PLL 5 32 APPLICATION NOTES Phase Noise @ 10 kHz offset (1 Hz BW, typ.) Harmonic Suppression (2nd, typ.) Sideband Spurs (typ.) Power Output Load Impedance Step Size Charge Pump Output Current Switching Speed (typ., adjacent channel) Startup Lock Time (typ.) Operating Temperature Range Package Style UNITS MHz dBc/Hz dBc dBc dBm KHz mSec mSec C POWER SUPPLY REQUIREMENTS Supply Voltage (Vcc, nom.) Supply Current (Icc, typ.) Vdc mA All specifications are typical unless otherwise noted and subject to change without notice. * AN-107 : How to Solder Z-COMM VCOs / PLLs * AN-200 : Mounting and Grounding of Z-COMM PLLs * AN-201 : PLL Fundamentals AN-202 : PLL Functional Description NOTES: Reference Oscillator Signal: 5 MHz< <40 MHz Frequency Synthesizer: National Semiconductor - LMX2316 (c) Z-Communications, Inc. Page 1 All rights reserved LOW COST - HIGH PERFORMANCE PHASE LOCKED LOOP VCO TUNING CURVE, typ. 1110 1060 PSN1000A PAGE 2 FREQUENCY (MHz) 1010 85 960 910 860 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 25 -40 c c c TUNING VOLTAGE (Vdc) VCO POWER CURVE, typ. 8 OUTPUT POWER (dBm) 6 4 2 25 0 -2 -4 887 c 914 937 957 976 995 1013 1032 1051 1070 1090 FREQUENCY (MHz) PHYSICAL DIMENSIONS PLL 415-0078 REV. F (DRAWING NOT TO SCALE) 14 0.000 0.605 13 12 0.140 1 -0.025 2 3 11 0.000 10 TABS RANGE: SEE NOTE 5. (4 PLACES) DETAIL A 0.148 9 0.321 BOTTOM SEE DETAIL A 0.495 4 8 5 0.668 0.816 6 7 .070 .015 .030 DETAIL B (TYP) 0.841 SEE DETAIL B P1 RF OUTPUT .032 P2 GROUND P3 REFERENCE OSCILLATOR INPUT P4 CLOCK P5 DATA P6 LOAD ENABLE P7 LOCK DETECT P8 VCC P9 OPTIONAL P10 NO CONNECTION P11-14 GROUND NOTES: 1. THE INSIDE RADIUS OF ALL 14 HALF HOLES AT THE PERIMETER OF THE BOARD ARE PLATED TO PROVIDE A SURFACE FOR THE ATTACHMENT OF THE PLL MODULE TO A PCB, IN 11 LOCATIONS, WITH 3 PADS BEING USED FOR ELECTROMECHANICAL INTERFACE. 14 SOLDER LOCATIONS REQUIRED. 2. THE SURFACE OF THE SHIELD IS TIN PLATED AND MAY BE SOLDERED TO. THE SHIELD'S BASE METAL IS COLD ROLLED STEEL. 3. THE GROUND PLANE IS GROUND AND ATTACHES TO A GROUND TRACK ON THE UPPER SIDE OF THE BOARD AS WELL AS THE SHIELD BY PTH. 4. UNLESS OTHERWISE NOTED ALL DIMENSIONS ARE IN INCHES. 5. UNLESS OTHERWISE NOTED ALL TOLERANCES ARE AS FOLLOWS: TOLERANCES .XXX= .010 -0.025 0.130 0.290 0.450 0.580 (c) Z-Communications, Inc. Page 2 Printed in the U.S.A. |
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