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FEDL6650-03
Semiconductor
This version: Jul. 2000 Previous version: Sep. 1999
MSM6652/53/54/55/56-xxx, MSM6652A/53A/ 54A/55A/56A/58A-xxx, MSM66P54-XX, MSM66P56-xx, MSM6650
Internal Mask ROM Voice Synthesis IC, Internal One-Time-Programmable (OTP) ROM Voice Synthesis IC, External ROM Drive Voice Synthesis IC This document contains minimum specifications. For full specifications, please contact your nearest Oki office or representative.
GENERAL DESCRIPTION
The MSM6650 family is the successor to OKI's MSM6375 family. To ensure high-quality voice synthesis, the MSM6650 family members offer adaptive differential pulse-code modulation (ADPCM) playback, pulse-code modulation (PCM) playback, 12-bit D/A conversion, and on-chip -40 dB/ octave low-pass filter (LPF). The conventional "beep" tones and 2-channel playback are now easier to use. OKI has added additional functions such as melody play, fade-out, and random playback. OKI has improved external control by adding an Edit ROM. The Edit ROM can be used to form sentences by linking phrases. The MSM6650 family members can support a variety of applications as it can function in either Standalone Mode or Microcontroller Interface Mode. In Microcontroller Interface Mode, serial input control is available. Serial input control minimizes the number of microcontroller port pins required for voice synthesis control. The MSM6650 family includes an internal mask ROM version, internal one-time-programmable (OTP) ROM version, and external ROM version. The features of the MSM6650 family devices are as follows. * MSM6652/53/54/55/56-xxx These devices are single-chip voice synthesizers with an on-chip mask ROM using the CMOS technology. Standalone Mode or Microcontroller Interface Mode can be selected by mask option. * MSM6652A/53A/54A/55A/56A/58A-xxx The trial production period for these devices is shorter than those described above. These devices are suitable for developing prototype models and concept demonstration of new products. * MSM66P54-XX, MSM66P56-xx The device is a single-chip CMOS voice synthesizer with one-time-programmable (OTP) ROM. Standalone and Microcontroller Interface Modes are selected by using a code (01-04). The user can easily write voice data using the development tool AR761 or AR762, or P54 adapter. Unlike the mask ROM version, the OTP version is suited to applications which requires a small lot production of different type devices or short delivery time. * MSM6650 The MSM6650 device can directly connect external ROM or EPROM of up to 64 Mbits, which stores voice data. This device is ideally suited to an evaluation IC for the MSM6650 family because its circuit configuration is identical to those of the mask ROM-based and OTP version devices.
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FEDL6650-03 Semiconductor MSM6650 Family
* Option Table
Pin Name
MSM6652/53/54/55/56 MSM6652A/53A/54A/55A/56A/58A
Microcontroller Interface Mode Serial Input
Standalone Mode No Standby
*1
Parallel Input With Standby Mask Option
-- -- CPU SERIAL STBY -01 "H" "H" -- -02 "H" "L" --
MSM66P54/P56 MSM6650
-03 "L" "L" "L"
-04 "L" "L" "H"
*2
*1. The options for the mask ROM-based devices are mask options. The user should send OKI an option list before starting development. A sample of option list is shown below. *2. A code of OTP version device corresponds to one of the options. The user should specify either MSM66P54-03 or MSM66P54-04 or MSM66P56-03 or MSM66P56-04. (In this case, no option list is required.)
Oki Electric Industry Co., Ltd. Date:
Option List
You are requested to develop MSM665X-XXX on the following conditions. 1. Options There are four options for the MSM6650 family. Choose and circle the desired option. Option Option A Option B Option C Option D Interface mode Microcontroller Microcontroller Standalone Standalone Input Serial Parallel -- -- Standby conversion -- -- Yes No
2. Package and quantity Package (circle the desired one) 18-pin DIP (ceramic) 18-pin DIP (plastic) 18-pin DIP (plastic) 24-pin SOP (ceramic) 24-pin SOP (plastic) 24-pin SOP (plastic)
Item
Quantity
Note Up to 10 samples. Operating temp. : 10 to 30C Up to 50 samples
Ceramic sample Mold sample
chip
pcs
chip
pcs
Mass production
chip
pcs per lot monthly Signed by Title : Company name :
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FEDL6650-03 Semiconductor MSM6650 Family
STANDALONE MODE
FEATURES
Device name MSM6652, 6652A MSM6653, 6653A MSM6654, 6654A MSM6655, 6655A MSM6656, 6656A MSM6658A MSM66P54 MSM66P56 MSM6650 ROM size 288 Kbits 544 Kbits 1 Mbit 1.5 Mbits 2 Mbits 4 Mbits 1 Mbit 2 Mbit 64 Mbits (Max) Maximum playback time (sec) fSAM=4.0 kHz fSAM=6.4 kHz 16.9 31.2 63.8 96.5 129.1 259.7 63.8 129.1 4194.3 10.5 19.5 39.9 60.3 80.7 162.9 39.9 80.7 2620.5 fSAM=8.0 kHz 8.4 15.6 31.9 48.2 64.5 129.8 31.9 64.5 2096.4 fSAM=16 kHz 4.2 7.8 15.9 24.1 32.2 64.9 15.9 32.2 1048.2
Note: Actual voice ROM area is smaller by 22 Kbits. * 4-bit ADPCM or 8-bit PCM sound generation * Melody function * Edit ROM function * Two-channel mixing function * Built-in random playback function * Fade-out function via four-step sound volume attenuation * Built-in beep tone of 0.5 kHz, 1.0 kHz, 1.3 kHz, or 2.0 kHz selectable with a specific code * Sampling frequency of 4.0 kHz, 5.3 kHz, 6.4 kHz, 8.0 kHz, 10.6 kHz, 12.8 kHz, 16.0 kHz, or 32.0 kHz (32 kHz sampling is not possible when using RC oscillation) * Up to 120 phrases * Built-in 12-bit D/A converter * Built-in -40 dB/octave low-pass filter * Standby function * Selectable RC or ceramic oscillation * Package options: 18-pin plastic DIP (DIP18-P-300-2.54) (Product name: MSM6652-xxxRS/MSM6653-xxxRS/ MSM6654-xxxRS/MSM6655-xxxRS/ MSM6656-xxxRS/MSM6652A-xxxRS/ MSM6653A-xxxRS/MSM6654A-xxxRS/ MSM6655A-xxxRS/MSM6656A-xxxRS/ MSM6658A-xxxRS) 24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name: MSM6652-xxxGS-K/MSM6653-xxxGS-K/ MSM6654-xxxGS-K/MSM6655-xxxGS-K/ MSM6656-xxxGS-K/MSM6652A-xxxGS-K/ MSM6653A-xxxGS-K/MSM6654A-xxxGS-K/ MSM6655A-xxxGS-K/MSM6656A-xxxGS-K/ MSM6658A-xxxGS-K/MSM66P54-03GS-K/ MSM66P54-04GS-K/MSM66P56-03GS-K/ MSM66P56-04GS-K) 20-pin plastic DIP (DIP20-P-300-2.54-W1) (Product name: MSM66P54-03RS/MSM66P54-04RS/ MSM66P56-03RS/MSM66P56-04RS) 64-pin plastic QFP (QFP64-P-1420-1.00-BK) (Product name: MSM6650GS-BK) 64-pin plastic SDIP (SDIP64-P-750-1.778) (Product name: MSM6650SS) 3/45
Semiconductor
MSM6652/53/54/55/56-xxx MSM6652A/53A/54A/55A/56A/58A-xxx
BLOCK DIAGRAMS
A2 A1 A0 SW3 SW2 SW1 SW0 TEST
Address & Switching Controller
7
16-Bit (MSM6652/52A) 17-Bit (MSM6653/53A) 17-Bit (MSM6654/54A) 18-Bit (MSM6655/55A) 18-Bit (MSM6656/56A) 19-Bit (MSM6658A) Multiplexer
(MSM6652/52A) (MSM6653/53A) (MSM6654/54A) (MSM6655/55A) (MSM6656/56A) (MSM6658A) ROM (Containing 22-Kbit Phrase Control Table & Phrase Address Table)
288-Kbit 544-Kbit 1-Mbit 1.5-Mbit 2-Mbit 4-Mbit
8
RND
Random Circuit
BUSY
I/O Interface
16-Bit (MSM6652/52A) 17-Bit (MSM6653/53A) 17-Bit (MSM6654/54A) 18-Bit (MSM6655/55A) 18-Bit (MSM6656/56A) 19-Bit (MSM6658A) Address Counter
DATA Controller
ADPCM Synthesizer
PCM Synthesizer 12 Melody Generator 12-Bit DAC
OSC1 OSC2 OSC3
OSC Ceramic/ Crystal/RC
Timing Controller
BEEP Tone Generator
LPF
MSM6650 Family
FEDL6650-03
4/45
XT/CR
RESET
VDD
GND
AOUT
Semiconductor
MSM66P54/P56-xx
VPP
PGM
Program Circuit A2 A1 A0 SW3 SW2 SW1 SW0
Address & Switching Controller
7
17-Bit (MSM66P54-XX) 18-Bit (MSM66P56-xx) Multiplexer
1-Mbit OTP ROM (MSM66P54-XX) 2-Mbit OTP ROM (MSM66P56-xx)
(Containing 22-Kbit Phrase Control Table & Phrase Address Table)
8
TEST ADPCM Synthesizer RND Random Circuit
17-Bit (MSM66P54-XX) 18-Bit (MSM66P56-xx) Address Counter
DATA Controller PCM Synthesizer 12 12-Bit DAC
BUSY
I/O Interface
Melody Generator OSC1 OSC2 OSC3 OSC (Ceramic/ Crystal/RC) Timing Controller BEEP Tone Generator
MSM6650 Family
LPF
FEDL6650-03
5/45
XT/CR
RESET
VDD
GND
AOUT
RA22
RA0
D7
D0
Semiconductor
MSM6650
A2 A1 A0 SW3 SW2 SW1 SW0 TEST1, 3
8-Bit LATCH Address & Switching Controller 7 23-Bit Multiplexer 8
RND
Random Circuit 23-Bit Address Counter
DATA Controller
ADPCM Synthesizer
CE RCS BUSY NAR IBUSY STANDBY
PCM Synthesizer 12 Melody Generator 12-Bit DAC
I/O Interface
XT/OSC1 XT/OSC2 OSC3
OSC (Ceramic/ Crystal/RC)
Timing Controller
BEEP Tone Generator
LPF
MSM6650 Family
FEDL6650-03
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XT/CR
RESET CPU STBY TEST2 DVDD DGND
AGND AVDD AOUT
FEDL6650-03 Semiconductor MSM6650 Family
PIN CONFIGURATION (TOP VIEW)
The MSM66P54-XX and MSM66P56-xx has two more pins than the MSM6652-6658A while their pin configurations are identical. The additional two pins (VPP, PGM) of the MSM66P54-XX/P56-xx may be open at playback after completion of writing.
MSM6652-6658A (Mask ROM)
A0 A1 A2 TEST RESET 1 2 3 4 5 6 7 8 9 18 SW3 17 SW2 16 SW1 15 SW0 14 RND
MSM66P54/P56 (OTP)
VPP A0 A1 A2 TEST 1 2 3 4 5 6 7 8 9 20 PGM 19 SW3 18 SW2 17 SW1 16 SW0 15 RND 14 OSC3 13 OSC2 12 OSC1 11 VDD

BUSY 13 OSC3 12 OSC2 11 OSC1 10 VDD RESET XT/CR AOUT BUSY XT/CR AOUT GND
18-Pin Plastic DIP
GND 10
20-Pin Plastic DIP
MSM6652-xxxRS, MSM6653-xxxRS, MSM6654-xxxRS, MSM66P54-03/-04RS MSM6655-xxxRS, MSM6656-xxxRS, MSM6652A-xxxRS, MSM66P56-03/-04RS MSM6653A-xxxRS, MSM6654A-xxxRS, MSM6655A-xxxRS, MSM6656A-xxxRS, MSM6658A-xxxRS
MSM6652-6658A (Mask ROM) MSM66P54/P56 (OTP)
24 23 22 21 20 19 18 17 16 15 14 13 GND AOUT XT/CR NC BUSY NC VPP RESET TEST A2 A1 A0
VDD
1 2 3 4 5 6 7 8 9
24 23 22 21 20 19 18 17 16 15 14 13
GND
VDD
1 2 3 4 5 6 7 8 9
OSC1 OSC2 NC
AOUT
OSC1 OSC2 NC
XT/CR NC
OSC3 NC NC
BUSY NC NC
OSC3 NC
PGM RND SW0 SW1 SW2 SW3
RND SW0 SW1 SW2 SW3
RESET TEST A2 A1 A0
10 11 12
10 11 12
24-Pin Plastic SOP
24-Pin Plastic SOP
MSM6652-xxxGS-K, MSM6653-xxxGS-K, MSM6654-xxxGS-K, MSM6655-xxxGS-K, MSM6656-xxxGS-K, MSM6652A-xxxGS-K, MSM6653A-xxxGS-K, MSM6654A-xxxGS-K, MSM6655A-xxxGS-K, MSM6656A-xxxGS-K, MSM6658A-xxxGS-K
MSM66P54-03/-04GS-K MSM66P56-03/-04GS-K
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Semiconductor MSM6650
Product name: MSM6650GS-BK
NC NC BUSY NAR AOUT AGND DGND AVDD DVDD XT/OSC1 XT/OSC2 OSC3 TEST1 RND XT/CR CPU TEST2 IBUSY NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
STANDBY SW0 SW1 SW2 SW3 A0 A1 A2 TEST3 RESET CE RCS D0
,
64 63 62 61 60 59 58 57 20 21 22 23 24 25 26 27
FEDL6650-03 MSM6650 Family
56
55
54
53
52
STBY RA22 RA21 RA20 RA19 RA18 RA17 RA16 RA15 RA14 RA13 RA12 RA11
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
RA10 RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 D7 D6 D5 D4 D3 D2 D1 NC
28
29
30
31
NC : No connection 64-Pin Plastic QFP
32
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FEDL6650-03 Semiconductor Product name: MSM6650SS MSM6650 Family
XT/OSC2 OSC3 TEST1 RND XT/CR CPU TEST2 IBUSY NC STANDBY SW0 SW1 SW2 SW3 A0 A1 A2 TEST3 RESET CE RCS D0 NC D1 D2 D3 D4 D5 D6 D7 RA0 RA1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
XT/OSC1 DVDD AVDD DGND AGND AOUT NAR BUSY NC STBY RA22 RA21 RA20 RA19 RA18 RA17 RA16 RA15 RA14 RA13 RA12 RA11 RA10 NC RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2
NC : No connection 64-Pin Plastic SDIP
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FEDL6650-03 Semiconductor MSM6650 Family
PIN DESCRIPTIONS
1. MSM6652/53/54/55/56-xxx, MSM6652A/53A/54A/55A/56A/58A-xxx 18-Pin plastic DIP
Pin 5 Symbol Type RESET I Description Reset. Setting this pin to "L" puts the LSI in standby status. At this time, oscillation stops, AOUT is pulled to GND, and the deveice is initialized. This pin has an internal pull-up resistor. Busy. This pin outputs a "L" level during playback. At power-on, this pin is at "H" level. XT/CR selectable pin. Set to "H" level when using ceramic oscillation. Set to "L" level when using RC oscillation. Sound Output. This is the synthesized output pin of the internal low-pass filter. Oscillator 1. This pin is a ceramic oscillator connection pin when using ceramic oscillation. This pin is an RC connection pin when using RC oscillation. When using an external clock, use this pin as the clock input. Oscillator 2. This pin is a ceramic oscillator connection pin when using a ceramic oscillator. This is an RC connection pin when using RC oscillation. Leave open if using an external clock. OSC2 outputs a "L" level in standby status. Oscillator 3. Leave open if using a ceramic oscillator. This pin is the RC connection pin when using RC oscillation. When RC oscillation is selected, OSC3 outputs a "H" level in standby status. Random Playback. Random playback starts when the RND pin is set to a "L" level. At the fall of RND, addresses from the random address playback circuit inside the IC are fetched. Set to a "H" level if random playback is not used. This pin has an internal pull-up resistor. Phrase Inputs. These pins are phrase input pins corresponding to playback. If the input changes, SW0 to SW3 pins capture address data after 16 ms and speech playback commences. These pins have internal pull-down resistors. Phrase Inputs. Phrase input pins correspoding to playback. The A0 input becomes invalid when the random playback function is used. Ground. Power supply. Insert a 0.1mF or more bypass capacitor between this pin and GND. Test Mode. Set to "H" level. This pin has an internal pull-up resistor.
6 7 8 11
BUSY XT/CR AOUT OSC1
O I O I
12
OSC2
O
13
OSC3
O
14
RND
I
15-18
SW0-SW3
I
1-3 9 10 4
A0-A2 GND VDD TEST
I -- -- I
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FEDL6650-03 Semiconductor 2.MSM66P54-XX, MSM66P56-xx 20-Pin plastic DIP
Pin 6 Symbol Type RESET I Description Reset. Setting this pin to "L" puts the LSI in standby status. At this time, oscillation stops, AOUT is pulled to GND, and the deveice is initialized. This pin has an internal pull-up resistor. Busy. This pin outputs a "L" level during playback. At power-on, this pin is at "H" level. XT/CR selectable pin. Set to "H" level when using ceramic oscillation. Set to "L" level when using RC oscillation. Sound Output. This is the synthesized output pin of the internal low-pass filter. Oscillator 1. This pin is a ceramic oscillator connection pin when using ceramic oscillation. This pin is an RC connection pin when using RC oscillation. When using an external clock, use this pin as the clock input. Oscillator 2. This pin is a ceramic oscillator connection pin when using a ceramic oscillator. This is an RC connection pin when using RC oscillation. Leave open if using an external clock. OSC2 outputs a "L" level in standby status. Oscillator 3. Leave open if using a ceramic oscillator. This pin is the RC connection pin when using RC oscillation. When RC oscillation is selected, OSC3 outputs a "H" level in standby status. Random Playback. Random playback starts when the RND pin is set to a "L" level. At the fall of RND, addresses from the random address playback circuit inside the IC are fetched. Set to a "H" level if random playback is not used. This pin has an internal pull-up resistor. Phrase Inputs. These pins are phrase input pins corresponding to playback. If the input changes, SW0 to SW3 pins capture address data after 16 ms and speech playback commences. These pins have internal pull-down resistors. Phrase Inputs. Phrase input pins correspoding to playback. The A0 input becomes invalid when the random playback function is used. Ground. Power supply. Insert a 0.1mF or more bypass capacitor between this pin and GND. Test Mode. Set to "H" level. This pin has an internal pull-up resistor. Power supply used when writing data to internal OTP ROM. Leave open or set to "H" level during playback. Interface with voice analysis edit tool AR203 or AR204. Set to "L" level or leave open during playback.
MSM6650 Family
7 8 9 12
BUSY XT/CR AOUT OSC1
O I O I
13
OSC2
O
14
OSC3
O
15
RND
I
16-19
SW0-SW3
I
2-4 10 11 5 1 20
A0-A2 GND VDD TEST VPP PGM
I -- -- I -- I
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FEDL6650-03 Semiconductor MSM6650 Family
3.MSM6652/53/54/55/56-xxx, MSM6652A/53A/54A/55A/56A/58A-xxx, MSM66P54-XX, MSM66P56-xx 24-Pin plastic SOP
Pin 17 Symbol Type RESET I Description Reset. Setting this pin to "L" puts the LSI in standby status. At this time, oscillation stops, AOUT is pulled to GND, and the deveice is initialized. This pin has an internal pull-up resistor. Busy. This pin outputs a "L" level during playback. At power-on, this pin is at "H" level. XT/CR selectable pin. Set to "H" level when using ceramic oscillation. Set to "L" level when using RC oscillation. Sound Output. This is the synthesized output pin of the internal low-pass filter. Oscillator 1. This pin is a ceramic oscillator connection pin when using ceramic oscillation. This pin is an RC connection pin when using RC oscillation. When using an external clock, use this pin as the clock input. Oscillator 2. This pin is a ceramic oscillator connection pin when using a ceramic oscillator. This is an RC connection pin when using RC oscillation. Leave open if using an external clock. OSC2 outputs a "L" level in standby status. Oscillator 3. Leave open if using a ceramic oscillator. This pin is the RC connection pin when using RC oscillation. When RC oscillation is selected, OSC3 outputs a "H" level in standby status. Random Playback. Random playback starts when the RND pin is set to a "L" level. At the fall of RND, addresses from the random address playback circuit inside the IC are fetched. Set to a "H" level if random playback is not used. This pin has an internal pull-up resistor. Phrase Inputs. These pins are phrase input pins corresponding to playback. If the input changes, SW0 to SW3 pins capture address data after 16 ms and speech playback commences. These pins have internal pull-down resistors. Phrase Inputs. Phrase input pins correspoding to playback. The A0 input becomes invalid when the random playback function is used. Ground. Power supply. Insert a 0.1mF or more bypass capacitor between this pin and GND. Test Mode. Set to "H" level. This pin has an internal pull-up resistor. Power supply used when writing data to internal OTP ROM. Leave open or set to "H" level during playback. Interface with voice analysis edit tool AR203 or AR204. Set to "L" level or leave open during playback.
20 22 23 2
BUSY XT/CR AOUT OSC1
O I O I
3
OSC2
O
5
OSC3
O
8
RND
I
9-12
SW0-SW3
I
13-15 24 1 16 18 7
A0-A2 GND VDD TEST VPP* PGM*
I -- -- I -- I
* Pins for MSM66P54/56-xx only
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FEDL6650-03 Semiconductor 4.MSM6650 64-Pin plastic QFP (64-Pin plastic SDIP)
Pin 29(19) Symbol Type RESET I Description Reset. Setting this pin to "L" puts the LSI in standby status. At this time, oscillation stops, AOUT is pulled to GND, and the deveice is initialized. This pin has an internal pull-up resistor. Busy. This pin outputs a "L" level during playback. At power-on, this pin is at "H" level. XT/CR selectable pin. Set to "H" level when using ceramic oscillation. Set to "L" level when using RC oscillation. Sound Output. This is the synthesized output pin of the internal low-pass filter. Oscillator 1. This pin is a ceramic oscillator connection pin when using ceramic oscillation. This pin is an RC connection pin when using RC oscillation. When using an external clock, use this pin as the clock input. Oscillator 2. This pin is a ceramic oscillator connection pin when using a ceramic oscillator. This is an RC connection pin when using RC oscillation. Leave open if using an external clock. OSC2 outputs a "L" level in standby status. Oscillator 3. Leave open if using a ceramic oscillator. This pin is the RC connection pin when using RC oscillation. When RC oscillation is selected, OSC3 outputs a "H" level in standby status. Random Playback. Random playback starts when the RND pin is set to a "L" level. At the fall of RND, addresses from the random address playback circuit inside the IC are fetched. Set to a "H" level if random playback is not used. This pin has an internal pull-up resistor. Phrase Inputs. These pins are phrase input pins corresponding to playback. If the input changes, SW0 to SW3 pins capture address data after 16 ms and speech playback commences. These pins have internal pull-down resistors. Phrase Inputs. Phrase input pins correspoding to playback. The A0 input becomes invalid when the random playback function is used.
MSM6650 Family
3(57) 15(5) 5 (59) 10(64)
BUSY XT/CR AOUT XT/OSC1
O I O I
11(1)
XT/OSC2
O
12(2)
OSC3
O
14(4)
RND
I
21-24 (11-14) 25-27 (15-17)
SW0-SW3
I
A0-A2
I
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FEDL6650-03 Semiconductor MSM6650 Family
Pin 6 (60) 7 (61) 8 (62) 9 (63) 16 (6) 13, 28 (3, 18) 17 (7) 18 (8) 20 (10) 30 (20)
Symbol Type AGND DGND AVDD DVDD CPU TEST1, 3 TEST2 IBUSY STANDBY CE -- -- -- -- I I I O O O Analog ground pin. Digital ground pin.
Description
Analog power pin. Insert a 0.1 mF or more bypass capacitor in between this pin and AGND. Digiral power pin. Insert a 0.1 mF or more bypass capacitor in between this pin and DGND. CPU Mode. Set to "L" level to select Standalone Mode. Set to "H" level to select Microcontroller Interface Mode. Test. Set these pins to "H" level. The TEST1 and TEST3 pins have internal pull-up resistor. Test. Set this pin to "L" level. I Busy. Outputs a "L" level during voice playback (except during standby conversion time), or when the AOUT pin is at half VDD level. Standby Indicator. This output pin remains at "L" level during oscillation. Chip Enable. CE is a timing output pin to control read of external memory. This pin outputs when RCS is at the "L" level. This pin goes high impedance when RCS is at the "H" level. Read Chip Select. The data bits D0-D7 are internally pulled down when RCS
31 (21) 32, 34-40 (22, 24-30) 41-63 (31-40, 42-54)
RCS
I
is high. Addresses and CE are output when RCS is at "L" level. The RA22-RA0 address pins and CE pin become high impedance. External Memory Data Bus. Data is input when RCS is low. When RCS is high, these pins become low due to internal pull-down resistors. External Memory Address. These are address pins for an external memory output when RCS is low. These pins become high impedance status if RCS is in "H" level. Standby Contorl. If set to "L" level, the MSM6650 enters standby mode 0.2
D0-D7
I
RA0-RA22
O
64 (55)
STBY
I
seconds after voice ends. If set to "H" level, the MSM6650 AOUT output maintains half VDD after voice ends.
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FEDL6650-03 Semiconductor MSM6650 Family
ABSOLUTE MAXIMUM RATINGS
(GND=0 V) Parameter Power supply voltage Input voltage Storage temperature Symbol VDD VIN TSTG -- Condition Ta = 25C Rating -0.3 to +7.0 -0.3 to VDD+0.3 -55 to +150 Unit V V C
RECOMMENDED OPERATING CONDITIONS
(GND=0 V) Parameter Power supply voltage Operating temperature Master clock frequency 1 Master clock frequency 2 Symbol VDD VDD Top fOSC1 fOSC2 Condition MSM6652-56, MSM6650, MSM6652A-56A MSM6658A, MSM66P54/P56 -- When crystal selected When RC selected (*) Min. 3.5 200 Range 2.4 to 5.5 3.5 to 5.5 -40 to +85 Typ. 4.096 256 Max. 4.5 300 Unit V V C MHz kHz
*
If RC oscillation is selected, 32kHz sampling frequency cannot be selected.
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FEDL6650-03 Semiconductor MSM6650 Family
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter "H" input voltage "L" input voltage "H" output voltage "L" output voltage "H" input current 1 "H" input current 2 "L" input current 1 "L" input current 2 (note) Operating power consumption Standby power consumption Symbol VIH VIL VOH VOL IIH1 IIH2 IIL1 IIL2 IDD IDS (VDD=4.5 to 5.5 V, GND=0 V, Ta=-40 to +85C) Condition Min. Typ. Max. Unit 0.84VDD -- -- -- V -- IOH=-1 mA IOL=2 mA VIH=VDD Internal pull-down resistance VIL=GND Internal pull-up resistance fOSC=4.096 MHz, No load Ta=-40C to +50C Ta=-40C to +85C -- 4.6 -- -- 30 -10 -200 -- -- -- -- -- -- -- 90 -- -90 6 -- -- 0.17VDD -- 0.4 10 200 -- -30 10 10 30 V V V mA mA mA mA mA mA mA
DC Characteristics
(VDD=2.4 to 3.6 V, GND=0 V, Ta=-40 to +85C) Parameter "H" input voltage "L" input voltage "H" output voltage "L" output voltage "H" input current 1 "H" input current 2 "L" input current 1 "L" input current 2 Operating power consumiption Standby power consumption LPF driving resistance LPF output impedance Symbol VIH VIL VOH VOL IIH1 IIH2 IIL1 IIL2 IDD IDS RAOUT RLPF Condition -- -- IOH=-1 mA IOL=2 mA VIH=VDD Internal pull-down resistance VIL=GND Internal pull-up resistance fOSC=4.096 MHz, No load Ta=-40C to +50C Ta=-40C to +85C When LPF output is selected IF=100 mA Min. Typ. 0.84VDD -- -- 2.6 -- -- 10 -10 -100 -- -- -- 50 -- -- -- -- -- 30 -- -30 4 -- -- -- 1 Max. -- 0.17VDD -- 0.4 10 100 -- -10 7 5 20 -- 3 Unit V V V V mA mA mA mA mA mA mA kW kW
16/45
FEDL6650-03 Semiconductor MSM6650 Family
APPLICATION CIRCUITS
(MSM6652/53/54/55/56-xxx, MSM6652A/53A/54A/55A/56A/58A-xxx, MSM66P54/P56-xx)
OSC3
OSC2
AOUT
XT/CR
TEST
SW0
SW1
SW2
SW3
RND A0
A1
Application Circuit in Standalone Mode Supporting 15 Switch-Selected Phrases 17/45
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A2
GND
VDD
MSM6652/53/54/55/56 MSM6652A/53A/54A/55A/56A/58A MSM66P54/P56
OSC1
FEDL6650-03 Semiconductor MSM6650 Family
(MSM6652/53/54/55/56-xxx, MSM6652A/53A/54A/55A/56A/58A-xxx, MSM66P54/P56-xx)
VDD S4 S3 S2 S1 SW1 SW2 SW3 TEST RND XT/CR A0 A1 A2 GND
MSM6652/53/54/55/56 MSM6652A/53A/54A/55A/56A/58A MSM66P54/P56
VDD
SW0
AOUT
OSC3 OSC2 OSC1
Application Circuit in Standalone Mode Supporting Four Switch-Selected Words
Switches and Playback Addresses
A2 S1 S2 S3 S4 0 0 0 0 A1 0 0 0 0 A0 0 0 0 0 SW3 0 0 0 1 SW2 0 0 1 0 SW1 0 1 0 0 SW0 1 0 0 0 ADR 01 02 04 08
18/45
FEDL6650-03 Semiconductor MSM6650 Family
(MSM6650)
MSM27C512
A15 O7 O0 A0 OE CE OSC3 OSC2 OSC1 A2
DGND AGND
VPP
RA15
RA0
D7
DVDD
AOUT
MSM6650
SW0 SW1 SW2 SW3 A1
Application Circuit in Standalone Mode Supporting 15 Switch-Selected Phrases
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
XT/CR D0 TEST1,3 RND CE A0
AVDD
GND
VCC
19/45
Semiconductor
(MSM6650)
2G 1B 1Y3 1Y2 1Y1 1A 1Y0 1G
74HC139
Application Circuit in Standalone Mode Supporting Four 1-Mbit EPROMs
DVDD
AVDD
CE AOUT RA18 SW0 RA17 SW1 RA16 SW2 SW3
VPP OE A16
VDD
VPP OE A16
VDD
VPP OE A16
VDD
VPP OE A16
VDD
RA0 TEST1 TEST3 D7 RND TEST2 STBY D0 XT/CR CPU OSC3 A0 OSC2 A1 OSC1 A2
DGND AGND
MSM6650
MSM27C101
GND
MSM27C101
MSM27C101
MSM27C101
A0 O7
A0 O7
A0 O7
A0 O7
O0
O0
O0
O0
MSM6650 Family
FEDL6650-03
CE
CE
GND
CE
GND
CE
GND
20/45
FEDL6650-03 Semiconductor MSM6650 Family
MICROCONTROLLER INTERFACE MODE
FEATURES
Device name MSM6652, 6652A MSM6653, 6653A MSM6654, 6654A MSM6655, 6655A MSM6656, 6656A MSM6658A MSM66P54 MSM66P56 MSM6650 Maximum playback time (sec) Data ROM size fSAM=4.0 kHz fSAM=6.4 kHz fSAM=8.0 kHz fSAM=16 kHz fSAM=32 kHz 288 Kbits 544 Kbits 1 Mbit 1.5 Mbits 2 Mbits 4 Mbits 1 Mbit 2 Mbit 64 Mbits (Max) 16.9 31.2 63.8 96.5 129.1 259.7 63.8 129.1 4194.3 10.5 19.5 39.9 60.3 80.7 162.9 39.9 80.7 2620.5 8.4 15.6 31.9 48.2 64.5 129.8 31.9 64.5 2096.4 4.2 7.8 15.9 24.1 32.2 64.9 15.9 32.2 1048.2 2.1 3.9 7.9 12.0 16.1 32.4 7.9 16.1 524.1
Note: Actual voice ROM area is smaller by 22 Kbits. * 4-bit ADPCM or 8-bit PCM sound generation * Melody function * Edit ROM function * Two-channel mixing function * Fade-out function via four-step sound volume attenuation * Serial input or parallel input selectable * Built-in beep tone of 0.5 kHz, 1.0 kHz, 1.3 kHz, or 2.0 kHz selectable with a specific code * Sampling frequency of 4.0 kHz, 5.3 kHz, 6.4 kHz, 8.0 kHz, 10.6 kHz, 12.8 kHz, 16.0 kHz, or 32.0 kHz (32 kHz sampling is not possible when using RC oscillation) * Up to 127 phrases * Built-in 12-bit D/A converter * Built-in -40 dB/octave low-pass filter * Standby function * Package options: 18-pin plastic DIP (DIP18-P-300-2.54) (Product name: MSM6652-xxxRS/MSM6653-xxxRS/ MSM6654-xxxRS/MSM6655-xxxRS/ MSM6656-xxxRS/MSM6652A-xxxRS/ MSM6653A-xxxRS/MSM6654A-xxxRS/ MSM6655A-xxxRS/MSM6656A-xxxRS/ MSM6658A-xxxRS) 24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name:MSM6652-xxxGS-K/MSM6653-xxxGS-K/ MSM6654-xxxGS-K/MSM6655-xxxGS-K/ MSM6656-xxxGS-K/MSM6652A-xxxGS-K/ MSM6653A-xxxGS-K/MSM6654A-xxxGS-K/ MSM6655A-xxxGS-K/MSM6656A-xxxGS-K/ MSM6658A-xxxGS-K/MSM66P54-01GS-K/ MSM66P54-02GS-K/MSM66P56-01GS-K/ MSM66P56-02GS-K) 20-pin plastic DIP (DIP20-P-300-2.54-W1) (Product name: MSM66P54-01RS/MSM66P54-02RS/ MSM66P56-01RS/MSM66P56-02RS) 64-pin plastic QFP (QFP64-P-1420-1.00-BK)(Product name: MSM6650GS-BK) 64-pin plastic SDIP (SDIP64-P-750-1.778) (Product name: MSM6650SS)
21/45
Semiconductor
MSM6652/53/54/55/56-xxx MSM6652A/53A/54A/55A/56A/58A-xxx
BLOCK DIAGRAMS
I6/SD I5/SI I4 I3/PORT1 I2/PORT0 I1 I0
Address & Command Controller
7
16-Bit (MSM6652/52A) 17-Bit (MSM6653/53A) 17-Bit (MSM6654/54A) 18-Bit (MSM6655/55A) 18-Bit (MSM6656/56A) 19-Bit (MSM6658A) Multiplexer
(MSM6652/52A) (MSM6653/53A) (MSM6654/54A) (MSM6655/55A) (MSM6656/56A) (MSM6658A) ROM (Containing 22-Kbit Phrase Control Table & Phrase Address Table)
288-Kbit 544-Kbit 1-Mbit 1.5-Mbit 2-Mbit 4-Mbit
8
CH ST CMD BUSY NAR I/O Interface
16-Bit (MSM6652/52A) 17-Bit (MSM6653/53A) 17-Bit (MSM6654/54A) 18-Bit (MSM6655/55A) 18-Bit (MSM6656/56A) 19-Bit (MSM6658A) Address Counter
DATA Controller
ADPCM Synthesizer
PCM Synthesizer 12 Melody Generator 12-Bit DAC
XT OSC XT Timing Controller BEEP Tone Generator LPF
MSM6650 Family
FEDL6650-03
22/45
RESET
VDD
GND
AOUT
Semiconductor
MSM66P54/P56-xx
VPP
PGM
Program Circuit I6/SD I5/SI I4 I3/PORT1 I2/PORT0 I1 I0
Address & Command Controller
7
17-Bit (MSM66P54-XX) 18-Bit (MSM66P56-xx) Multiplexer
1-Mbit OTP ROM (MSM66P54-XX) 2-Mbit OTP ROM (MSM66P56-xx)
(Containing 22-Kbit Phrase Control Table & Phrase Address Table)
8
ADPCM Synthesizer CH ST CMD BUSY NAR 12 12-Bit DAC I/O Interface 17-Bit (MSM66P54-XX) 18-Bit (MSM66P56-xx) Address Counter DATA Controller PCM Synthesizer
Melody Generator XT XT OSC Timing Controller BEEP Tone Generator
MSM6650 Family
LPF
FEDL6650-03
23/45
RESET
VDD
GND
AOUT
RA22
RA0
D7
D0
Semiconductor
MSM6650
I6/SD I5/SI I4 I3/PORT1 I2/PORT0 I1 I0
8-Bit LATCH Address & Switching Controller 7 23-Bit Multiplexer 8
CH ST CMD CE RCS BUSY NAR IBUSY STANDBY
DATA Controller 23-Bit Address Counter I/O Interface
ADPCM Synthesizer
PCM Synthesizer 12 Melody Generator 12-Bit DAC
XT XT MCK OSC Timing Controller BEEP Tone Generator LPF
MSM6650 Family
FEDL6650-03
24/45
TEST1
RESET CPU TEST2 SERIAL DVDD DGND
AGND AVDD AOUT
FEDL6650-03 Semiconductor MSM6650 Family
PIN CONFIGURATION (TOP VIEW)
The MSM66P54/P56-xx has two more pins than the MSM6652-6658A while their pin configurations are identical. The additional two pins (VPP, PGM) of the MSM66P54/P56-xx may be open at playback after completion of writing.
MSM6652-6658A (Mask ROM)
I4 I5/SI I6/SD CH RESET BUSY 1 2 3 4 5 6 7 8 9 18 I3/PORT1 17 I2/PORT0 16 I1 15 I0 14 ST
MSM66P54/P56 (OTP)
VPP I4 I5/SI I6/SD CH 1 2 3 4 5 6 7 8 9 20 PGM 19 I3/PORT1 18 I2/PORT0 17 I1 16 I0 15 ST 14 CMD 13 XT 12 XT 11 VDD
MSM6652-xxxRS, MSM6653-xxxRS, MSM6654-xxxRS, MSM6655-xxxRS, MSM6656-xxxRS, MSM6652A-xxxRS, MSM6653A-xxxRS, MSM6654A-xxxRS, MSM6655A-xxxRS, MSM6656A-xxxRS, MSM6658A-xxxRS
MSM6652-6658A (Mask ROM)

13 CMD 12 XT 11 XT RESET BUSY NAR NAR AOUT GND 10 VDD AOUT
18-Pin Plastic DIP
GND 10
20-Pin Plastic DIP
MSM66P54-01/-02RS MSM66P56-01/-02RS
MSM66P54/P56 (OTP)
24 23 22 21 20 19 18 17 16 15 14 13 GND AOUT NAR NC BUSY NC VPP RESET CH I6/SD I5/SI I4
VDD XT XT
1 2 3 4 5 6 7 8 9
24 23 22 21 20 19 18 17 16 15 14 13
GND
VDD XT XT
1 2 3 4 5 6 7 8 9
AOUT NAR NC
NC
NC
CMD NC NC ST I0 I1
BUSY NC NC
CMD NC
PGM ST I0 I1
RESET CH I6/SD I5/SI I4
10 11 12
10 11 12
I2/PORT0 I3/PORT1
I2/PORT0 I3/PORT1
24-Pin Plastic SOP
24-Pin Plastic SOP
MSM6652-xxxGS-K, MSM6653-xxxGS-K, MSM6654-xxxGS-K, MSM6655-xxxGS-K, MSM6656-xxxGS-K, MSM6652A-xxxGS-K, MSM6653A-xxxGS-K, MSM6654A-xxxGS-K, MSM6655A-xxxGS-K, MSM6656A-xxxGS-K, MSM6658A-xxxGS-K
MSM66P54-01/-02GS-K MSM66P56-01/-02GS-K
25/45
Semiconductor MSM6650
Product name: MSM6650GS-BK
NC NC BUSY NAR AOUT AGND DGND AVDD DVDD XT XT MCK CMD ST TEST1 CPU SERIAL IBUSY NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
STANDBY I0 I1 I2/PORT0 I3/PORT1 I4 I5/SI I6/SD CH RESET CE RCS D0
,
64 63 62 61 60 59 58 57 20 21 22 23 24 25 26 27
FEDL6650-03 MSM6650 Family
56
55
54
53
52
TEST2 RA22 RA21 RA20 RA19 RA18 RA17 RA16 RA15 RA14 RA13 RA12 RA11
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
RA10 RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 D7 D6 D5 D4 D3 D2 D1 NC
28
29
30
31
NC : No connection 64-Pin Plastic QFP
32
26/45
FEDL6650-03 Semiconductor Product name: MSM6650SS MSM6650 Family
XT MCK CMD ST TEST1 CPU SERIAL IBUSY NC STANDBY I0 I1 I2/PORT0 I3/PORT1 I4 I5/SI I6/SD CH RESET CE RCS D0 NC D1 D2 D3 D4 D5 D6 D7 RA0 RA1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
XT DVDD AVDD DGND AGND AOUT NAR BUSY NC TEST2 RA22 RA21 RA20 RA19 RA18 RA17 RA16 RA15 RA14 RA13 RA12 RA11 RA10 NC RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2
NC : No connection 64-Pin Plastic SDIP
27/45
FEDL6650-03 Semiconductor MSM6650 Family
PIN DESCRIPTIONS
1.MSM6652/53/54/55/56-xxx, MSM6652A/53A/54A/55A/56A/58A-xxx 18-Pin plastic DIP
Pin 5 Symbol Type RESET I Description Reset. The devices enter stanby status when a low level is input to this pin. When RESET, oscillation stops. The AOUT output goes to ground and the IC status is reinitialized. This pin has an internal pull-up resistor. Busy. Outputs a "L" level during playback and a "H" level when power is turned ON. The CMD and ST inputs become effective when high. NAR indicates whether the 7 NAR O address bus (I0 through I6) is ready to accept another address. When high, it is ready to accept. NAR goes high when power is turned ON. 8 11 12 AOUT XT XT CMD O I O Analog Speech Output. D/A converter output or LPF output is selected by entering the command. Ceramic Oscillator Input. This pin has an internal 0.5 to 5 MW feedback resistor between XT and XT. If an external clock is used, this is the clock input pin. Ceramic Oscillator Output. If an external clock is used, leave this pin open. Command Input and Option Control. This pin is used as command and option input when CMD is at the high level with ST low. If this pin is not used or serial input is optioned, set this pin to "H" level. This pin has an internal pull-up resistor. Start. Speech playback starts at the fall of the ST pulse. The I0 - I6 addresses are latched at the rise of the ST pulse. Input a ST pulse when NAR goes to the high level for channels 1 and 2. This pin has an internal pull-up resistor. Channel Control. Channel 1 is selected when the input is pulled high. Channel 2 is selected when the input is low. This pin has an internal pull-up resistor. This pin is command and user-defined phrase input when parallel input is optioned. This pin is serial data (command and address) input when serial input is optioned. This pin is command and user-defined phrase input when parallel input is optioned. This pin is used as serial clock input when serial input is optioned. This pin is command and user-defined phrase input when parallel input is optioned. When serial input is optioned, set this pin to "L" level. This pin has an internal pull-down resistor. This pin is command and user-defined phrase input when parallel input is optioned. 18 I3/PORT1 I/O When serial input is optioned, this pin is a port output. The port output is controlled by entering external silence insertion code. This pin is command and user-defined phrase input when parallel input is optioned. 17 I2/PORT0 I/O When serial input is optioned, this pin is a port output. The port output is controlled by entering external silence insertion code. This pin is command and user-defined phrase input when parallel input is optioned. 15, 16 9 10 I0, I1 GND VDD I -- -- When serial input is optioned, set this pin to "L" level. This pin has an internal pull-down resistor. Ground pin. Power supply. Insert a 0.1F ro more bypass capacitor between this pin and GND.
6
BUSY
O
13
I
14
ST CH I6/SD I5/SI
I
4 3 2
I I I
1
I4
I
28/45
FEDL6650-03 Semiconductor MSM6650 Family
2.MSM66P54/P56-xx 20-Pin plastic DIP
Pin 6 Symbol Type RESET I Description Reset. The devices enter stanby status when a low level is input to this pin. When RESET, oscillation stops. The AOUT output goes to ground and the IC status is reinitialized. This pin has an internal pull-up resistor. Busy. Outputs a "L" level during playback and a "H" level when power is turned ON. The CMD and ST inputs become effective when high. NAR indicates whether the 8 NAR O address bus (I0 through I6) is ready to accept another address. When high, it is ready to accept. NAR goes high when power is turned ON. 9 12 13 AOUT XT XT CMD O I O Analog Speech Output. D/A converter output or LPF output is selected by entering the command. Ceramic Oscillator Input. This pin has an internal 0.5 to 5 MW feedback resistor between XT and XT. If an external clock is used, this is the clock input pin. Ceramic Oscillator Output. If an external clock is used, leave this pin open. Command Input and Option Control. This pin is used as command and option input when CMD is at the high level with ST low. If this pin is not used or serial input is optioned, set this pin to "H" level. This pin has an internal pull-up resistor. Start. Speech playback starts at the fall of the ST pulse. The I0 - I6 addresses are latched at the rise of the ST pulse. Input a ST pulse when NAR goes to the high level for channels 1 and 2. This pin has an internal pull-up resistor. Channel Control. Channel 1 is selected when the input is pulled high. Channel 2 is selected when the input is low. This pin has an internal pull-up resistor. This pin is command and user-defined phrase input when parallel input is optioned. This pin is serial data (command and address) input when serial input is optioned. This pin is command and user-defined phrase input when parallel input is optioned. This pin is used as serial clock input when serial input is optioned. This pin is command and user-defined phrase input when parallel input is optioned. When serial input is optioned, set this pin to "L" level. This pin has an internal pull-down resistor. This pin is command and user-defined phrase input when parallel input is optioned. 19 I3/PORT1 I/O When serial input is optioned, this pin is a port output. The port output is controlled by entering external silence insertion code. This pin is command and user-defined phrase input when parallel input is optioned. 18 I2/PORT0 I/O When serial input is optioned, this pin is a port output. The port output is controlled by entering external silence insertion code. This pin is command and user-defined phrase input when parallel input is optioned. 16, 17 10 11 1 20 I0, I1 GND VDD VPP PGM I -- -- -- I When serial input is optioned, set this pin to "L" level. This pin has an internal pull-down resistor. Ground pin. Power supply. Insert a 0.1F ro more bypass capacitor between this pin and GND. Supply voltage for writing data to internal OTP ROM. Interface with voice analysis edit tools AR203 and AR204. Set to "L" level or leave open during playback. This pin has an internal pull-down resistor.
7
BUSY
O
14
I
15
ST CH I6/SD I5/SI
I
5 4 3
I I I
2
I4
I
29/45
FEDL6650-03 Semiconductor MSM6650 Family
3.MSM6652/53/54/55/56-xxx, MSM6652A/53A/54A/55A/56A/58A-xxx, MSM66P54/P56-xx 24-Pin plastic SOP
Pin 17 Symbol Type RESET I Description Reset. The devices enter stanby status when a low level is input to this pin. When RESET, oscillation stops. The AOUT output goes to ground and the IC status is reinitialized. This pin has an internal pull-up resistor. Busy. Outputs a "L" level during playback and a "H" level when power is turned ON. The CMD and ST inputs become effective when high. NAR indicates whether the 22 NAR O address bus (I0 through I6) is ready to accept another address. When high, it is ready to accept. NAR goes high when power is turned ON. 23 2 3 AOUT XT XT CMD O I O Analog Speech Output. D/A converter output or LPF output is selected by entering the command. Ceramic Oscillator Input. This pin has an internal 0.5 to 5 MW feedback resistor between XT and XT. If an external clock is used, this is the clock input pin. Ceramic Oscillator Output. If an external clock is used, leave this pin open. Command Input and Option Control. This pin is used as command and option input when CMD is at the high level with ST low. If this pin is not used or serial input is optioned, set this pin to "H" level. This pin has an internal pull-up resistor. Start. Speech playback starts at the fall of the ST pulse. The I0 - I6 addresses are latched at the rise of the ST pulse. Input a ST pulse when NAR goes to the high level for channels 1 and 2. This pin has an internal pull-up resistor. Channel Control. Channel 1 is selected when the input is pulled high. Channel 2 is selected when the input is low. This pin has an internal pull-up resistor. This pin is command and user-defined phrase input when parallel input is optioned. This pin is serial data (command and address) input when serial input is optioned. This pin is command and user-defined phrase input when parallel input is optioned. This pin is used as serial clock input when serial input is optioned. This pin is command and user-defined phrase input when parallel input is optioned. When serial input is optioned, set this pin to "L" level. This pin has an internal pull-down resistor. This pin is command and user-defined phrase input when parallel input is optioned. 12 I3/PORT1 I/O When serial input is optioned, this pin is a port output. The port output is controlled by entering external silence insertion code. This pin is command and user-defined phrase input when parallel input is optioned. 11 I2/PORT0 I/O When serial input is optioned, this pin is a port output. The port output is controlled by entering external silence insertion code.
20
BUSY
O
5
I
8
ST CH I6/SD I5/SI
I
16 15 14
I I I
13
I4
I
30/45
FEDL6650-03 Semiconductor MSM6650 Family
Pin 9, 10 24 1 18 7
Symbol Type I0, I1 GND VDD VPP * PGM * I -- -- -- I
Description This pin is command and user-defined phrase input when parallel input is optioned. When serial input is optioned, set this pin to "L" level. This pin has an internal pull-down resistor. Ground pin. Power supply. Insert a 0.1F ro more bypass capacitor between this pin and GND. Supply voltage for writing data to internal OTP ROM. Interface with voice analysis edit tools AR761 and AR762. Set to "L" level or leave open during playback. This pin has an internal pull-down resistor.
*
Pins for MSM66P54/56-xx only
31/45
FEDL6650-03 Semiconductor 4.MSM6650 64-Pin plastic QFP (64-Pin plastic SDIP)
Pin 29 (19) Symbol Type RESET I Description Reset. The devices enter stanby status when a low level is input to this pin. When RESET, oscillation stops. The AOUT output goes to ground and the IC status is reinitalized. This pin has an internal pull-up resistor. Busy. Outputs a "L" level during playback and a "H" level when power is turned ON. The CMD and ST inputs become effective when high. NAR indicates whether the 4 (58) NAR O address bus (I0 through I6) is ready to accept another address. When high, it is ready to accept. NAR goes high when power is turned ON. 5 (59) 10 (64) 11 (1) AOUT XT XT CMD O I O Analog Speech Output. D/A converter output or LPF output is selected by entering the command. Ceramic Oscillator Input. This pin has an internal 0.5 to 5 MW feedback resistor between XT and XT. If an external clock is used, this is the clock input pin. Ceramic Oscillator Output. If an external clock is used, leave this pin open. Command Input and Option Control. This pin is used as command and option input when CMD is at the high level with ST low. If this pin is not used or serial input is optioned, set this pin to "H" level. This pin has an internal pull-up resistor. Start. Speech playback starts at the fall of the ST pulse. The I0 - I6 addresses are latched at the rise of the ST pulse. Input a ST pulse when NAR goes to the high level for channels 1 and 2. This pin has an internal pull-up resistor. Channel Control. Channel 1 is selected when the input is pulled high. Channel 2 is selected when the input is low. This pin has an internal pull-up resistor. This pin is command and user-defined phrase input when parallel input is optioned. This pin is serial data (command and address) input when serial input is optioned. This pin is command and user-defined phrase input when parallel input is optioned. This pin is used as serial clock input when serial input is optioned. This pin is command and user-defined phrase input when parallel input is optioned. When serial input is optioned, set this pin to "L" level. This pin has an internal pull-down resistor. This pin is command and user-defined phrase input when parallel input is optioned. 24 (14) I3/PORT1 I/O When serial input is optioned, this pin is a port output. The port output is controlled by entering external silence insertion code. This pin is command and user-defined phrase input when parallel input is optioned. 23 (13) I2/PORT0 I/O When serial input is optioned, this pin is a port output. The port output is controlled by entering external silence insertion code. This pin is command and user-defined phrase input when parallel input is optioned. 21, 22 (11, 12) I0, I1 I When serial input is optioned, set this pin to "L" level. This pin has an internal pull-down resistor.
MSM6650 Family
3 (57)
BUSY
O
13 (3)
I
14 (4)
ST CH I6/SD I5/SI
I
28 (18) 27 (17) 26 (16)
I I I
25 (15)
I4
I
32/45
FEDL6650-03 Semiconductor MSM6650 Family
Pin 6 (60) 7 (61) 8 (62) 9 (63) 12 (2) 16 (6) 17 (7)
Symbol Type AGND DGND AVDD DVDD MCK CPU SERIAL -- -- -- -- O I I Analog ground pin. Digital ground pin.
Description
Analog power pin. Insert a 0.1mF or more bypass capacitor between this pin and AGND. Digital power pin. Insert a 0.1mF or more bypass capacitor between this pin and DGND. Main clock output pin. Use MCK as a connection pin for the MSC1192, etc. When the IC is in standby status, MCK is held high. CPU Mode. Set to "H" level to select Microcontroller Interface Mode. Serial/Parallel Interface Select. This input selects either the parallel or the serial input interface. The serial input interface is selected with a high level; the parallel input interface is selected with a low level. Chip Enable. CE is a timing output pin to control read of external memory. This pin outputs when RCS is at the "L" level. This pin goes high impedance when RCS is at the "H" level. Read Chip Select. The data bits D0-D7 are internally pulled down when RCS is high. External Memory Data Bus. Data is input when RCS is low. When RCS is high, these pins become low due to internal pull-down resistors. External Memory Address. These are address pins for an external memory output when RCS is low. These pins become high impedance status if RCS is in "H" level. Test. Set these pins to "H" level. Outputs a "L" level during playback or when AOUT is at 1/2 VDD (except standby conversion) Outputs a "L" level during which the device is oscillating.
30 (20) 31 (21) 32, 34-40 (22, 24-30) 41-63 (31-40, 42-54) 15, 64 (5, 55) 18 (8) 20 (10)
CE RCS D0 - D7 RA0 - RA22 TEST1, 2 IBUSY STANDBY
O I I O I O O
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FEDL6650-03 Semiconductor MSM6650 Family
ABSOLUTE MAXIMUM RATINGS
(GND=0 V) Parameter Power supply voltage Input voltage Storage temperature Symbol VDD VIN TSTG -- Condition Ta = 25C Rating -0.3 to +7.0 -0.3 to VDD+0.3 -55 to +150 Unit V V C
RECOMMENDED OPERATING CONDITIONS
(GND=0 V) Parameter Power supply voltage Operating temperature Master clock frequency Symbol VDD Top fOSC Condition MSM6652-56, MSM6650, MSM6652A-56A MSM6658A, MSM66P54/P56 -- -- Min. 3.5 Range 2.4 to 5.5 3.5 to 5.5 -40 to +85 Typ. 4.096 Max. 4.5 Unit V V C MHz
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FEDL6650-03 Semiconductor MSM6650 Family
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter High level input voltage Low level input voltage High level output voltage Low level output voltage High level input current 1 High level input current 2 Low level input current 1 Low level input current 2 Operating current Standby current D/A output relative accuracy D/A output impedance LPF driving resisance LPF output impedance
*1
Symbol VIH VIL VOH VOL IIH1 IIH2 IIL1 IIL2 IDD IDS |VDAE| RDAO RAOUT RLPF
Condition -- -- IOH=-1 mA IOL=2 mA VIH=VDD
(VDD=4.5 to 5.5 V, GND=0 V, Ta=-40 to +85C) Min. Typ. Max. Unit 0.84VDD -- -- V -- 4.6 -- -- 30 -10 -200 -- -- -- -- 15 15 50 -- -- -- -- -- 90 -- -90 6 -- -- -- 25 30 -- 1 0.17VDD -- 0.4 10 200 -- -30 10 10 30 40 35 45 -- 3 V V V mA mA mA mA mA mA mA mV kW kW kW kW
Internal pull-down resistor VIL=GND Internal pull-up resistor fOSC=4.096 MHz, No load Ta=-40C to +50C Ta=-40C to +85C When D/A output selected When D/A output selected *2 When D/A output selected *3 When LPF output selected
IF=100 mA
*1. Applied to RESET, CMD, ST, CH. *2. Applied to MSM6652/53/54/55/56, MSM6652A/53A/54A/55A/56A/58A, MSM6650. *3. Applied to MSM66P54/P56. DC Characteristics
Parameter High level input voltage Low level input voltage High level output voltage Low level output voltage High level input current 1 High level input current 2 Low level input current 1 Low level input current 2 (Note) Operating current Standby current D/A output relative accuracy D/A output impedance LPF driving resistance LPF output impedance Symbol VIH VIL VOH VOL IIH1 IIH2 IIL1 IIL2 IDD IDS |VDAE| RDAO RAOUT RLPF Condition -- -- IOH=-1 mA IOL=2 mA VIH=VDD Internal pull-down resistor VIL=GND Internal pull-up resistor fOSC=4.096 MHz, No load Ta=-40C to +50C Ta=-40C to +85C When D/A output selected When D/A output selected When LPF output selected IF=100 mA (VDD=2.4 to 3.6 V, GND=0 V, Ta=-40 to +85C) Min. Typ. 0.84VDD -- -- 2.6 -- -- 10 -10 -100 -- -- -- -- 15 50 -- -- -- -- -- 30 -- -30 4 -- -- -- 25 -- 1 Max. -- 0.17VDD -- 0.4 10 100 -- -10 7 5 20 20 35 -- 3 Unit V V V V mA mA mA mA mA mA mA mV kW kW kW
Note: Applied to RESET, CMD, ST, CH.
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FEDL6650-03 Semiconductor MSM6650 Family
APPLICATION CIRCUITS
(MSM6652/53/54/55/56-xxx, MSM6652A/53A/54A/55A/56A/58A-xxx, MSM66P54/P56-xx)
P1.0 P1.1 P1.2 MSM83C154 P2.0 P3.0
I6/SD I5/SI ST RESET NAR
VDD MSM6652/53/54/55/56 MSM6652A/53A/54A/55A/56A/58A MSM66P54/P56 CH CMD
PORT0 PORT1 AOUT I4 I1 I0
XT
AMP
RESET
XT
GND
Application Circuit in Serial Input Interface Mode
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FEDL6650-03 Semiconductor MSM6650 Family
(MSM6652/53/54/55/56-xxx, MSM6652A/53A/54A/55A/56A/58A-xxx, MSM66P54/P56-xx)
P2.0 P3.1 P2.2 P2.1 P3.0
CH CMD ST RESET NAR XT
MSM6652/53/54/55/56 MSM6652A/53A/54A/55A/56A/58A MSM66P54/P56
P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0
I6 I5 I4 I3 I2 I1 I0
VDD
MSM83C154
RESET XT GND
AOUT
AMP
Application circuit in Parallel Input Interface Mode
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Semiconductor
(MSM6650)
1B
2G
74HC139 1Y3 1Y2 1Y1 1Y0
1A 1G
Application Circuit in Microcontroller Interface Mode Using Four 1-Mbit EPROMs (Serial Input Interface)
DVDD
AVDD
AOUT P2.0 P1.0 P1.1 P1.2 P3.0 RESET I6/SD I5/SI ST NAR
CE RA18 RA17 RA16
VPP OE
VDD
VPP OE
VDD
VPP OE
VDD
VPP OE
VDD
RESET
MSM83C154
MSM27C101
MSM27C101
MSM27C101
MSM27C101
A16
A16
A16
A16
CH CMD TEST1 TEST2 CPU SERIAL RCS I4
I1 I0 DGND AGND
MSM6650
RA0 D7 A0 O7 D0 XT XT O0 CE
A0 O7
A0 O7
A0 O7
O0
O0
O0
MSM6650 Family
GND
CE
GND
CE
GND
CE
GND
FEDL6650-03
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Semiconductor
(MSM6650)
1B
2G
74HC139 1Y3 1Y2 1Y1 1Y0
1A
Application Circuit in Microcontroller Interface Mode Using Four 1-Mbit EPROMs (Parallel Input Interface)
1G
DVDD
AVDD
P2.0 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P3.0 P2.1 P2.0 P3.1 P1.0
AOUT RESET I6/SD I5/SI I4 I3 I2 I1 I0 CH ST CMD NAR
CE RA18 RA17 RA16
VPP OE
VDD
VPP OE
VDD
VPP OE
VDD
VPP OE
VDD
RESET TEST1 TEST2 CPU RCS SERIAL D0 XT XT O0 O0 O0 O0
MSM83C154
MSM27C101
MSM27C101
MSM27C101
MSM27C101
A16
A16
A16
A16
DGND AGND
MSM6650
RA0 D7 A0 O7 CE
A0 O7
A0 O7
A0 O7
MSM6650 Family
GND
CE
GND
CE
GND
CE
GND
FEDL6650-03
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FEDL6650-03 Semiconductor MSM6650 Family
PACKAGE DIMENSIONS
(Unit : mm)
DIP18-P-300-2.54
Oki Electric Industry Co., Ltd.
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5 mm) 1.30 TYP. 2/Dec. 11, 1996
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FEDL6650-03 Semiconductor MSM6650 Family
(Unit : mm)
SOP24-P-430-1.27-K
Mirror finish
Oki Electric Industry Co., Ltd.
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5 mm) 0.58 TYP. 5/Oct. 13, 1998
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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FEDL6650-03 Semiconductor MSM6650 Family
(Unit : mm)
DIP20-P-300-2.54-W1
Oki Electric Industry Co., Ltd.
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5 mm) 1.50 TYP. 2/Dec. 11, 1996
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FEDL6650-03 Semiconductor MSM6650 Family
(Unit : mm)
QFP64-P-1420-1.00-BK
Mirror finish
Oki Electric Industry Co., Ltd.
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5 mm) 1.25 TYP. 4/Nov. 28, 1996
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
43/45
FEDL6650-03 Semiconductor MSM6650 Family
(Unit : mm)
SDIP64-P-750-1.778
Oki Electric Industry Co., Ltd.
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin Cu alloy Solder plating (5 mm) 8.70 TYP. 2/Dec. 11, 1996
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