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32K x 32 CacheRAMTM 3.3V Synchronous SRAM Burst Counter Single Cycle Deselect Features
x x
IDT71V432
x
x x
x x x
32K x 32 memory configuration Supports high-performance system speed: Commercial and Industrial: -- 5ns Clock-to-Data Access (100MHz) -- 6ns Clock-to-Data Access (83MHz) -- 7ns Clock-to-Data Access (66MHz) Single-cycle deselect functionality (Compatible with Micron Part # MT58LC32K32D7LG-XX) LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) Power down controlled by ZZ input Operates with a single 3.3V power supply (+10/-5%) Packaged in a JEDEC Standard 100-pin rectangular plastic thin quad flatpack (TQFP).
Description
The IDT71V432 is a 3.3V high-speed 1,048,576-bit CacheRAM organized as 32K x 32 with full support of the PentiumTM and PowerPCTM
processor interfaces. The pipelined burst architecture provides costeffective 3-1-1-1 secondary cache performance for processors up to 100 MHz. The IDT71V432 CacheRAM contains write, data, address, and control registers. Internal logic allows the CacheRAM to generate a selftimed write based upon a decision which can be left until the extreme end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as the IDT71V432 can provide four cycles of data for a single address presented to the CacheRAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will be pipelined for one cycle before it is available on the next rising clock edge. If burst mode operation is selected (ADV=LOW), the subsequent three cycles of output data will be available to the user on the next three rising clock edges. The order of these three addresses will be defined by the internal burst counter and the LBO input pin. The IDT71V432 CacheRAM utilizes IDT's high-performance, highvolume 3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x 20mm 100-pin thin plastic quad flatpack (TQFP) for optimum board density in both desktop and notebook applications.
Pin Description Summary
A0-A14 CE CS0, CS1 OE GW BWE BW1, BW2, BW3, BW4 CLK ADV ADSC ADSP LBO ZZ I/O0-I/O31 VDD VSS Address Inputs Chip Enable Chips Selects Output Enable Global Write Enable Byte Write Enable Individual Byte Write Selects Clock Burst Address Advance Address Status (Cache Controller) Address Status (Processor) Linear / Interleaved Burst Order Sleep Mode Data Input/Output 3.3V Power Ground Input Input Input Input Input Input Input Input Input Input Input Input Input I/O Power Ground Synchronous Synchronous Synchronous Asynchronous Synchronous Synchronous Synchronous N/A Synchronous Synchronous Synchronous DC Asynchronous Synchronous DC DC
3104 tbl 01
CacheRAM is a trademark of Integrated Device Technology. Pentium processor is a trademark of Intel Corp. PowerPC is a trademark of International Business Machines, Inc.
AUGUST 2001
1
DSC-3104/05
(c)2000 Integrated Device Technology, Inc.
IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Definitions(1)
Symbol A0-A14 ADSC Pin Function Address Inputs Address Status (Cache Controller) Address Status (Processor) Burst Address Advance I/O I I Active N/A LOW Description Synchronous Address inputs. The address re gister is triggered by a combination of the rising edge of CLK and ADSC Low or ADSP Low and CE Low. Synchronous Ad dress Status from Cache Controller. ADSC is an active LOW input that is used to load the add ress registers with new addresses. ADSC is NOT GATED by CE. Synchronous Address Status from Processor. ADSP is an active LOW input that is used to load the address registers with new addresses. ADSP is gated by CE. Synchronous Address Advance. ADV is an active LOW input that is used to advance the internal burst counter, co ntrolling burst access after the initial address is loaded. When this input is HIGH the burst counter is not incremented; that is, there is no address advance. Synchronous byte write enable gates the byte write inputs BW1-BW4. If BWE is LOW at the rising edge of CLK then BWX inputs are passed to the next stage in the circuit. A byte write can still be blocked if ADSP is LOW at the rising edge of CLK. If ADSP is HIGH and BWX is LOW at the rising edge of CLK then data will be written to the SRAM. If BWE is HIGH then the byte write inputs are blocked and only GW can initiate a write cycle. Synchronous byte write enables. BW1 controls I/O(7:0), BW2 controls I/O(15:8), etc. Any active byte write causes all outputs to be disabled. ADSP LOW disables all byte writes. BW1-BW4 must meet specified setup and hold times with respect to CLK. Synchronous chip enable. CE is used with CS0 and CS1 to enable the IDT71V432. CE also gates ADSP. This is the clock input to the IDT71V432. All timing references for the device are made with respect to this input. Synchronous active HIGH chip select. CS0 is used with CE and CS1 to enable the chip. Synchronous active LOW chip select. CS1 is used with CE and CS0 to enable the chip. Synchrono us global write enable. This input will write all four 8-bit data bytes when LOW on the rising edge of CLK. GW supercedes individual byte write enables. Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered and triggered by the rising edge of CLK. Asynchronous burst order sele ction DC input. When LBO is HIGH the Interleaved (Intel) burst sequence is selected. When LBO is LOW the Linear (PowerPC) burst sequence is selected. LBO is a static DC input and must not change state while the device is operating. Asynchronous output enable. When OE is LOW the data output drivers are enabled on the I/O pins. OE is gated internally by a d elay circuit driven by CE, CS0, and CS1. In dual-bank mode, when the user is utilizing two banks of IDT71V432 and toggling back and forth between them using CE, the internal de lay circuit delays the OE activation of the data output drivers by one cycle to prevent bus contention between the banks. When used in single bank mode CE, CS0, and CS1 are all tied active and there is no output enable delay. When OE is HIGH the I/O pins are in a high-impedence state. 3.3V power supply inputs. Ground pins. Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V432 to its lowest power consumption level. Data retention is guaranteed in Sleep Mode.
3104 tbl 02
ADSP ADV
I I
LOW LOW
BWE
Byte Write Enable
I
LOW
BW1 - BW4
Individual Byte Write Enables
I
LOW
CE CLK CS0 CS1
Chip Enable Clock Chip Select 0 Chip Select 1
I I I I
LOW N/A HIGH LOW
GW
Global Write Enable
I
LOW
I/O0-I/O31 LBO
Data Input/Output Linear Burst Order
I/O I
N/A LOW
OE
Output Enable
I
LOW
VDD VSS ZZ
Power Supply Ground Sleep Mode
N/A N/A I
N/A N/A HIGH
NOTE: 1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42 2
IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Functional Block Diagram
LBO ADV
CE Burst Sequence INTERNAL ADDRESS
CLK ADSC ADSP
CLK EN ADDRESS REGISTER Byte 1 Write Register
Binary Counter CLR
2
Burst Logic
15 A0* A1*
32K x 32 BIT MEMORY ARRAY
.
32
A0, A1
2
A2-A14 32
A0-A14 GW BWE BW1
15
15
Byte 1 Write Driver
Byte 2 Write Register
8
Byte 2 Write Driver
BW2
Byte 3 Write Register
8
Byte 3 Write Driver
BW3
Byte 4 Write Register
8
Byte 4 Write Driver
BW4
8
OUTPUT REGISTER
CE CS0 CS1
D
Q Enable Register
CLK EN
DATA INPUT REGISTER
ZZ
Powerdown
D
Q Enable Delay Register
OUTPUT BUFFER
OE
32
I/O0-I/O31
3104 drw 01
6.42 3
IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings(1)
Symbol VTERM VTERM TA TBIAS TSTG PT IOUT
(2)
Rating Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature Power Dissipation DC Output Current
Value -0.5 to +4.6 -0.5 to VDD+0.5 0 to +70 -55 to +125 -55 to +125 1.0 50
Unit V V
o o o
Recommended Operating Temperature and Supply Voltage
Grade Commercial Industrial Temperature 0C to +70C -40C to +85C VSS 0V 0V VDD 3.3V+10/-5% 3.3V+10/-5%
3104 tbl 03
(3)
C C C
W mA
3104 tbl 05
Recommended DC Operating Conditions
Symbol Parameter VDD VSS VIH VIH VIL Supply Voltage Ground Input High Voltage -- Inputs Input High Voltage -- I/O Input Low Voltage Min. 3.135 0 2.0 2.0 -0.5
(1)
Typ. 3.3 0 -- -- --
Max. 3.63 0 4.6
(2)
Unit V V V V V
3104 tbl 04
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDD and Input terminals only. 3. I/O terminals.
VDD+0.3 0.8
NOTES: 1. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle. 2. VIH (max) = 6.0V for pulse width less than tCYC/2, once per cycle.
Capacitance
Symbol CIN CI/O
(TA = +25C, f = 1.0MHz, TQFP package)
Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 3dV VOUT = 3dV Max. 6 7 Unit pF pF
3104 tbl 06
NOTE: 1. This parameter is guaranteed by device characterization, but not production tested.
6.42 4
IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration
A6 A7 CE CS0 BW4 BW3 BW2 BW1 CS1 VDD VSS CLK GW BWE OE ADSC ADSP ADV A8 A9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC I/O16 I/O17 VDD VSS I/O18 I/O19 I/O20 I/O21 VSS VDD I/O22 I/O23 VDD/NC(1) VDD NC VSS I/O24 I/O25 VDD VSS I/O26 I/O27 I/O28 I/O29 VSS VDD I/O30 I/O31 NC
80 79 78 77 76 75 74 73 72 71 70 69 68 67
PK100-1
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
NC I/O15 I/O14 VDD VSS I/O13 I/O12 I/O11 I/O10 VSS VDD I/O9 I/O8 VSS NC VDD ZZ(2) I/O7 I/O6 VDD VSS I/O5 I/O4 I/O3 I/O2 VSS VDD I/O1 I/O0 NC
LBO A5 A4 A3 A2 A1 A0 NC NC VSS VDD
NC NC A10 A11 A12 A13 A14 NC NC
3104 drw 02
Top View TQFP
NOTES: 1. Pin 14 can either be directly connected to VDD or not connected. 2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42 5
IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Synchronous Truth Table(1,2)
Operation Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst
NOTES: 1. L = VIL, H = VIH, X = Don't Care. 2. ZZ = LOW for this table. 3. OE is an asynchronous input.
Address Used None None None None None External External External External External External External Next Next Next Next Next Next Next Next Next Next Next Next Current Current Current Current Current Current Current Current Current Current Current Current
CE H L L L L L L L L L L L X X X X H H H H X X H H X X X X H H H H X X H H
CS0 X X L X L H H H H H H H X X X X X X X X X X X X X X X X X X X X X X X X
CS1 X H X H X L L L L L L L X X X X X X X X X X X X X X X X X X X X X X X X
ADSP X L L X X L L H H H H H H H H H X X X X H H X X H H H H X X X X H H X X
ADSC L X X L L X X L L L L L H H H H H H H H H H H H H H H H H H H H H H H H
ADV X X X X X X X X X X X X L L L L L L L L L L L L H H H H H H H H H H H H
GW X X X X X X X H H H H L H H H H H H H H H L H L H H H H H H H H H L H L
BWE X X X X X X X H L L L X H H X X H H X X L X L X H H X X H H X X L X L X
BWX X X X X X X X X H H L X X X H H X X H H L X L X X X H H X X H H L X L X
OE (3) X X X X X L H L L H X X L H L H L H L H X X X X L H L H L H L H X X X X
CLK
I/O Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z DOUT Hi-Z DOUT DOUT Hi-Z DIN DIN DOUT Hi-Z DOUT Hi-Z DOUT Hi-Z DOUT Hi-Z DIN DIN DIN DIN DOUT Hi-Z DOUT Hi-Z DOUT Hi-Z DOUT Hi-Z DIN DIN DIN DIN
3104 tbl 07
6.42 6
IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Synchronous Write Function Truth Table(1)
Operation Read Read Write all Bytes Write all Bytes Write Byte 1 Write Byte 2 Write Byte 3
(2) (2) (2)
GW H H L H H H H H
BWE H L X L L L L L
BW1 X H X L L H H H
BW2 X H X L H L H H
BW3 X H X L H H L H
BW4 X H X L H H H L
3104 tbl 08
Write Byte 4(2)
NOTES: 1. L = VIL, H = VIH, X = Don't Care. 2. Multiple bytes may be selected during the same cycle.
Asynchronous Truth Table(1)
Operation(2) Read Read Write Deselected Sleep OE L H X X X ZZ L L L L H I/O Status Data Out (I/O0 - I/O31) High-Z High-Z -- Data In (I/O0 - I/O31) High-Z High-Z Power Active Active Active Standby Sleep
3104 tbl 09
NOTES: 1. L = VIL, H = VIH, X = Don't Care. 2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
Interleaved Burst Sequence Table (LBO=VDD)
Sequence 1 A1 First Address Second Address Third Address Fourth Address
(1)
Sequence 2 A1 0 0 1 1 A0 1 0 1 0
Sequence 3 A1 1 1 0 0 A0 0 1 0 1
Sequence 4 A1 1 1 0 0 A0 1 0 1 0
3104 tbl 10
A0 0 1 0 1
0 0 1 1
NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Linear Burst Sequence Table (LBO=VSS)
Sequence 1 A1 First Address Second Address Third Address Fourth Address
(1)
Sequence 2 A1 0 1 1 0 A0 1 0 1 0
Sequence 3 A1 1 1 0 0 A0 0 1 0 1
Sequence 4 A1 1 0 0 1 A0 1 0 1 0
3104 tbl 11
A0 0 1 0 1
0 0 1 1
NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state.
6.42 7
IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 3.3V +10/-5%, Commercial and Industrial Temperature Ranges)
Symbol |ILI| |ILI| |ILO| VOL VOH Parameter Input Leakage Current ZZ and LBO Input Leakage Current Output Leakage Current Output Low Voltage (I/O1-I/O31) Output High Voltage (I/O1-I/O31)
(1)
Test Conditions VDD = Max., VIN = 0V to VDD VDD = Max., VIN = 0V to VDD CE > VIH or OE > VIH, VOUT = 0V to VDD, VDD = Max. IOL = 5mA, VDD = Min. IOH = -5mA, VDD = Min.
Min. -- -- -- -- 2.4
Max. 5 30 5 0.4 --
Unit A A A V V
3104 tbl 12
NOTE: 1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven.
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) (VDD = 3.3V +10/-5%, VHD = VDD0.2V, VLD = 0.2V)
IDT71V432S5 Symbol IDD ISB ISB1 IZZ Parameter Operating Power Supply Current Standby Power Supply Current Full Standby Power Supply Current Test Conditions Device Selected, Outputs Open, VDD = Max., VIN > VIH or < VIL, f = fMAX(2) Device Deselected, Outputs Open, VDD = Max., VIN > VIH or < VIL, f = fMAX(2) Device Deselected, Outputs Open, VDD = Max., VIN > VHD or < VLD, f = 0(2) Com'l. 200 65 15 10 Ind. 200 65 15 10 IDT71V432S6 Com'l. 180 60 15 10 Ind. 180 60 15 10 IDT71V432S7 Com'l. 160 55 15 10 Ind. 160 55 15 10 Unit mA mA mA mA
3104 tbl 13
Full Sleep Mode Power Supply Current ZZ > VHD, VDD = Max.
NOTES: 1. All values are maximum guaranteed values. 2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.
AC Test Loads
+1.5V 50 I/O Z0 = 50
+3.3V 317 I/O 351
3104 drw 03
5pF*
Figure 1. AC Test Load
6 5 4 3 tCD (Typical, ns) 2 1 20 30 50 80 100 Capacitance (pF) 200
3104 drw 05
* Including scope and jig capacitance.
3104 drw 04
Figure 2. AC Test Load
(for tOHZ, tCHZ, tOLZ, and tDC1)
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Timing Reference Levels AC Test Load 0 to 3.0V 2ns 1.5V 1.5V See Figures 1 and 2
3104 tbl 14
Figure 3. Lumped Capacitive Load, Typical Derating 6.42 8
IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V +10/-5%, Commercial and Industrial Temperature Ranges)
71V432S5 Symbol CLOCK PARAMETERS tCYC tCH
(1)
71V432S6 Min. Max.
71V432S7 Min. Max. Unit
Parameter
Min.
Max.
Clock Cycle Time Clock High Pulse Width Clock Low Pulse Width
10 4 4
____ ____ ____
12 4.5 4.5
____ ____ ____
15 5 5
____ ____ ____
ns ns ns
tCL(1)
OUTPUT PARAMETERS tCD tCDC tCLZ
(2)
Clock High to Valid Data Clock High to Data Change Clock High to Output Active Clock High to Data High-Z Output Enable Access Time
(2) (2)
____
5
____ ____
____
6
____ ____
____
7
____ ____
ns ns ns ns ns ns ns
1.5 0 1.5
____
2 0 2
____
2 0 2
____
tCHZ(2) tOE tOLZ
5 5
____
5 5
____
6 6
____
Output Enable Low to Data Active Output Enable High to Data High-Z
0
____
0
____
0
____
tOHZ
4
5
6
SETUP TIMES tSA tSS tSD tSW tSAV tSC HOLD TIMES tHA tHS tHD tHW tHAV tHC Address Hold Time Address Status Hold Time Data In Hold Time Write Hold Time Address Advance Hold Time Chip Enable/Select Hold Time 0.5 0.5 0.5 0.5 0.5 0.5
____ ____ ____ ____ ____ ____
Address Setup Time Address Status Setup Time Data in Setup Time Write Setup Time Address Advance Setup Time Chip Enable/Select Setup Time
2.5 2.5 2.5 2.5 2.5 2.5
____ ____ ____ ____ ____ ____
2.5 2.5 2.5 2.5 2.5 2.5
____ ____ ____ ____ ____ ____
2.5 2.5 2.5 2.5 2.5 2.5
____ ____ ____ ____ ____ ____
ns ns ns ns ns ns
0.5 0.5 0.5 0.5 0.5 0.5
____ ____ ____ ____ ____ ____
0.5 0.5 0.5 0.5 0.5 0.5
____ ____ ____ ____ ____ ____
ns ns ns ns ns ns
SLEEP MODE AND CONFIGURATION PARAMETERS tZZPW tZZR(3) tCFG
(4)
ZZ Pulse Width ZZ Recovery Time Configuration Set-up Time
100 100 40
-- -- --
100 100 50
____ ____ ____
100 100 50
____ ____ ____
ns ns ns
3104 tbl 15
NOTES: 1. Measured as HIGH above 2.0V and LOW below 0.8V. 2. Transition is measured 200mV from steady-state. 3. Device must be deselected when powered-up from sleep mode. 4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
6.42 9
tCYC
CLK tCH tCL
tSS tHS
ADSP
(1)
ADSC tHA Ax tSW tHW Ay
tSA
ADDRESS
GW, BWE, BWx tHC tSAV tHAV
tSC
CE, CS1
(Note 3)
ADV tOE tCD tOHZ tCDC
O1(Ay) O2(Ay) O3(Ay)
ADV inserts a wait-state
IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Timing Waveform of Pipelined Read Cycle(1,2)
6.42 10
tOLZ tCLZ
O1(Ax)
OE
(Burst wraps around to its initial state)
tCHZ
O4(Ay) O1(Ay) O2(Ay)
DATAOUT
Output Disabled Pipelined Read
Burst Pipelined Read
3104 drw 06
Commercial and Industrial Temperature Ranges
NOTES: 1. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. 2. ZZ input is LOW and LBO is Don't Care for this cycle. 3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
tCYC
CLK tCH
(2)
tSS tHS tCL
ADSP
tSA tHA Ax Ay tSW tHW Az
ADDRESS
GW
ADV
IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Timing Waveform of Combined Pipelined Read and Write Cycles(1,2,3)
6.42 11
OE tSD tHD tOE tCD tCLZ O1(Ax) tOHZ I1(Ay) tOLZ
DATAIN
tCDC O1(Az) O2(Az) O3(Az)
DATAOUT
Single Read
Pipelined Write
Pipelined Burst Read
3104 drw 07
Commercial and Industrial Temperature Ranges
NOTES: 1. Device is selected through entire cycle; CE and CS1 are LOW, CS0 is HIGH. 2. ZZ input is LOW and LBO is Don't Care for this cycle. 3. O1(Ax) represents the first output from the external address Ax. I1 (Ay) represents the first input from the external address Ay. O1(Az) represents the first output from the external addresss Az; O2(Az) represents the next output data in the burst sequence of the base address Az, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
tCYC
CLK tCH tCL
tSS tHS
ADSP
ADSC
tSA tHA Ax
BWE is ignored when ADSP initiates burst
ADDRESS Ay Az
tHW tSW
GW
tSC
tHC
CE, CS1 tSAV tHAV
(Note 3)
ADV
(ADV suspends burst)
IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Timing Waveform of Write Cycle No. 1 GW Controlled(1,2,3)
6.42 12
I1(Ax) I2(Ay) tOHZ O4(Aw) I1(Ay) I2(Ay) Burst Write Single Write
OE tSD I3(Ay) I4(Ay) I1(Az)
tHD
DATAIN
I2(Az)
I3(Az)
DATAOUT
O3(Aw)
Burst Read
Burst Write
3104 drw 08
Commercial and Industrial Temperature Ranges
NOTES: 1. ZZ input is LOW, BWE is HIGH, and LBO is Don't Care for this cycle. 2. O4(Aw) represents the final output data in the burst sequence of the base address Aw. I1(Ax) represents the first input from the external address Ax. I1(Ay) represents the first input from the external address Ay; I2(Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. In the case of input I2(Ay) this data is valid for two cycles because ADV is high and has suspended the burst. 3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
.
tCYC
CLK tCH tCL
tSS tHS
ADSP
ADSC
tSA tHA Ax
BWE is ignored when ADSP initiates burst
ADDRESS Az tHW tSW
Ay
BWE
BWx is ignored when ADSP initiates burst
tHW tSW
BWx
tSC
tHC
CE, CS1 tSAV
(Note 3)
IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Timing Waveform of Write Cycle No. 2 Byte Controlled(1,2,3)
6.42 13
(ADV suspends burst)
ADV
OE tSD I1(Ax) I2(Ay) tOHZ I1(Ay) I2(Ay) I3(Ay) I4(Ay) I1(Az)
tHD
DATAIN
I2(Az)
I3(Az)
DATAOUT Single Write
O3(Aw)
O4(Aw) Burst Write Extended Burst Write
3104 drw 09
Burst Read
Commercial and Industrial Temperature Ranges
NOTES: 1. ZZ input is LOW, GW is HIGH, and LBO is Don't Care for this cycle. 2. O4(Aw) represents the final output data in the burst sequence of the base address Aw. I1(Ax) represents the first input from the external address Ax. I1(Ay) represents the first input from the external address Ay; I2(Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. In the case of input I2(Ay) this data is valid for two cycles because ADV is high and has suspended the burst. 3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
tCYC
CLK tCH tCL
tSS
tHS
ADSP
ADSC tHA Ax Az
tSA
ADDRESS
GW tHC
tSC
CE, CS1
(Note 4)
IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Timing Waveform of Sleep (ZZ) and Power-Down Modes(1,2,3)
6.42 14
tOE tOLZ
O1(Ax)
ADV
OE
DATAOUT
tZZR tZZPW Single Read Snooze Mode
3104 drw 10
ZZ
Commercial and Industrial Temperature Ranges
NOTES: 1. Device must power up in deselected Mode. 2. LBO input is Don't Care for this cycle. 3. It is not necessary to retain the state of the input registers throughout the Power-down cycle. 4. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Non-Burst Read Cycle Timing Waveform(1,2,3,4)
CLK
ADSP or ADSC
ADDRESS
Av
Aw
Ax
Ay
Az
DATAOUT
(Av)
(Aw)
(Ax)
(Ay)
NOTES: 1. ZZ, CE, CS1, and OE are LOW for this cycle. 2. ADV, GW, BWE, BWx, and CS0 are HIGH for this cycle. 3. (Ax) represents the data for address Ax, etc. 4. For read cycles, ADSP and ADSC function identically and are therefore interchangeable.
3104 drw 11
Non-Burst Write Cycle Timing Waveform(1,2,3,4)
CLK
ADSP
ADSC
ADDRESS GW or BWE and BWx DATAIN
Av
Aw
Ax
Ay
Az
(Av)
(Aw)
(Ax)
(Ay)
(Az)
3104 drw 12
NOTES: 1. ZZ, CE and CS1 are LOW for this cycle. 2. ADV, OE and CS0 are HIGH for this cycle. 3. (AX) represents the data for address AX, etc. 4. For write cycles, ADSP and ADSC have different limitations.
6.42 15
IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
100-pin Thin Plastic Quad Flatpack (TQFP) Package Diagram Outline
6.42 16
IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Ordering Information
IDT 71V432 Device Type S Power X Speed PF Package X Process/ Temperature Range Blank I Commercial (0C to +70C) Industrial (-40C to +85C)
PF
Plastic Thin Quad Flatpack, 100 pin (PK100-1)
5 6 7
Speed in nanoseconds
PART NUMBER
71V432S5PF 71V432S6PF 71V432S7PF
SPEED IN MEGAHERTZ
100 MHz 83 MHz 66 MHz
tCD PARAMETER
5 ns 6 ns 7 ns
CLOCK CYCLE TIME
10 ns 12 ns 15 ns
3104 drw 13
6.42 17
IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Datasheet Document History
9/10/99 Pg. 3-5 Pg. 5 Pg. 11-14 Pg. 17 Pg. 1, 4, 8, 9, 16 Pg. 16 Updated to new format Adjusted page layout, added extra page Added notes to pin configuration Revised notes Added Datasheet Document History Added Industrial temperature range offerings Added 100pinTQFP package Diagram Outline Not recommended for new designs Removed "Not recommended for new designs" from the background on the datasheet
03/09/00 04/04/00 08/09/00 08/17/01
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
6.42 18
for Tech Support: sramhelp@idt.com 800-544-7726, x4033
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