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SN74CB3T3245 8-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE WITH 5-V-TOLERANT LEVEL SHIFTER
SCDS136 - OCTOBER 2003 - REVISED MARCH 2005
FEATURES
* * * Standard '245-Type Pinout Output Voltage Translation Tracks VCC Supports Mixed-Mode Signal Operation on All Data I/O Ports - 5-V Input Down to 3.3-V Output Level Shift With 3.3-V VCC - 5-V/3.3-V Input Down to 2.5-V Output Level Shift With 2.5-V VCC 5-V-Tolerant I/Os With Device Powered Up or Powered Down Bidirectional Data Flow With Near-Zero Propagation Delay Low ON-State Resistance (ron) Characteristics (ron = 5 Typ) Low Input/Output Capacitance Minimizes Loading (Cio(OFF) = 5 pF Typ) Data and Control Inputs Provide Undershoot Clamp Diodes Low Power Consumption (ICC = 40 A Max)
* * * * * *
* * * * * *
*
*
VCC Operating Range From 2.3 V to 3.6 V Data I/Os Support 0- to 5-V Signaling Levels (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V) Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Outputs Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Performance Tested Per JESD 22 - 2000-V Human-Body Model (A114-B, Class II) - 1000-V Charged-Device Model (C101) Supports Digital Applications: Level Translation, PCI Interface, USB Interface, Memory Interleaving, Bus Isolation Ideal for Low-Power Portable Equipment
DBQ, DGV, DW, OR PW PACKAGE (TOP VIEW)
NC A1 A2 A3 A4 A5 A6 A7 A8 GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC OE B1 B2 B3 B4 B5 B6 B7 B8
NC - No internal connection
DESCRIPTION/ORDERING INFORMATION
The SN74CB3T3245 is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O ports by providing voltage translation that tracks VCC. The SN74CB3T3245 supports systems using 5-V TTL, 3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels (see Figure 1).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2003-2005, Texas Instruments Incorporated
SN74CB3T3245 8-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE WITH 5-V-TOLERANT LEVEL SHIFTER
SCDS136 - OCTOBER 2003 - REVISED MARCH 2005
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
VCC
5.5 V VCC 9VCC - 1 V IN OUT 9VCC 9VCC - 1 V
CB3T
0V
0V
Input Voltages
Output Voltages
NOTE A: If the input high-voltage (VIH) level is greater than or equal to (VCC - 1 V) and less than or equal to 5.5 V, then the output high-voltage (VOH) level will be equal to approximately the VCC voltage level.
Figure 1. Typical DC Voltage Translation Characteristics The SN74CB3T3245 is an 8-bit bus switch with a single ouput-enable (OE) input and a standard '245 pinout. When OE is low, the 8-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the 8-bit bus switch is OFF, and a high-impedance state exists between the A and B ports. This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION
TA SOIC - DW -40C to 85C SSOP (QSOP) - DBQ TSSOP - PW TVSOP - DGV (1) PACKAGE (1) Tube Tape and reel Tape and reel Tube Tape and reel Tape and reel ORDERABLE PART NUMBER SN74CB3T3245DW SN74CB3T3245DWR SN74CB3T3245DBQR SN74CB3T3245PW SN74CB3T3245PWR SN74CB3T3245DGVR TOP-SIDE MARKING CB3T3245 CB3T3245 KS245 KS245
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
INPUT OE L H INPUT/OUTPUT A B Z FUNCTION A port = B port Disconnect
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SN74CB3T3245 8-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE WITH 5-V-TOLERANT LEVEL SHIFTER
SCDS136 - OCTOBER 2003 - REVISED MARCH 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
2 A1 9 SW SW 11 18 B1
A8
B8
19 OE
SIMPLIFIED SCHEMATIC, EACH FET SWITCH (SW)
A VG(1) Control Circuit
B
EN(2)
1) Gate Voltage (VG) is approximately equal to VCC + VT when the switch is ON and VI > (VCC + VT). 2) EN is the internal enable signal applied to the switch.
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SN74CB3T3245 8-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE WITH 5-V-TOLERANT LEVEL SHIFTER
SCDS136 - OCTOBER 2003 - REVISED MARCH 2005
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Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN VCC VIN VI/O IIK II/OK II/O Supply voltage range (2) Control input voltage range (2) (3) Switch I/O voltage range (2) (3) (4) VIN < 0 VI/O < 0 Control input clamp current I/O port clamp current ON-state switch current (5) DBQ package JA Package thermal impedance (6) DGV package DW package PW package Tstg (1) (2) (3) (4) (5) (6) Storage temperature range -65 Continuous current through VCC or GND -0.5 -0.5 -0.5 MAX 7 7 7 -50 -50 128 100 68 92 58 83 150 C C/W UNIT V V V mA mA mA mA
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to ground unless otherwise specified. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. VI and VO are used to denote specific conditions for VI/O. II and IO are used to denote specific conditions for II/O. The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions (1)
MIN VCC VIH VIL VI/O TA (1) Supply voltage High-level control input voltage Low-level control input voltage Data input/output voltage Operating free-air temperature VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V 2.3 1.7 2 0 0 0 -40 MAX 3.6 5.5 5.5 0.7 0.8 5.5 85 UNIT V V V V C
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SN74CB3T3245 8-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE WITH 5-V-TOLERANT LEVEL SHIFTER
SCDS136 - OCTOBER 2003 - REVISED MARCH 2005 (1)
Electrical Characteristics
PARAMETER VIK VOH IIN II IOZ (3) Ioff ICC ICC (4) Cin Cio(OFF) Cio(ON) Control inputs Control inputs Control inputs
over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS VCC = 3 V, II = -18 mA See Figure 3 and Figure 4 VCC = 3.6 V, VIN = 3.6 V to 5.5 V or GND VI = VCC - 0.7 V to 5.5 V VCC = 3.6 V, Switch ON, VIN = VCC or GND VI = 0.7 V to VCC - 0.7 V VI = 0 to 0.7 V VCC = 3.6 V, VO = 0 to 5.5 V, VI = 0, Switch OFF, VIN = VCC or GND VCC = 0, VO = 0 to 5.5 V, VI = 0, VCC = 3.6 V, II/O = 0, Switch ON or OFF, VIN = VCC or GND VCC = 3.3 V, VIN = VCC or GND VCC = 3.3 V, VI/O = 5.5 V, 3.3 V, or GND, Switch OFF, VIN = VCC or GND VCC = 3.3 V, Switch ON, VIN = VCC or GND VCC = 2.3 V, TYP at VCC = 2.5 V, VI = 0 ron (5) VCC = 3 V, VI = 0 (1) (2) (3) (4) (5) VI/O = 5.5 V or 3.3 V VI/O = GND IO = 24 mA IO = 16 mA IO = 64 mA IO = 32 mA VI = VCC or GND VI = 5.5 V 4 5 5 13 5 5 5 5 8.5 8.5 7 7 10 20 -40 5 10 10 40 40 300 A A A A pF pF pF A A MIN TYP (2) MAX -1.2 UNIT V
VCC = 3 V to 3.6 V, One input at VCC - 0.6 V, Other inputs at VCC or GND
VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins. All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25C. For I/O ports, the parameter IOZ includes the input leakage current. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. Measured by the voltage drop between A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals.
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
PARAMETER tpd (1) ten tdis (1) FROM (INPUT) A or B OE OE TO (OUTPUT) B or A A or B A or B 1 1 VCC = 2.5 V 0.2 V MIN MAX 0.15 10.5 5.5 1 1 VCC = 3.3 V 0.3 V MIN MAX 0.25 8 7.5 ns ns ns UNIT
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
5
SN74CB3T3245 8-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE WITH 5-V-TOLERANT LEVEL SHIFTER
SCDS136 - OCTOBER 2003 - REVISED MARCH 2005
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PARAMETER MEASUREMENT INFORMATION
VCC Input Generator VIN 50 VG1 50 DUT Input Generator 50 VG2 2 x VCC VI 50 VO CL (see Note A) RL RL S1 Open GND
TEST CIRCUIT
TEST tpd(s) tPLZ/tPZL
VCC 2.5 V 0.2 V 3.3 V 0.3 V 2.5 V 0.2 V 3.3 V 0.3 V 2.5 V 0.2 V 3.3 V 0.3 V
S1 Open Open 2 x VCC 2 x VCC Open Open
RL 500 500 500 500 500 500
VI 3.6 V or GND 5.5 V or GND GND GND 3.6 V 5.5 V Output Control (VIN) tPZL
CL 30 pF 50 pF 30 pF 50 pF 30 pF 50 pF
V
0.15 V 0.3 V 0.15 V 0.3 V VCC
tPHZ/tPZH
VCC/2
VCC/2 0V tPLZ VCC
Output Control (VIN) tPLH Output
VCC VCC/2 VCC/2 0V tPHL VOH VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (tpd(s)) VCC/2 VOL
Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH Output Waveform 2 S1 at Open (see Note B)
VCC/2
VOL + V VOL tPHZ VOH VOH - V 0V
VCC/2
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). H. All parameters and waveforms are not applicable to all devices.
Figure 2. Test Circuit and Voltage Waveforms
6
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SN74CB3T3245 8-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE WITH 5-V-TOLERANT LEVEL SHIFTER
SCDS136 - OCTOBER 2003 - REVISED MARCH 2005
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE vs INPUT VOLTAGE
4.0 VCC = 2.3 V IO = 1 A TA = 25C 4.0 VCC = 3 V IO = 1 A TA = 25C
OUTPUT VOLTAGE vs INPUT VOLTAGE
V - Output Voltage - V O
3.0
V - Output Voltage - V O 2.0 3.0 4.0 5.0 6.0
3.0
2.0
2.0
1.0
1.0
0.0 0.0 1.0 VI - Input Voltage - V
0.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 VI - Input Voltage - V
Figure 3. Data Output Voltage vs Data Input Voltage
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SN74CB3T3245 8-BIT FET BUS SWITCH 2.5-V/3.3-V LOW-VOLTAGE WITH 5-V-TOLERANT LEVEL SHIFTER
SCDS136 - OCTOBER 2003 - REVISED MARCH 2005
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TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE
4.0 VOH - Output Voltage High - V 3.5 4.0 100 A 8 mA 16 mA 24 mA VOH - Output Voltage High - V VCC = 2.3 V to 3.6 V VI = 5.5 V TA = 85C VCC = 2.3 V to 3.6 V VI = 5.5 V TA = 25C 100 A 8 mA 16 mA 24 mA
OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE
3.5
3.0
3.0
2.5 2.0 1.5 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 VCC - Supply Voltage - V 100 A 8 mA 16 mA 24 mA 4.0 VOH - Output Voltage High - V VCC = 2.3 V to 3.6 V VI = 5.5 V TA = -40C
2.5
2.0
1.5 2.3
2.5
2.7 2.9 3.1 3.3 VCC - Supply Voltage - V
3.5
3.7
OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE
100 A 8 mA 16 mA 24 mA
3.5
3.0
2.5
2.0
1.5 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 VCC - Supply Voltage - V
Figure 4. VOH Values
8
PACKAGE OPTION ADDENDUM
www.ti.com
5-Sep-2005
PACKAGING INFORMATION
Orderable Device 74CB3T3245DBQRE4 74CB3T3245DGVRE4 SN74CB3T3245DBQR SN74CB3T3245DGVR SN74CB3T3245DW SN74CB3T3245DWE4 SN74CB3T3245DWR SN74CB3T3245DWRE4 SN74CB3T3245PW SN74CB3T3245PWE4 SN74CB3T3245PWR SN74CB3T3245PWRE4
(1)
Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type SSOP/ QSOP TVSOP SSOP/ QSOP TVSOP SOIC SOIC SOIC SOIC TSSOP TSSOP TSSOP TSSOP
Package Drawing DBQ DGV DBQ DGV DW DW DW DW PW PW PW PW
Pins Package Eco Plan (2) Qty 20 20 20 20 20 20 20 20 20 20 20 20 2500 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 25 25 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU
MSL Peak Temp (3) Level-2-260C-1YEAR Level-1-260C-UNLIM Level-2-260C-1YEAR Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM
2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 70 70 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br)
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS006C - FEBRUARY 1996 - REVISED AUGUST 2000
DGV (R-PDSO-G**)
24 PINS SHOWN 0,23 0,13 13
PLASTIC SMALL-OUTLINE
0,40 24
0,07 M
0,16 NOM 4,50 4,30 6,60 6,20
Gage Plane
0,25 0- 8 1 A 12 0,75 0,50
Seating Plane 1,20 MAX 0,15 0,05 0,08
PINS ** DIM A MAX A MIN
14 3,70 3,50
16 3,70 3,50
20 5,10 4,90
24 5,10 4,90
38 7,90 7,70
48 9,80 9,60
56 11,40 11,20
4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins - MO-153 14/16/20/56 Pins - MO-194
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C - JANUARY 1995 - REVISED FEBRUARY 1999
PW (R-PDSO-G**)
14 PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,65 14 8
0,30 0,19
0,10 M
0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0- 8 0,75 0,50
Seating Plane 1,20 MAX 0,15 0,05 0,10
PINS ** DIM A MAX
8
14
16
20
24
28
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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