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MPC17C724 Rev 2.0, 12/2005
0.4 A Dual H-Bridge Motor Driver IC
The 17C724 is a compact monolithic dual channel H-Bridge power IC, ideal for portable electronic applications containing bipolar stepper motors or brush DC motors such as those used in camera lenses and shutters. The 17C724 can operate efficiently with supply voltages from 2.7 V to 5.5 V and can provide continuous motor drive currents of 0.4 A with low RDS(ON) of 1.0 . It is easily interfaced to low-cost MCUs via parallel 3.0 V- or 5.0 V-compatible logic and has built-in shootthrough current protection circuit and undervoltage detector to avoid malfunction. The 17C724 has four output control modes: Forward, Reverse, Brake, and Tri-State (High Impedance). The H-bridge outputs are designed to be independently PWM'ed at up to 200 kHz for speed/ torque and current control. Features * Manufactured in SMOS7 Process Technology * Built-In 2-Channel H-Bridge Driver * Provides 4 Driving Modes (Forward, Reverse, Break, High Impedance) * Direct Interface to MCU * Low ON-Resistance, RDS(ON) = 1.0 (Typical) * Dual Channel Parallel Drive, RDS(ON) = 0.5 (Typical) * * * * * * *
17C724
MOTOR DRIVER
EP (Pb-FREE) SUFFIX SCALE 4:1 98ARL10566D 16-Terminal QFN
ORDERING INFORMATION
Device MPC17C724EP/R2 Temperature Range (TA) -20C to 85C Package 16 QFN
Output Current Driver (IDR) is 400 mA (Continuous) Low Power Consumption Built-In Shoot-Through Current Prevention Circuit Built-In Low-Voltage Shutdown Circuit PWM Control Frequency 200 kHz (Max) Very Compact Size, Comes in 16-Terminal QFN Package (3 x 3 mm Terminal Pitch: 0.5 mm) Pb-Free Packaging Designated by Suffix Code EP
3.0 V 17C724 VDD VM OUT1A OUT1B IN1A MCU IN1B IN2A IN2B PSAVE GND OUT2A OUT2B Bipolar Step Motor
S
N
Figure 1. 17C724 Simplified Application Diagram
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2005. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VDD
PSAVELowVoltage Shutdown
VM1
IN1A H-Bridge 1 IN1B VDD PSAVE Control Logic Level Shifter Predriver
OUT1A OUT1B
PGND1 VM2
IN2A H-Bridge 2 IN2B OUT2A OUT2B
LGND
PGND2 PGND2
Figure 2. 17C724 Simplified Internal Block Diagram
17C724
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Analog Integrated Circuit Device Data Freescale Semiconductor
TERMINAL CONNECTIONS
TERMINAL CONNECTIONS
Transparent Top View of Package
PGND1 VDD LGND
14
16
15
PSAVE
13 12 11 10 9
1N1A 1N1B OUT1A VM1
1
IN2A IN2B OUT1B VM2
2 3
4 5 6 7
8
OUT2A
PGND2
Figure 3. 17C724 Terminal Connections Table 1. 17C724 Terminal Definitions A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 8.
Terminal Number 1 2 3 4 5 6, 7 8 9 10 11 12 13 14 15 16 Terminal Name IN1A IN1B OUT1A VM1 OUT2A PGND2 OUT2B VM2 OUT1B IN2B IN2A PSAVE LGND PGND1 VDD Terminal Function Logic Logic Output Power Output Ground Output Power Output Input Input Input Ground Ground Logic Formal Name Definition
Logic Input Control 1A Logic input control of OUT1A (refer to Table 5, Truth Table, page 7). Logic Input Control 1B Logic input control of OUT1B (refer to Table 5, Truth Table, page 7). H-Bridge Output 1A Motor Driver Power Supply 1 H-Bridge Output 2A Power Ground 2 H-Bridge Output 2B Motor Driver Power Supply 2 H-Bridge Output 1B Output A of H-Bridge channel 1. Positive power source connection for H-Bridge 1 (Motor Driver Power Supply) (1). Output A of H-Bridge channel 2. High-current power ground 2 (2). Output B of H-Bridge channel 2. Positive power source connection for H-Bridge 2 (Motor Driver Power Supply) (1). Output B of H-Bridge channel 1.
Logic Input Control 2B Logic input control of OUT2B (refer to Table 5, Truth Table, page 7). Logic Input Control 2A Logic input control of OUT2A (refer to Table 5, Truth Table, page 7). Input Enable Control Logic Ground Power Ground 1 Logic Circuit Power Supply Logic input enable control of H-Bridges to save power. Low-current logic signal ground (2). High-current power ground 1 (2). Positive power source connection for logic circuit.
Notes 1. VM1 and VM2 are internally connected. 2. LGND, PGND1, and PGND2 are internally connected.
PGND2
OUT2B
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MAXIMUM RATINGS
MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings ELECTRICAL RATINGS Power Supply Voltage (Motor Driver) Normal Operation (Steady-State) Transient Conditions (3) Logic Supply Voltage Input Terminal Voltage Driver Output Current (Continuous) (4) Driver Output Current (Peak) (5) ESD Voltage (6) Human Body Model Machine Model TEMPERATURE RATINGS Storage Temperature Operating Temperature Ambient Operating Junction Temperature Thermal Resistance (Junction-to-Ambient) Single-Layer PCB Mounting (8) Multi-Layer PCB (2S2P) Mounting Terminal Soldering Temperature (7) Notes 3. 4. 5. 6. 7. 8. 9.
(9)
Symbol
Value
Unit
V V M(SS) V M(PK) V DD V IN IO I OPK V ESD1 V ESD2 - 0.3 to 6.0 - 0.3 to 6.5 6.0 - 0.3 to VDD + 0.3 400 800 V V mA mA
2000 200
V
T STG TA TJ R JA R JMA T SOLDER
- 40 to 150 - 20 to 85 150 maximum 169 47 260
C C C C/W
C
Transient condition within 500 ms. Continuous output current must not be exceeded and at operating junction temperature below 150C. Peak time is for 10 ms pulse width at 200 ms intervals. ESD testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), and the Machine Model (CZAP = 200 pF, RZAP = 0 ). Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. For cases using SEMI G38-87, JEDEC JESD51-2, JESD51-3, JESD51-5, single layer PCB mounting without thermal vias. For cases using SEMI JEDEC JESD51-6, JESD51-5, JESD51-7, 2S2P PCB mounting with 4 thermal vias.
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STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics noted under conditions TA = 25C, VDD = VM = 3.0V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic POWER INPUT (VDD, PSAVE) Supply Voltage Range Motor Driver Supply Voltage Logic Supply Voltage Standby Power Supply Current (10) VM = 3.0 V VDD = 3.0 V Operating Power Supply Current (11) VDD = 3.0 V Logic Input Function High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current PSAVE Terminal Low Level Input Current Driver Output ON Resistance (13) Low-Voltage Shutdown Detection Voltage (14)
(12)
Symbol
Min
Typ
Max
Unit
V VM V DD I I VMSTBY 2.7 2.7 - - 3.0 3.0 - - 5.5 5.5 1.0 1.0 A - V IH V IL I. IH I IL I IL R DS(ON) V DDDET V DD 0.7 - - - 1.0 - - 1.5 40 - - - - - 30 1.0 2.0 100 - V DD 0.3 1.0 - - 60 1.5 2.5 V V A A A V A
VDDSTBY IC
Notes 10. Power SAVE mode. 11. IC is the sum of the current of V DD monitor block "Low Voltage Detection Module" and the PSAVE pull-up resistor at f IN = 200 kHz. 12. 13. 14. VDD = 3.0 V. IO = 375 mA. R DS(ON) = RSOURCE + RSINK. RL = 6.8 . Detection voltage is defined as when the output becomes high impedance after VDD voltage falls and when VM = 5.5 V.
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Analog Integrated Circuit Device Data Freescale Semiconductor
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DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions TA = 25C, VDD = VM = 3.0V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic INPUT Pulse Input Frequency Input Pulse Rise Time (15) Input Pulse Fall Time (17) OUTPUT Output Propagation Delay Time (18) Turn-ON Time Turn-OFF Time Low-Voltage Detection Time Notes 15. 16. 17. 18. t PLH t PHL - - - 0.2 0.1 0.02 0.5 0.5 1.0 ms s f IN tR tF - - - - - - 200 1.0
(16)
Symbol
Min
Typ
Max
Unit
kHz s s
1.0
(16)
tV
DDDET
Time is defined between 10% and 90%. That is, the input waveform slope must be steeper than this. Time is defined between 90% and 10%. RL = 6.8 . Slew time, rise time, and fall times are between 10% and 90% of output low and high levels with respect to the 50% level of the input.
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Analog Integrated Circuit Device Data Freescale Semiconductor
TIMING DIAGRAMS
TIMING DIAGRAMS
IN1, IN2, PSAVE
VDDDETon 50% VDD 1.0 V
2.5 V 50%
VDDDEToff
tPLH
OUTA, OUTB 90% 10%
tPHL
t
VDDDET 90%
t
VDDDET 0% (<1.0 A)
IM
Figure 4. tPLH and tPHL Timing Table 5. Truth Table
INPUT PSAVE(19) L L L L H H : High L : Low Z : High impedance X : Don't care IN1A IN2A L H L H X IN1B IN2B L L H H X
Figure 5. Low-Voltage Detection Timing
OUTPUT OUT1A OUT2A L H L Z Z OUT1B OUT2B L L H Z Z V DDDET(20) Enabled Enabled Enabled Enabled Disabled
Notes 19. Terminal 13 (PSAVE) is pulled up by an internal resistor. 20. When VDD is lower than VDDDET while VM is applied, output becomes "Z" (high impedance); however, when PSAVE = "H", the low-voltage shutdown detection circuit is disabled.
17C724
Analog Integrated Circuit Device Data Freescale Semiconductor
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FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 17C724 is a monolithic dual H-Bridge that is ideal in portable electronic applications to control bipolar step motors and brush DC motors such as those used in camera lens and shutters. The 17C724 can operate efficiently with supply voltages as low as 2.7 V to as high as 5.5 V, and provide continuous motor drive currents of 0.4 A while handling peak currents up to 0.8 A. It is easily interfaced to low-cost MCUs via parallel 3.0 V- or 5.0 V-compatible logic. The device can be pulse width modulated (PWM'ed) at up to 200 kHz. The 17C724 can drive two motors simultaneously (see Figure 6), or it can drive one bipolar step motor as shown in the simplified application diagram on page 1. Dual channel parallel drive is also possible if higher current drive is desired (0.8 A). Two-motor operation is accomplished by hooking one motor between OUT1A and OUT1B, and the other motor between OUT2A and OUT2B. This IC has a built-in shoot-through current protection circuit and undervoltage detector to avoid malfunction. It also allows for power-conserving Sleep mode by the setting of the PSAVE terminal (refer to Table 5, Truth Table, page 7). The device features four operating modes: Forward, Reverse, Brake, and Tri-Stated (High Impedance).
FUNCTIONAL TERMINAL DESCRIPTION LOGIC CIRCUIT POWER SUPPLY (VDD)
The VDD terminal carries the power source connection to the control (logic) circuit, and its input range is between 2.7 V to 5.5 V (3.0 V and 5.0 V compatible). VDD has an undervoltage threshold. If the supply voltage to VDD drops below 2.0 V (typical), then all the output of H-Bridges (OUT1A, OUT1B, OUT2A, OUT2B) will become open (high impedance = Z). When the supply voltage returns to a level that is above the threshold voltage the H-Bridge outputs automatically resume normal operation according to the established condition of the input terminals. this mode, the built-in low-voltage detection circuit is disabled.
H-BRIDGE OUTPUT (OUT1A, OUT1B, OUT2A, AND OUT2B)
These terminals are the outputs of the power MOSFET H-Bridges. OUT1 is from H-Bridge Channel 1, and OUT2 from H-Bridge Channel 2. These terminals will typically connect to an external load (step motor or brush DC motors).
MOTOR DRIVER POWER SUPPLY (VM1 AND VM2)
VM1 and VM2 carries the main supply voltage and current into the power sections (the H-Bridges) of the IC. Both of these terminals are connected internally but they must be connected together on the printed circuit board with as short as possible traces. The input range is 2.7 V to 5.5 V.
LOGIC INPUT CONTROL (IN1A, IN1B, IN2A, AND IN2B)
These logic input terminals control each H-Bridge output. For example, IN1A logic HIGH = OUT1A HIGH; likewise, IN1B logic HIGH = OUT1B HIGH. If both A and B inputs are HIGH, then both A and B outputs are Z (refer to Table 5, Truth Table, page 7).
POWER GROUND (PGND1 AND PGND2)
These two are the power ground terminals that connect to the power ground of the H-Bridges. The power grounds are for higher current handling capability from loads and they must be connected together on the PCB.
INPUT ENABLE CONTROL (PSAVE)
The PSAVE input controls the functioning of the power output stages (the H-Bridges). When it is set logic LOW, the output stages are enabled and the H-Bridges function normally. When it is set logic HIGH, the output stages are disabled and all the outputs are opened (high impedance). In
LOGIC GROUND (LGND)
LGND is the logic ground terminal and its current handling level is lower than the PGND.
17C724
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Analog Integrated Circuit Device Data Freescale Semiconductor
TYPICAL APPLICATIONS FUNCTIONAL TERMINAL DESCRIPTION
TYPICAL APPLICATIONS
Figure 6 shows a typical application for the 17C724. 3.0 V 17C724 VDD VM
OUT1A
OUT1B
MCU
IN1A IN1B IN2A IN2B
PSAVE
OUT2A
OUT2B
GND
Figure 6. 17C724 Typical Application Diagram
CEMF SNUBBING TECHNIQUES
Care must be taken to protect the IC from potentially damaging CEMF spikes induced when commutating currents in inductive loads. Typical practice is to provide snubbing of voltage transients by placing a zener or capacitor at the supply terminal (VM) (see Figure 7).
3.0 V 3.0 V 17C724 VDD VM OUT 3.0 V 3.0 V 17C724 VDD VM OUT
PCB LAYOUT
When designing the printed circuit board (PCB), connect sufficient capacitance between power supply and ground terminals to ensure proper filtering from transients. For all high-current paths, use wide copper traces and shortest possible distance.
APPLICATION NOTES
Although VM1 and VM2 are connected internally, they must be connected externally to attain sufficient power distribution. Take precautions to guard against electrostatic discharge when handling the device, especially when mounting and demounting the device to a PCB.
OUT OUT
OUT OUT
OUT GND
OUT GND
Figure 7. CEMF Snubbing Techniques
17C724
Analog Integrated Circuit Device Data Freescale Semiconductor
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PACKAGING PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the "98A" listed below. EP (Pb-FREE) SUFFIX 16-TERMINAL QFN NON-LEADED PACKAGE 98ARL10566D ISSUE A
17C724
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Analog Integrated Circuit Device Data Freescale Semiconductor
PACKAGING PACKAGE DIMENSIONS
EP (Pb-FREE) SUFFIX 16-TERMINAL QFN NON-LEADED PACKAGE 98ARL10566D ISSUE A
17C724
Analog Integrated Circuit Device Data Freescale Semiconductor
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REVISION HISTORY
REVISION HISTORY
REVISION 2.0
DATE 2005
DESCRIPTION OF CHANGES * Initial Release
17C724
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Analog Integrated Circuit Device Data Freescale Semiconductor
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MPC17C724 Rev 2.0 12/2005

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