View M28C64C_216418.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M28C64C M28C64X
64 Kbit (8Kb x8) Parallel EEPROM
FAST ACCESS TIME: 150ns SINGLE 5V 10% SUPPLY VOLTAGE LOW POWER CONSUMPTION FAST WRITE CYCLE - 32 Bytes Page Write Operation - Byte or Page Write Cycle: 5ms ENHANCED END OF WRITE DETECTION - Ready/Busy Open Drain Output (for M28C64C product only) - Data Polling - Toggle Bit PAGE LOAD TIMER STATUS BIT HIGH RELIABILITY SINGLE POLYSILICON, CMOS TECHNOLOGY - Endurance >100,000 Erase/Write Cycles - Data Retention >40 Years JEDEC APPROVED BYTEWIDE PIN OUT DESCRIPTION The M28C64C is an 8 Kbit x8 low power Parallel EEPROM fabricated with STMicroelectronics proprietary single polysilicon CMOS technology. The device offers fast access time with low power dissipation and requires a 5V power supply. The circuit has been designed to offer a flexible microcontroller interface featuring both hardware and software handshakingmode with Ready/Busy, Data Polling and Toggle Bit. The M28C64C supports 32 byte page write operation. Table 1. Signal Names
A0 - A12 DQ0 - DQ7 W E G RB VCC VSS Address Input Data Input / Output Write Enable Chip Enable Output Enable Ready / Busy Supply Voltage Ground
28
1
PDIP28 (P)
PLCC32 (K)
28
1
SO28 (MS) 300 mils
TSOP28 (N) 8 x13.4mm
Figure 1. Logic Diagram
VCC
13 A0-A12
8 DQ0-DQ7
W E
M28C64C RB
G
VSS
AI00746B
February 1999
1/15
M28C64C, M28C64X
Figure 2A. DIP Pin Connections Figure 2B. LCC Pin Connections
AI00747C
DQ1 DQ2 VSS DU DQ3 DQ4 DQ5
AI00748D
RB A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 28 2 27 3 26 4 25 5 24 6 23 7 22 M28C64C 8 21 9 20 10 19 11 18 12 17 13 16 14 15
VCC W DU A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
A6 A5 A4 A3 A2 A1 A0 NC DQ0
RB DU VCC W DU 1 32 A8 A9 A11 NC G A10 E DQ7 DQ6 25 17 21 15 14 8
AI01016D
9
Warning: DU = Don't Use.
Warning: NC = Not Connected, DU = Don't Use.
Figure 2C. SO Pin Connections
Figure 2D. TSOP Pin Connections
RB A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 2 3 4 5 6 7 M28C64C 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC W DU A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
G A11 A9 A8 DU W VCC RB A12 A7 A6 A5 A4 A3
22
A7 A12
M28C64C
28 1
M28C64C
7
A10 E DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2
AI00876C
Warning: DU = Don't Use.
Warning: DU = Don't Use.
PIN DESCRITPION Addresses (A0-A12). The address inputs select an 8-bit memory location during a read or write operation.
Chip Enable (E). The chip enable input must be low to enable all read/write operations. When Chip Enable is high, power consumption is reduced. Output Enable (G). The Output Enable input controls the data output buffers and is used to initiate read operations.
2/15
M28C64C, M28C64X
Table 2. Absolute Maximum Ratings
Symbol TA T STG VCC V IO VI VESD Parameter Ambient Operating Temperature Storage Temperature Range Supply Voltage Input/Output Voltage Input Voltage Electrostatic Discharge Voltage (Human Body model) Value - 40 to 125 - 65 to 150 - 0.3 to 6.5 - 0.3 to VCC +0.6 - 0.3 to 6.5 2000 Unit C C V V V V
Note: Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Table 3. Operating Modes
Mode Read Write Standby / Write Inhibit Write Inhibit Write Inhibit Output Disable
Note: X = VIH or VIL
E VIL VIL VIH X X X
G VIL VIH X X VIL VIH
W VIH VIL X VIH X X
DQ0 - DQ7 Data Out Data In Hi-Z Data Out or Hi-Z Data Out or Hi-Z Hi-Z
Data In/ Out (DQ0 - DQ7). Data is written to or read from the M28C64C through the I/O pins. Write Enable (W). The Write Enable input controls the writing of data to the M28C64C. Ready/Busy (RB). Ready/Busy is an open drain output that can be used to detect the end of the internal write cycle. OPERATION In order to prevent data corruption and inadvertent write operations during power-up, a Power On Reset (POR) circuit resets all internal programming cicuitry. Access to the memory in write mode is allowed after a power-up as specified in Table 6. Read The M28C64C is accessed like a static RAM. When E and G are low with W high, the data addressed is presented on the I/O pins. The I/O pins are high impedancewhen either G or E is high.
Write Write operations are initiated when both W and E are low and G is high.The M28C64C supports both E and W controlled write cycles. The Address is latched by the falling edge of E or W which ever occurs last and the Data on the rising edge of E or W which ever occurs first. Once initiated the write operation is internally timed until completion. Page Write Page write allows up to 32 bytes to be consecutively latched into the memory prior to initiating a programming cycle. All bytes must be located in a single page address, that is A5 - A12 must be the same for all bytes. The page write can be initiated during any byte write operation. Following the first byte write instruction the host may send another address and data up to a maximum of 100s after the rising edge of E or W which ever occurs first (t BLC). If a transition of E or W is not detected within 100s, the internal programming cycle will start.
3/15
M28C64C, M28C64X
Figure 3. Block Diagram
RB E G W
VPP GEN
RESET
ATD & CONTROL LOGIC
X DECODE
A5-A12 (Page Address)
ADDRESS LATCH
64K ARRAY
A0-A4
ADDRESS LATCH
Y DECODE
SENSE AND DATA LATCH
I/O BUFFERS
PAGE LOAD TIMER STATUS TOGGLE BIT DATA POLLING
AI00877C
DQ0-DQ7
Microcontroller Control Interface The M28C64C provides two write operation status bits and one status pin that can be used to minimize the system write cycle. These signals are available on the I/O port bits DQ7 or DQ6 of the memory during programming cycle only, or as the RB signal on a separate pin. Figure 4. Status Bit Assignment
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 DP TB PLTS Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
DP = Data Polling TB = Toggle Bit PLTS = Page Load Timer Status
Data Polling bit (DQ7). During the internal write cycle, any attempt to read the last byte written will produce on DQ7 the complementary value of the previously latched bit. Once the write cycle is finished the true logic value appears on DQ7 in the read cycle.
4/15
Toggle bit (DQ6). The M28C64C offers another way for determining when the internal write cycle is completed. Duringthe internal Erase/Write cycle, DQ6 will toggle from "0" to "1" and "1" to "0" (the first read value is "0") on subsequent attempts to read any address in the memory. When the internal cycle is completed the toggling will stop and the device will be accessible for a new Read or Write operation. Page Load Timer Status bit (DQ5). In the Page Write mode data may be latched by E or W up to 100s after the previous byte. Up to 32 bytes may be input. The Data output (DQ5) indicates the status of the internal Page Load Timer. DQ5 may be read by asserting Output Enable Low (tPLTS). DQ5 Low indicates the timer is running, High indicates time-out after which the write cycle will start and no new data may be input. Ready/Busy pin. The RB pin provides a signal at its open drain output which is low during the erase/write cycle, but which is released at the completion of the programming cycle.
M28C64C, M28C64X
Table 4. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 20ns 0.4V to 2.4V 0.8V to 2.0V
1N914
Figure 6. AC Testing Equivalent Load Circuit
1.3V
Note that Output Hi-Z is defined as the point where data is no longer driven.
3.3k
Figure 5. AC Testing Input Output Waveforms
2.4V
DEVICE UNDER TEST CL = 30pF
OUT
2.0V 0.8V
AI00826
0.4V
CL includes JIG capacitance
AI01129
Table 5. Capacitance (1) (TA = 25 C, f = 1 MHz )
Symbol CIN C OUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF
Note: 1. Sampled only, not 100% tested.
Table 6. Read Mode DC Characteristics (TA = 0 to 70C or -40 to 85C, VCC = 4.5V to 5.5V)
Symbol ILI ILO ICC ICC1 ICC2
(1) (1) (1)
Parameter Input Leakage Current Output Leakage Current Supply Current (TTL and CMOS inputs) Supply Current (Standby) TTL Supply Current (Standby) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
Test Condition 0V VIN VCC 0V VIN VCC E = VIL, G = VIL , f = 5 MHz E = VIH E > VCC -0.3V
Min
Max 10 10 30 2 100
Unit A A mA mA A V V V V
VIL VIH VOL VOH
- 0.3 2 IOL = 2.1 mA IOH = -400 A 2.4
0.8 VCC +0.5 0.4
Note: 1. All I/O's open circuit.
Table 7. Power Up Timing (1) (TA = 0 to 70C or -40 to 85C, VCC = 4.5V to 5.5V)
Symbol tPUR tPUW Parameter Time Delay to Read Operation Time Delay to Write Operation Min 1 10 Max Unit s ms
Note: 1. Sampled only, not 100% tested.
5/15
M28C64C, M28C64X
Table 8. Read Mode AC Characteristics (TA = 0 to 70C or -40 to 85C, VCC = 4.5V to 5.5V)
M28C64C Symbol Alt Parameter Test Condition -150 min tAVQV tELQV tGLQV tEHQZ (1) tGHQZ (1) tAXQX tACC tCE tOE tDF tDF tOH Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition E = VIL, G = VIL G = VIL E = VIL G = VIL E = VIL E = VIL, G = VIL 0 0 0 max 150 150 75 50 50 0 0 0 -200 min max 200 200 100 60 60 0 0 0 -250 min max 250 250 110 65 65 ns ns ns ns ns ns Unit
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.
Figure 7. Read Mode AC Waveforms
A0-A12 tAVQV E tGLQV G tELQV DQ0-DQ7
VALID tAXQX
tEHQZ
tGHQZ DATA OUT Hi-Z
AI00749B
Note: Write Enable (W) = High
6/15
M28C64C, M28C64X
Table 9. Write Mode AC Characteristics (TA = 0 to 70C or -40 to 85C, VCC = 4.5V to 5.5V)
Symbol tAVWL tAVEL tELWL tGHWL tGHEL tWLEL tWLAX tELAX tWLDV tELDV tWLWH tELEH tWHEH tWHGL tEHGL tEHWH tWHDX tEHDX tWHWL tWHWH tWHRH tWHRL tEHRL tDVWH tDVEH Alt tAS tAS tCES tOES tOES tWES tAH tAH tDV tDV tWP tWP tCEH tOEH tOEH tWEH tDH tDH tWPH tBLC tWC tDB tDB tDS tDS Parameter Address Valid to Write Enable Low Address Valid to Chip Enable Low Chip Enable Low to Write Enable Low Output Enable High to Write Enable Low Output Enable High to Chip Enable Low Write Enable Low to Chip Enable Low Write Enable Low to Address Transition Chip Enable Low to Address Transition Write Enable Low to Input Valid Chip Enable Low to Input Valid Write Enable Low to Write Enable High Chip Enable Low to Chip Enable High Write Enable High to Chip Enable High Write Enable High to Output Enable Low Chip Enable High to Output Enable Low Chip Enable High to Write Enable High Write Enable High to Input Transition Chip Enable High to Input Transition Write Enable High to Write Enable Low Byte Load Repeat Cycle Time Write Cycle Time Write Enable High to Ready/Busy Low Chip Enable High to Ready/Busy Low Data Valid before Write Enable High Data Valid before Chip Enable High Note 1 Note 1 50 50 E = VIL, G = VIH G = VIH, W = VIL 150 150 0 10 10 0 0 0 200 0.35 50 5 220 220 Test Condition E = VIL, G = VIH G = VIH, W = VIL G = VIH E = VIL W = VIL G = VIH Min 0 0 0 0 0 0 150 150 1 1 Max Unit ns ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns s ms ns ns ns ns
Note: 1. With a 3.3 k external pull-up resistor.
7/15
M28C64C, M28C64X
Figure 8. Write Mode AC Waveforms - Write Enable Controlled
A0-A12 tAVWL E tELWL G tGHWL W
VALID tWLAX
tWHEH
tWLWH
tWHGL
tWLDV DQ0-DQ7 DATA IN tDVWH RB
tWHWL
tWHDX
tWHRL
AI00750
Figure 9. Write Mode AC Waveforms - Chip Enable Controlled
A0-A12 tAVEL E tGHEL G tWLEL W
VALID tELAX
tELEH
tEHGL
tELDV DQ0-DQ7 DATA IN tDVEH RB tEHDX
tEHWH
tEHRL
AI00751
8/15
M28C64C, M28C64X
Figure 10. Page Write Mode AC Waveforms - Write Enable Controlled
A0-A12
Addr 0
Addr 1
Addr 2
Addr n
E tPLTS G tWHWL W tWLWH DQ0-DQ7 Byte 0 Byte 1 tWHWH Byte 2 tWHWH Byte n tWHRH
DQ5 tWHRL RB
Byte n
AI00752C
Figure 11. Data Polling Waveform Sequence
A0-A12
Address of the last byte of the Page Write instruction
E
G
W
DQ7 DQ7 DQ7 DQ7 DQ7 DQ7
LAST WRITE
INTERNAL WRITE SEQUENCE
READY
AI00753C
9/15
M28C64C, M28C64X
Figure 12. Toggle Bit Waveform Sequence
A0-A12
E
G
W
DQ6
(1)
LAST WRITE
TOGGLE INTERNAL WRITE SEQUENCE
READY
AI00754D
Note: 1. First Toggle bit is forced to '0'
ORDERING INFORMATION SCHEME
Example:
M28C64C
-150
K
1
Version C RB available X RB not bonded (pin NC) -150 -200 -250
Speed 150 ns 200 ns 250 ns P K
Package PDIP28 PLCC32
Temperature Range 1 6 0 to 70 C -40 to 85 C
MS SO28 300 mils N TSOP28 8 x 13.4mm
For a listof availableoptions (Speed, Package,etc... ) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
10/15
M28C64C, M28C64X
PDIP28 - 28 pin Plastic DIP, 600 mils width
Symb Typ A A1 A2 B B1 C D D2 E E1 e1 eA eB L S N 2.54 14.99 15.24 3.18 1.78 0 28 17.78 3.43 2.08 10 33.02 15.24 13.59 13.84 0.100 0.590 0.600 0.125 0.070 0 28 0.700 0.135 0.082 10 1.52 0.20 36.83 0.30 37.34 1.300 0.600 0.535 0.545 0.38 3.56 0.38 4.06 0.51 0.060 0.008 1.450 0.012 1.470 mm Min Max 5.08 0.015 0.140 0.015 0.160 0.020 Typ inches Min Max 0.200
A2 A1 B1 B D2 D S
N
A L eA eB C
e1
E1
1
E
PDIP
Drawing is not to scale.
11/15
M28C64C, M28C64X
PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular
Symb Typ A A1 A2 B B1 D D1 D2 E E1 E2 e F R N Nd Ne CP 0.89 1.27 mm Min 2.54 1.52 - 0.33 0.66 12.32 11.35 9.91 14.86 13.89 12.45 - 0.00 - 32 7 9 0.10 Max 3.56 2.41 0.38 0.53 0.81 12.57 11.56 10.92 15.11 14.10 13.46 - 0.25 - 0.035 0.050 Typ inches Min 0.100 0.060 - 0.013 0.026 0.485 0.447 0.390 0.585 0.547 0.490 - 0.000 - 32 7 9 0.004 Max 0.140 0.095 0.015 0.021 0.032 0.495 0.455 0.430 0.595 0.555 0.530 - 0.010 -
D D1
1N
A1 A2
B1
Ne
E1 E
F 0.51 (.020)
D2/E2 B
e
1.14 (.045)
Nd
A R CP
PLCC
Drawing is not to scale.
12/15
M28C64C, M28C64X
SO28 - 28 lead Plastic Small Outline, 300 mils body width
Symb Typ A A1 A2 B C D E e H L N CP 1.27 mm Min 2.46 0.13 2.29 0.35 0.23 17.81 7.42 - 10.16 0.61 0 28 0.10 Max 2.64 0.29 2.39 0.48 0.32 18.06 7.59 - 10.41 1.02 8 0.050 Typ inches Min 0.097 0.005 0.090 0.014 0.009 0.701 0.292 - 0.400 0.024 0 28 0.004 Max 0.104 0.011 0.094 0.019 0.013 0.711 0.299 - 0.410 0.040 8
A2 B e D
A C CP
N
E
1
H A1 L
SO-b
Drawing is not to scale.
13/15
M28C64C, M28C64X
TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4mm
Symb Typ A A1 A2 B C D D1 E e L N CP 0.55 0.95 0.17 0.10 13.20 11.70 7.90 - 0.50 0 28 0.10 mm Min Max 1.25 0.20 1.15 0.27 0.21 13.60 11.90 8.10 - 0.70 5 0.022 0.037 0.007 0.004 0.520 0.461 0.311 - 0.020 0 28 0.004 Typ inches Min Max 0.049 0.008 0.045 0.011 0.008 0.535 0.469 0.319 - 0.028 5
A2
22 21
e
28 1
E B
7 8
D1 D
A CP
DIE
C
TSOP-c
Drawing is not to scale.
A1
L
14/15
M28C64C, M28C64X
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Spec ifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com
15/15

▲Up To Search▲

Price & Availability of M28C64C

	To Download M28C64C Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .