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PD - 95526
IRF1104S/LPbF
l l l l l l l l
Advanced Process Technology Ultra Low On-Resistance Surface Mount (IRF1104S) Low-profile through-hole (IRF1104L) 175C Operating Temperature Fast Switching Fully Avalanche Rated Lead-Free
HEXFET(R) Power MOSFET
D
VDSS = 40V RDS(on) = 0.009
G
ID = 100A
S
Description
Absolute Maximum Ratings
ID @ TC = 25C ID @ TC = 100C IDM PD @TA = 25C PD @TC = 25C VGS EAS IAR EAR dv/dt TJ TSTG
Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The D2Pak is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible on-resistance in any existing surface mount package. The D2Pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application. The through-hole version (IRF1104L) is available for lowprofile applications.
D 2 Pak
TO-262
Parameter
Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds
Max.
100 71 400 2.4 170 1.1 20 350 60 17 5.0 -55 to + 175 300 (1.6mm from case )
Units
A W W W/C V mJ A mJ V/ns C
Thermal Resistance
Parameter
RJC RJA Junction-to-Case Junction-to-Ambient(PCB Mounted,steady-state)**
Typ.
--- ---
Max.
0.9 62
Units
C/W
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7/20/04
IRF1104S/LPbF
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
Parameter Min. Drain-to-Source Breakdown Voltage 40 V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient --- RDS(on) Static Drain-to-Source On-Resistance --- VGS(th) Gate Threshold Voltage 2.0 gfs Forward Transconductance 37 --- IDSS Drain-to-Source Leakage Current --- Gate-to-Source Forward Leakage --- IGSS Gate-to-Source Reverse Leakage --- Qg Total Gate Charge --- Qgs Gate-to-Source Charge --- Qgd Gate-to-Drain ("Miller") Charge --- td(on) Turn-On Delay Time --- tr Rise Time --- td(off) Turn-Off Delay Time --- tf Fall Time --- V(BR)DSS LS Ciss Coss Crss Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance --- --- --- --- Typ. --- 0.038 --- --- --- --- --- --- --- --- --- --- 15 114 28 19 7.5 2900 1100 250 Max. Units Conditions --- V VGS = 0V, ID = 250A --- V/C Reference to 25C, ID = 1mA 0.009 VGS = 10V, ID = 60A 4.0 V VDS = VGS, ID = 250A --- S VDS = 30V, ID = 60A 25 VDS = 40V, VGS = 0V A 250 VDS = 32V, VGS = 0V, TJ = 150C 100 VGS = 20V nA -100 VGS = -20V 93 ID = 60A 29 nC VDS = 32V 30 VGS = 10V, See Fig. 6 and 13 --- VDD = 20V --- ID = 60A ns --- RG = 3.6 --- RD = 0.33, See Fig. 10 Between lead, --- nH and center of die contact --- VGS = 0V --- pF VDS = 25V --- = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
IS
I SM
VSD trr Q rr ton Notes:
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time
Min. Typ. Max. Units
Conditions D MOSFET symbol --- --- 100 showing the A G integral reverse --- --- 400 p-n junction diode. S --- --- 1.3 V TJ = 25C, IS =60A, VGS = 0V --- 74 110 ns TJ = 25C, IF =60A --- 188 280 nC di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 ) Starting TJ = 25C, L = 194H RG = 25, IAS = 60A. (See Figure 12)
Pulse width 300s; duty cycle 2%. Uses IRF1104 data and test conditions. Calculated continuous current based on maximum allowable
ISD 60A, di/dt 304A/s, VDD V(BR)DSS,
junction temperature;for recommended current-handling of the package refer to Design Tip # 93-4 TJ 175C ** When mounted on 1" square PCB ( FR-4 or G-10 Material ). For recommended footprint and soldering techniques refer to application note #AN-994.
2
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IRF1104S/LPbF
1000
I D , Drain-to-Source Current (A)
100
I D , Drain-to-Source Current (A)
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
1000
100
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
4.5V
10
10
4.5V
20s PULSE WIDTH TJ = 25 C
1 10 100
1 0.1
1 0.1
20s PULSE WIDTH TJ = 175 C
1 10 100
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
2.5
RDS(on) , Drain-to-Source On Resistance (Normalized)
ID = 100A
I D , Drain-to-Source Current (A)
100
TJ = 175 C
2.0
1.5
10
TJ = 25 C
1
1.0
0.5
0.1 4.0
V DS = 50V 20s PULSE WIDTH 5.0 6.0 7.0 8.0 9.0 10.0
0.0 -60 -40 -20 0
VGS = 10V
20 40 60 80 100 120 140 160 180
VGS , Gate-to-Source Voltage (V)
TJ , Junction Temperature ( C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
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IRF1104S/LPbF
5000
4000
VGS , Gate-to-Source Voltage (V)
VGS = 0V, f = 1MHz Ciss = Cgs + Cgd , Cds SHORTED Crss = Cgd Coss = Cds + Cgd
20
ID = 60A
VDS = 32V VDS = 20V
C, Capacitance (pF)
15
3000
Ciss
10
2000
Coss
1000
5
Crss
0 1 10 100
0 0 25 50
FOR TEST CIRCUIT SEE FIGURE 13
75 100
VDS , Drain-to-Source Voltage (V)
QG , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
1000
10000
ISD , Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED BY RDS(on)
TJ = 175 C
ID , Drain Current (A)
100
1000 10us 100us 1ms 10 10ms
10
100
1
TJ = 25 C
0.1 0.2
V GS = 0 V
0.8 1.4 2.0 2.6
1
TC = 25 C TJ = 175 C Single Pulse
1 10 100
VSD ,Source-to-Drain Voltage (V)
VDS , Drain-to-Source Voltage (V)
4
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
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IRF1104S/LPbF
100
LIMITED BY PACKAGE
80
V DS V GS RG 10V
Pulse Width 1 s Duty Factor 0.1 %
RD
D.U.T.
+
ID , Drain Current (A)
-V DD
60
40
Fig 10a. Switching Time Test Circuit
20
VDS 90%
0
25
50
TC , Case Temperature ( C)
75
100
125
150
175
Fig 9. Maximum Drain Current Vs. Case Temperature
10% VGS
td(on) tr t d(off) tf
Fig 10b. Switching Time Waveforms
1
Thermal Response (Z thJC )
D = 0.50
0.20 0.10 0.05 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) PDM t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.0001 0.001 0.01 0.1 1
0.1
0.01 0.00001
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRF1104S/LPbF
EAS , Single Pulse Avalanche Energy (mJ)
800
TOP
600
15V
BOTTOM
ID 24A 42A 60A
VDS
L
DRIVER
RG
20V
D.U.T
IAS tp
+ V - DD
400
A
0.01
200
Fig 12a. Unclamped Inductive Test Circuit
0
25
50
75
100
125
150
175
V(BR)DSS tp
Starting TJ , Junction Temperature ( C)
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
I AS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator Same Type as D.U.T.
50K
QG
12V
.2F .3F
10 V
QGS
QGD
VGS
3mA
D.U.T.
+ V - DS
VG
Charge
IG
ID
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
Fig 13b. Gate Charge Test Circuit
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IRF1104S/LPbF
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
-
+
RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
+ V DD
Driver Gate Drive P.W. Period D=
P.W. Period VGS=10V
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
VDD
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS
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IRF1104S/LPbF
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information (Lead-Free)
T H IS IS AN IR F 5 3 0 S W IT H L O T CO D E 8 0 2 4 AS S E M B L E D O N W W 0 2 , 2 0 0 0 IN T H E AS S E M B L Y L IN E "L " N ote: "P " in as s em bly lin e po s i tion in dicates "L ead-F r ee" IN T E R N AT IO N AL R E CT IF IE R L O GO AS S E M B L Y L O T CO D E P AR T N U M B E R F 53 0 S D AT E CO D E Y E AR 0 = 2 0 0 0 W E E K 02 L IN E L
OR
IN T E R N AT IO N AL R E C T IF IE R L O GO AS S E M B L Y L OT COD E P AR T N U M B E R F 530S D AT E CO D E P = D E S IG N AT E S L E AD -F R E E P R O D U C T (O P T IO N AL ) Y E AR 0 = 2 0 0 0 W E E K 02 A = AS S E M B L Y S IT E CO D E
8
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IRF1104S/LPbF TO-262 Package Outline
IGBT 1- GATE 2- COLLECTOR 3- EMITTER
TO-262 Part Marking Information
EXAMPLE: T HIS IS AN IRL3103L LOT CODE 1789 AS SEMBLED ON WW 19, 1997 IN T HE ASS EMBLY LINE "C" Note: "P" in as s embly line pos ition indicates "Lead-Free" INT ERNAT IONAL RECT IFIER LOGO ASS EMBLY LOT CODE PART NUMBER
DAT E CODE YEAR 7 = 1997 WEEK 19 LINE C
OR
INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER DAT E CODE P = DES IGNAT ES LEAD-FREE PRODUCT (OPTIONAL) YEAR 7 = 1997 WEEK 19 A = AS S EMBLY S ITE CODE
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IRF1104S/LPbF
D2Pak Tape & Reel Infomation
TRR
1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153)
1.60 (.063) 1.50 (.059)
0.368 (.0145) 0.342 (.0135)
FEED DIRECTION 1.85 (.073)
1.65 (.065)
11.60 (.457) 11.40 (.449)
15.42 (.609) 15.22 (.601)
24.30 (.957) 23.90 (.941)
TRL
10.90 (.429) 10.70 (.421) 1.75 (.069) 1.25 (.049) 16.10 (.634) 15.90 (.626) 4.72 (.136) 4.52 (.178)
FEED DIRECTION
13.50 (.532) 12.80 (.504)
27.40 (1.079) 23.90 (.941)
4
330.00 (14.173) MAX.
60.00 (2.362) MIN.
NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039) 24.40 (.961) 3
30.40 (1.197) MAX. 4
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.07/04
10
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