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Micrel
3.3V, 125Mbps 155Mbps CLOCK and DATA RECOVERY
SY69753L
SY69753L
FEATURES
s Industrial temperature range (-40C to +85C) s 3.3V power supply s SONET/SDH/ATM compatible s Clock and data recovery for 125Mbps/155Mbps NRZ data stream s Two on-chip PLLs: one for clock generation and another for clock recovery s Selectable reference frequencies s Differential PECL high-speed serial I/O s Line receiver input: no external buffering needed s Link fault indication s 100k ECL compatible I/O s Complies with Bellcore, ITU/CCITT and ANSI specifications for OC-3 applications s Available in 32-pin EPAD-TQFP
DESCRIPTION
The SY69753L is a complete Clock Recovery and Data Retiming integrated circuit for OC-3/STS-3 applications at 155Mbps NRZ. The device is ideally suited for SONET/ SDH/ATM applications and other high-speed data transmission systems. Clock recovery and data retiming is performed by synchronizing the on-chip VCO directly to the incoming data stream. The VCO center frequency is controlled by the reference clock frequency and the selected divide ratio. On-chip clock generation is performed through the use of a frequency multiplier PLL with a byte rate source as reference. The SY69753L also includes a link fault detection circuit. Data sheets and support documentation can be found on Micrel's web site at www.micrel.com.
APPLICATIONS
s Ethernet media converter s SONET/SDH/ATM OC-3 s Proprietary architectures at 135Mbps to 180Mbps
BLOCK DIAGRAM
PLLR P/N RDINP (PECL) RDINN RDOUTP (PECL)
PHASE DETECTOR
RDOUTN RCLKP (PECL) RCLKN
0 1 PHASE/ FREQUENCY DETECTOR
CHARGE PUMP
VCO
CD (PECL)
LINK FAULT DETECTION
LFIN (TTL)
REFCLK (TTL)
PHASE/ FREQUENCY DETECTOR
CHARGE PUMP
VCO
1 0
TCLKP (PECL) TCLKN VCC VCCA VCCO GND
DIVIDER BY 8, 10, 16, 20
DIVSEL 1/2 (TTL)
PLLS P/N
CLKSEL (TTL)
Rev.: B
Amendment: /2
1
Issue Date: September 2003
Micrel
SY69753L
PACKAGE/ORDERING INFORMATION
DIVSEL1
32 NC RDINP RDINN NC REFCLK NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Top View EPAD-TQFP H32-1
DIVSEL2
Ordering Information
Part Number
24 RDOUTP 23 RDOUTN 22 VCCO 21 RCLKP 20 RCLKN 19 VCCO 18 TCLKP 17 TCLKN
VCCA
VCCA
LFIN PLLSN
31 30 29 28 27 26 25
VCC
VCC PLLRN
CD
Package Type H32-1 H32-1
Operating Range Industrial Industrial
Package Marking SY69753LHI SY69753LHI
SY69753LHI SY69753LHI*
*Tape and Reel
PIN DESCRIPTIONS
INPUTS RDINP, RDINN [Serial Data Input] Differential PECL These built-in line receiver inputs are connected to the differential receive serial data stream. An internal receive PLL recovers the embedded clock (RCLK) and data (RDOUT) information. REFCLK [Reference Clock] TTL Input This input is used as the reference for the internal frequency synthesizer and the "training" frequency for the receiver PLL to keep it centered in the absence of data coming in on the RDIN inputs. CD [Carrier Detect] PECL Input This input controls the recovery function of the Receive PLL and can be driven by the carrier detect output of optical modules or from external transition detection circuitry. When this input is HIGH the input data stream (RDIN) is recovered normally by the Receive PLL. When this input is LOW the data on the inputs RDIN will be internally forced to a constant LOW, the data outputs RDOUT will remain LOW, the Link Fault Indicator output LFIN forced LOW and the clock recovery PLL forced to look onto the clock frequency generated from REFCLK. DIVSEL1, DIVSEL2 [Divider Select] TTL Inputs These inputs select the ratio between the output clock frequency (RCLK/TCLK) and the REFCLK input frequency as shown in the "Reference Frequency Selection" Table. CLKSEL [Clock Select] TTL Inputs This input is used to select either the recovered clock of the receiver PLL (CLKSEL = HIGH) or the clock of the frequency synthesizer (CLKSEL = LOW) to the TCLK outputs. OUTPUTS LFIN [Link Fault Indicator] TTL Output This output indicates the status of the input data stream RDIN. Active HIGH signal is indicating when the internal clock recovery PLL has locked onto the incoming data stream. LFIN will go HIGH if CD is HIGH and RDIN is within the frequency range of the Receive PLL (1000ppm). LFIN is an asynchronous output. RDOUTP, RDOUTN [Receive Data Output] Differential PECL These ECL 100K outputs represent the recovered data from the input data stream (RDIN). This recovered data is specified against the rising edge of RCLK. RCLKP, RCLKN [Clock Output] Differential PECL These ECL 100K outputs represent the recovered clock used to sample the recovered data (RDOUT). TCLKP, TCLKN [Clock Output] Differential PECL These ECL 100K outputs represent either the recovered clock (CLKSEL = HIGH) used to sample the recovered data (RDOUT) or the transmit clock of the frequency synthesizer (CLKSEL = LOW). PLLSP, PLLSN [Clock Synthesis PLL Loop Filter] External loop filter pins for the clock synthesis PLL. PLLRP, PLLRN [Clock Recovery PLL Loop Filter] External loop filter pins for the receiver PLL. POWER & GROUND VCC VCCA VCCO GND N/C Supply Voltage(1) Analog Supply Voltage(1) Output Supply Voltage(1) Ground No Connect
PLLSP
GNDA
GND
PLLRP
GND
CLKSEL
NOTE: 1. VCC, VCCA, VCCO must be the same value.
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Micrel
SY69753L
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) .................................. -0.5V to +5.0V Input Voltage (VIN) .......................................... -0.5V toVCC Output Current (IOUT) Continuous ......................................................... 50mA Surge ................................................................ 100mA Storage Temperature (TS) ....................... -65C to +150C
Operating Ratings(Note 2)
Supply Voltage (VCC) .............................. +3.15V to +3.45V Ambient Temperature (TA) ..................... -40C to +85C Junction Temperature (TJ) .................................. +125C Package Thermal Resistance, Note 3 EPAD-TQFP (JA) Still-Air ............................................................. 28C/W 500lfpm ............................................................ 20C/W EPAD-TQFP (JC) ................................................. 4C/W
DC ELECTRICAL CHARACTERISTICS
TA = -40C to +85C Symbol VCC ICC Parameter Power Supply Voltage Power Supply Current Condition Min 3.15 -- Typ 3.3 170 Max 3.45 230 Units V mA
PECL 100K DC ELECTRICAL CHARACTERISTICS
VCC = VCCO = VCCA = 3.3V 5%; TA = -40C to + 85C Symbol VIH VIL IIL VOH VOL Parameter Input HIGH Voltage Input LOW Voltage Input LOW Current Output HIGH Voltage Output LOW Voltage VIN = VIL(Min.) 50 to VCC -2V 50 to VCC -2V Condition Min VCC - 1.165 VCC - 1.810 0.5 VCC - 1.075 VCC - 1.860 Typ -- -- -- -- -- Max VCC - 0.880 VCC - 1.475 -- VCC - 0.830 VCC - 1.570 Units V V A V V
TTL DC ELECTRICAL CHARACTERISTICS
VCC = VCCO = VCCA = 3.3V 5%; TA = -40C to + 85C Symbol VIH VIL IIH IIL VOH VOL IOS
Note 1.
Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Output HIGH Voltage Output LOW Voltage Output Short Circuit Current
Condition
Min 2.0 --
Typ -- -- -- -- -- -- -- --
Max VCC 0.8 -- +100 -- -- 0.5 -100
Units V V A A A V V mA
VIN = 2.7V, VCC = Max. VIN = VCC, VCC = Max. VIN = 0.5V, VCC = Max. IOH = -0.4mA IOL = 4mA VOUT = 0V (maximum 1sec)
-125 -- -300 2.0 -- -15
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions for extended periods may affect device reliability. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. Numbers valid with proper thermal design of PCB and exposed pad soldered to island on PCB. Refer to Figure on page 9.
Note 2. Note 3.
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Micrel
SY69753L
AC ELECTRICAL CHARACTERISTICS
VCC = VCCO = VCCA = 3.3V 5%; TA = -40C to + 85C Symbol fVCO fVCO tACQ tCPWH tCPWL tDV tDH tir tODC trskew tr, tf Parameter VCO Center Frequency VCO Center Frequency Tolerance Acquisition Lock Time REFCLK Pulse Width HIGH REFCLK Pulse Width LOW Data Valid Data Hold REFCLK Input Rise Time Output Duty Cycle (RCLK/TCLK) Recovered Clock Skew ECL Output Rise/Fall Time (20% to 80%) 50 to VCC -2V Nominal Condition Min 800 -- -- 4 4
1/(2*fRCLK) - 200 1/(2*fRCLK) - 200
Typ -- 5 -- -- -- -- -- 0.5 -- -- --
Max 1100 -- 15 -- -- -- -- 2 55 +200 500
Units MHz % s ns ns ps ps ns % of UI ps ps
-- 45 -200 100
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Micrel
SY69753L
FUNCTIONAL DESCRIPTION AND CHARACTERISTICS
Clock Recovery Clock Recovery, as shown in the block diagram generates a clock that is at the same frequency as the incoming data bit rate at the Serial Data input. The clock is phase aligned by a PLL so that it samples the data in the center of the data eye pattern. The phase relationship between the edge transitions of the data and those of the generated clock are compared by a phase/frequency detector. Output pulses from the detector indicate the required direction of phase correction. These pulses are smoothed by an integral loop filter. The output of the loop filter controls the frequency of the Voltage Controlled Oscillator (VCO), which generates the recovered clock. Frequency stability without incoming data is guaranteed by an alternate reference input (REFCLK) that the PLL locks onto when data is lost. If the Frequency of the incoming signal varies by greater than approximately 1000ppm with respect to the synthesizer frequency, the PLL will be declared out of lock, and the PLL will lock to the reference clock. The loop filter transfer function is optimized to enable the PLL to track the jitter, yet tolerate the minimum transition density expected in a received SONET data signal. This transfer function yields a 30s data stream of continuous 1's or 0's for random incoming NRZ data. The total loop dynamics of the clock recovery PLL provides jitter tolerance which is better than the specified tolerance in GR-253-CORE. Lock Detect The SY69753L contains a link fault indication circuit which monitors the integrity of the serial data inputs. If the received serial data fails the frequency test, the PLL will be forced to lock to the local reference clock. This will maintain the correct frequency of the recovered clock output under loss of signal or loss of lock conditions. If the recovered clock frequency deviates from the local reference clock frequency by more than approximately 1000ppm, the PLL will be declared out of lock. The lock detect circuit will poll the input data stream in an attempt to reacquire lock to data. If the recovered clock frequency is determined to be within approximately 1000ppm, the PLL will be declared in lock and the lock detect output will go active. Performance The SY69753L PLL complies with the jitter specifications proposed for SONET/SDH equipment defined by the Bellcore Specifications: GR-253-CORE, Issue 2, December 1995 and ITUT Recommendations: G.958 document, when used with differential inputs and outputs. Input Jitter Tolerance Input jitter tolerance is defined as the peak-to-peak amplitude of sinusoidal jitter applied on the input signal that causes an equivalent 1dB optical/electrical power penalty. SONET input jitter tolerance requirement condition is the input jitter amplitude which causes an equivalent of 1dB power penalty.
A
Sinusoidal Input Jitter Amplitude (UI p-p)
15 1.5
-20dB/decade
-20dB/decade
0.40 f0 f1 f2
Frequency
f4
ft
OC/STS-N Level 3
f0 (Hz) 10
f1 (Hz) 30
f2 (Hz) 300
f3 (kHz) 6.5
ft (kHz) 65
Figure 1. Input Jitter Tolerance
Jitter Transfer Jitter transfer function is defined as the ratio of jitter on the output OC-N/STS-N signal to the jitter applied on the input OC-N/ STS-N signal versus frequency. Jitter transfer requirements are shown in Figure 2. Jitter Generation The jitter of the serial clock and serial data outputs shall not exceed .01 U.I. rms when a serial data input with no jitter is presented to the serial data inputs.
Jitter Transfer (dB) 0.1
-20dB/decade
-20
Acceptable Range
fc
Frequency
OC/STS-N Level 3
fc (kHz) 500
Figure 2. Jitter Transfer
P (dB) 0.1
5
Micrel
SY69753L
LOOP FILTER COMPONENTS(1)
R1
C1
R2
C2
PLLSP
PLLSN
PLLRP
PLLRN
R1 = 80 C1 = 1.5F (X7R Dielectric)
NOTE: 1. Suggested Values. Values may vary for different applications.
R2 = 50 C2 = 1.0F (X7R Dielectric)
REFERENCE FREQUENCY SELECTION
DIVSEL1 0 0 1 1 DIVSEL2 0 1 0 1 fRCLK/fREFCLK 8 10 16 20
TIMING WAVEFORMS
tCPWL
tCPWH
REFCLK tODC RCLK tSKEW tDV RDOUT tDH tODC
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Micrel
SY69753L
APPLICATION EXAMPLE
VCC
R13
LED D2
Q1 2N2222A R12
DIVSEL1
DIVSEL2
VCCA
VCCA
LFIN
VCC
VCC
VEE
DIODE D1
CD
32
31
30
29
28
27
26
25 RDOUTP RDOUTN VCCO RCLKP RCLKN VCCO TCLKP TCLKN
VCC
1N4148
R6 R7 R8 R9
NC
R10
1 2 3 4 5 6 7 8 9
PLLSP
24 23 22 21 20 19 18 17 10
PLLSN
RDINP RDINN
1
NC
2
NC
3 4 CLKSEL 5 6 7
NC NC NC
DIVSEL1 DIVSEL2 CD
11
VEEA
12
VEE
13
VEE
14
PLLRN
15
PLLRP
16
CLKSEL
VEE
R11 1k
SW1
GND
Ferrite Bead BLM21A102
R1 C1 1.5F VCCO (+2V) VCC (+2V) VCCA (+2V) C2 1.0F
R2
VCC
L3 L2 C5 22F L1 C6 0.1F C7 6.8F C8 6.8F C11 0.1F C13 0.1F
C9 6.8F
C15 0.1F
C12 0.01F C14 0.01F C16 0.01F
GND
C10 6.8F C17 0.1F C18 0.01F VEE (--1.3V)
VEE
C19 1.0F C20 0.1F C21 0.01F
VEEA (--3V)
Note: C3, C4 are optional
C1 = 1.5F C2 = 1.0F R1 = 80 R2 = 50 R3 through R10 = 5k R12 = 12k R13 = 130
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Micrel
SY69753L
BILL OF MATERIALS
Item C1 C2 C3, C4 C5 C6 C7, C8, C9, C10 C19 C11, C13 C15, C17 C20 C12, C14 C16, C18 C21 D1 D2 J1, J2, J3, J4, J5 J6, J7, J8, J9, J10, J11, J12 L1, L2, L3 Q1 R1 R2 R3, R4, R5, R6 R7, R8, R9, R10 R11 R12 R13 SW1 206-7 CTS Part Number ECU-V1H104KBW ECU-V1H104KBW ECU-V1H104KBW ECS-T1ED226R ECU-V1H104KBW ECS-T1EC685R ECJ-3YB1E105K ECU-V1H104KBW ECU-V1H104KBW ECU-V1H104KBW ECU-V1H103KBW ECU-V1H103KBW ECU-V1H103KBW 1N4148 P300-ND/P301-ND 142-0701-851 Panasonic Johnson Components Murata NTE Manufacturer Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Description 1.5F Ceramic Capacitor, Size 1206 X7R Dielectric, Loop Filter, Critical 1.0F Ceramic Capacitor, Size 1206 X7R Dielectric, Loop Filter, Critical 0.47F Ceramic Capacitor, Size 1206 X7R Dielectric, Loop Filter, Optional 22F Tantalum Electrolytic Capacitor, Size D 0.1F Ceramic Capacitor, Size 1206 X7R Dielectric, Power Supply Decoupling 6.8F Tantalum Electrolytic Capacitor, Size C 1.0F Ceramic Capacitor, Size 1206 X7R Dielectric, VEEA Decoupling 0.1F Ceramic Capacitor, Size 1206 X7R Dielectric, VCCO/VCC Decoupling 0.1F Ceramic Capacitor, Size 1206 X7R Dielectric, VCCA/VEEA Decoupling 0.1F Ceramic Capacitor, Size 1206 X7R Dielectric, VEEA Decoupling 0.01F Ceramic Capacitor, Size 1206 X7R Dielectric, VCCO/VCC Decoupling 0.01F Ceramic Capacitor, Size 1206 X7R Dielectric, VCCA/VEEA Decoupling 0.01F Ceramic Capacitor, Size 1206 X7R Dielectric, VEEA Decoupling Diode T-1 3/4 Red LED Gold Plated, Jack, SMA, PCB Mount Qty. 1 1 2 1 1 4 1 1 1 1 1 1 1 1 1 12
BLM21A102F NTE123A
Ferrite Beads, Power Noise Suppression 2N2222A Buffer/Driver Transistor, NPN 80 Resistor, 2%, Size 1206 Loop Filter Component, Critical 50 Resistor, 2%, Size 1206 Loop Filter Component, Critical 5k Pullup Resistors, 2%, Size 1206 1k Pulldown Resistor, 2%, Size 1206 12k Resistor, 2%, Size 1206 130 Pullup Resistor, 2%, Size 1206 SPST, Gold Finish, Sealed Dip Switch
3 1 1 1 8 1 1 1 1
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Micrel
SY69753L
32 LEAD EPAD-TQFP (DIE UP) (H32-1)
Rev. 01
Package EP- Exposed Pad
Die
CompSide Island
Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane
PCB Thermal Consideration for 32-Pin EPAD-TQFP Package
MICREL, INC.
TEL
1849 FORTUNE DRIVE SAN JOSE, CA 95131 USA
FAX
+ 1 (408) 944-0800
+ 1 (408) 944-0970
WEB
http://www.micrel.com
The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2003 Micrel, Incorporated.
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