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LR38620
LR38620
DESCRIPTION
The LR38620 is a CMOS timing generator IC which generates timing pulses for driving 4 200 kpixel CCD area sensor and processing pulses.
48-PIN QFP
Timing Generator IC for 4 200 k-pixel CCD
PIN CONNECTIONS
TOP VIEW
FEATURES
* Designed for 1/1.8-type 4 200 k-pixel CCD area sensor * Frequency of driving horizontal CCD : 24.54545 MHz * In monitoring mode, it can be obtained 30 fields/s * External shutter control function with serial data input is possible * +3.3 V and +4.5 V power supplies * Package : 48-pin QFP (P-QFP048-0707) 0.5 mm pin-pitch
GND 1 OFDC 2 OFDX 3 V1X 4 VH1AX 5 VH1BX 6 V2X 7 V3X 8 VH3AX 9 VH3BX 10 V4X 11 GND 12
48 47 46 45 44 43 42 41 40 39 38 37 36 GND 35 TST1 34 ED2 33 ED1 32 ED0 31 HD 30 VD 29 DCLK 28 CLK 27 CKO 26 CKI 25 GND 13 14 15 16 17 18 19 20 21 22 23 24 VDD3 VDD3 PBLK BCPX CLPX ADCK FCDS FS SHTR ID VDD3 VDD3
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
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VDD4 VDD4 TST3 TST2 FR FH2 GND GND FH1 ACLX VDD4 VDD4
(P-QFP048-0707)
LR38620
BLOCK DIAGRAM
DCLK TST1 GND GND 25 CKO CLK ED2 ED1 ED0 CKI 26 OSC VDD4 37 VDD4 38 ACLX 39 FH1 40 1/2 GND 41 1/2 GND 42 FH2 43 RESET FR 44 TST2 45 TST3 46 VDD4 47 VDD4 48 LEVEL SHIFTER RESET DECODER 17 CLPX 16 BCPX 15 PBLK 14 VDD3 13 VDD3 H COUNTER GATE 19 FCDS 18 ADCK 1/16 DATA LATCH & SHUTTER CONTROL 24 VDD3 23 VDD3 22 ID 21 SHTR 20 FS RESET 11 V4X HD VD 30
36
35
34
33
32
31
29
28
27
V COUNTER
1 GND
2 OFDC
3 OFDX
4 V1X
5 VH1AX
6 VH1BX
7 V2X
8 V3X
9 VH3AX
10 VH3BX
12 GND
2
LR38620
PIN DESCRIPTION
PIN NO. SYMBOL IO SYMBOL POLARITY PIN NAME - 1 GND - Ground 2 OFDC O3MR1 Control pulse output for OFD voltage DESCRIPTION A grounding pin. A pulse to control OFD voltage. A pulse that sweeps the charge of the photo-diode for the electronic shutter. Connect to OFD pin of the CCD through the vertical driver IC and DC offset circuit. Held at H level in normal mode. A vertical transfer pulse for the CCD. Connect to V1X pin of vertical driver IC. A pulse that transfers the charge of the photo-diode to the vertical shift register. Connect to VH1AX pin of vertical driver IC. A pulse that transfers the charge of the photo-diode to the vertical shift register. Connect to VH1BX pin of vertical driver IC. A vertical transfer pulse for the CCD. Connect to V2X pin of vertical driver IC. A vertical transfer pulse for the CCD. Connect to V3X pin of vertical driver IC. A pulse that transfers the charge of the photo-diode to the vertical shift register. Connect to VH3AX pin of vertical driver IC. A pulse that transfers the charge of the photo-diode to the vertical shift register. Connect to VH3BX pin of vertical driver IC. A vertical transfer pulse for the CCD. Connect to V4X pin of vertical driver IC. A grounding pin. Supply of +3.3 V power. Supply of +3.3 V power. A pulse for pre-blanking. This pulse is controlled by serial data BLKCNT. Pre-blanking pulse output BLKCNT = H; This pulse stays low during the absence of effective pixels within the vertical blanking or during the sweepout signal. BLKCNT = L; Continuous pulse The output phase of PBLK is selected by serial data.
3
OFDX
O3MR1
OFD pulse output
4
V1X
O3MR1
Vertical transfer pulse output 1 Readout pulse output 1A Readout pulse output 1B Vertical transfer pulse output 2 Vertical transfer pulse output 3 Readout pulse output 3A Readout pulse output 3B Vertical transfer pulse output 4 - - - Ground Power supply Power supply
5
VH1AX
O3MR1
6
VH1BX
O3MR1
7 8
V2X V3X
O3MR1 O3MR1
9
VH3AX
O3MR1
10
VH3BX
O3MR1
11 12 13 14
V4X GND VDD3 VDD3
O3MR1 - - -
15
PBLK
O3MR1
3
LR38620
PIN NO. SYMBOL IO SYMBOL POLARITY PIN NAME DESCRIPTION A pulse to clamp the optical black signal. This pulse is controlled by serial data BCPCNT. Optical black clamp pulse output BCPCNT = H; This pulse stays high during the absence of effective pixels within the vertical blanking or during the sweepout signal. BCPCNT = L; This pulse stays high during the sweepout signal. 17 18 CLPX ADCK O3MR1 O6M32 Clamp pulse output AD clock output A pulse to clamp the dummy outputs of the CCD signal. This pulse stays high during the sweepout period. An output pin for AD converter. The output phase of ADCK is selected by serial data in 90 steps. A pulse to clamp the feed-through level for the CCD. The output phase and output polarity of FCDS are selected by serial data. A pulse to sample-hold the signal for the CCD. 20 21 22 23 24 25 26 27 28 FS SHTR ID VDD3 VDD3 GND CKI CKO CLK O6M32 O3MR1 O3MR1 - - - OSCI3 OSCO3 O6M32 - - - - - CDS pulse output 2 Trigger output Line index pulse output Power supply Power supply Ground Clock input Clock output Clock output The output phase and output polarity of FS are selected by serial data. A trigger pulse for effective signal period. The pulse is used in the color separator. The signal switches between high and low at every line. Supply of +3.3 V power. Supply of +3.3 V power. A grounding pin. An input pin for reference clock oscillation. The frequency is 49.0909 MHz. An output pin for reference oscillation. The output is the inverse of CKI (pin 26). An output pin to generate HD and VD pulses. The frequency is 24.54545 MHz. An output pin for DSP IC. The frequency is 24.54545 MHz. 29 DCLK O6M32 Clock output Vertical reference pulse input Horizontal drive pulse input - Strobe pulse input Shift register clock input The output phase of DCLK is selected by serial data in 90 steps. An input pin for reference of vertical pulse. Connect to VD pin of DSP IC. An input pin for reference of horizontal pulse. Connect to HD pin of DSP IC. An input pin for the strobe pulse, to control the functions of LR38620. For details, see "Serial Data Control". An input pin for the clock of the shift register, to control the functions of LR38620. For details, see "Serial Data Control".
16
BCPX
O3MR1
19
FCDS
O6M32
CDS pulse output 1
30 31 32
VD HD ED0
IC3 IC3 ICSD3
33
ED1
ICSD3
-
4
LR38620
PIN NO. SYMBOL IO SYMBOL POLARITY 34 35 36 37 38 39 ED2 TST1 GND VDD4 VDD4 ACLX ICSD3 ICD3 - - - ICU4 - - - - - - PIN NAME Shift register data input Test pin 1 Ground Power supply Power supply All clear input Horizontal transfer - - pulse output 1 Ground Ground Horizontal transfer pulse output 2 Reset pulse output - - - - Test pin 2 Test pin 3 Power supply Power supply DESCRIPTION An input pin for the data of the shift register, to control the functions of LR38620. For details, see "Serial Data Control". A test pin. Set open or to L level in normal mode. A grounding pin. Supply of +4.5 V power. Supply of +4.5 V power. An input pin for resetting all internal circuit at power-on. Connect to VDD3 through the diode and GND through the capacitor. A horizontal transfer pulse for the CCD. Connect to OH1 pin of the CCD. A grounding pin. A grounding pin. A horizontal transfer pulse for the CCD. Connect to OH2 pin of the CCD. A pulse to reset the charge of output circuit. The output phase of FR is selected by serial data. A test pin. Set open or to L level in normal mode. A test pin. Set open or to L level in normal mode. Supply of +4.5 V power. Supply of +4.5 V power.
O3MR1 O6M32 O8M43 OSCI3 OSCO3 : : : : : Output pin (output high level is VDD3.) Output pin (output high level is VDD3.) Output pin (output high level is VDD4.) Input pin for oscillation Output pin for oscillation
40 41 42 43 44 45 46 47 48
IC3 ICD3 ICSD3 ICD4 ICU4
FH1 GND GND FH2 FR TST2 TST3 VDD4 VDD4
O8M43 - - O8M43 O8M43 ICD4 ICD4 - -
: Input pin (CMOS level) : Input pin (CMOS level with pull-down resistor) : Input pin (CMOS schmitt-trigger level with pulldown resistor) : Input pin (CMOS level with pull-down resistor) : Input pin (CMOS level with pull-up resistor)
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LR38620
Serial Data Control
SERIAL DATA INPUT TIMING
ED0 ED1
ED2
D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24
ED2 is shifted by the rising edge of ED1, and is latched by the pulse #1 which is generated after 122 to 162 ns delay from the rising edge of ED0. (See Fig. 2.) The latched serial data are divided into two types by the data of D00, and are relatched by the pulse #2 which is generated after 203 to 243 ns delay from the rising edge of ED0. (See Fig. 1.)
INMD is effective at the start of #3 horizontal line, and shutter control data are effective at the start of #11 horizontal line in monitoring mode and #93 horizontal line in still mode, and other data are effective at pulse #2. ED0 should be at low level during data inputs of ED1 and ED2 or while ACLX is at low level.
244 ns min. ED0 24.54545 MHz Pulse #1 Pulse #2 122 ns 203 ns
Fig. 1 Data Latch Timing
Mode VD VH1AX VH3AX ED0 ED1 ED2 OFDC
Monitoring Odd Field
Still Even Field
Monitoring
from monitoring mode to still mode data input period 10 ms min.
from still mode to monitoring mode data input period
VD HD ED0
5 s min. 5 s min.
Fig. 2 Input Pulse Timing of ED0, ED1 and ED2
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LR38620
SERIAL DATA INPUTS D00 = L
DATA D01-D09 D10-D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 NAME SDV0-SDV8 SDH0-SDH5 SDF0 SDF1 SDF2 SMD PWSA INMD Dummy Dummy VHCNT FUNCTION Integration time control in field period step by horizontal period. Dummy Integration time control by field period. Electronic shutter mode control Power save control Integration mode control Dummy Dummy VH1AX to VH3BX control Normal DATA = L - Fix to L level - - Power save Still Monitoring Fix to L level Fix to L level Output Held at H level DATA = H AT ACLX = L All L All L All L L L L L L L
D00 = H
DATA D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 NAME ML1 ML2 MR1 MR2 MR3 MC1 MC2 MC3 MS1 MS2 MS3 MD1 MD2 MD3 MA1 MA2 Dummy Dummy Dummy MP1 MP2 PLCH BLKCNT BCPCNT Dummy Fix to L level All L - All L Phase control - All L - All L FUNCTION DATA = L - DATA = H AT ACLX = L All L
-
All L
-
All L
Phase control Polarity control of FCDS and FS pulses PBLK control BCPX control Negative Continuous Continuous
- Positive Discontinuous Discontinuous
All L L L L
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LR38620
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply voltage Input voltage Output voltage Operating temperature Storage temperature SYMBOL VDD3, VDD4 VI3 VI4 VO3 VO4 TOPR TSTG RATING -0.3 to +5.5 -0.3 to VDD3 + 0.3 -0.3 to VDD4 + 0.3 -0.3 to VDD3 + 0.3 -0.3 to VDD4 + 0.3 -20 to +70 -55 to +150 UNIT V V V V V C C
ELECTRICAL CHARACTERISTICS DC Characteristics
PARAMETER Input "Low" voltage Input "High" voltage Input "Low" voltage Input "High" voltage Hysteresis voltage Input "Low" voltage Input "High" voltage Input "Low" current Input "High" current Input "Low" current Input "High" current Input "Low" current Input "High" current Input "Low" current Input "High" current Output "Low" voltage Output "High" voltage Output "Low" voltage Output "High" voltage Output "Low" voltage Output "High" voltage SYMBOL VIL3-1 VIH3-1 VIL3-2 VIH3-2 VT+ - VT- VIL4 VIH4 |IIL3-1| |IIH3-1| |IIL3-2| |IIH3-2| |IIL4-1| |IIH4-1| |IIL4-2| |IIH4-2| VOL3-1 VOH3-1 VOL3-2 VOH3-2 VOL4 VOH4 0.8VDD4 VI = 0 V VI = VDD3 VI = 0 V VI = VDD3 VI = 0 V VI = VDD4 VI = 0 V VI = VDD4 IOL = 3 mA IOH = -2.5 mA IOL = 12 mA IOH = -10 mA IOL = 20 mA IOH = -20 mA VDD3 - 0.5 0.4 VDD4 - 0.5 20 VDD3 - 0.5 0.4 8.0 20 1.0 1.0 3.0 100 300 5.0 5.0 300 0.4 Schmitt-buffer 0.14VDD3 0.2VDD4
(VDD3 = 3.310%, VDD4 = 4.510%, TOPR = -20 to +70C)
CONDITIONS MIN. 0.8VDD3 0.2VDD3 0.75VDD3 TYP. MAX. UNIT 0.2VDD3 V V V V V V V A A A A A A A A V V V V V V NOTE 1, 2
3
4, 5 1 2, 3 4 5 6 7 8
NOTES :
1. 2. 3. 4. 5. Applied Applied Applied Applied Applied to to to to to inputs (IC3, OSCI3). input (ICD3). input (ICSD3). input (ICU4). input (ICD4). 6. Applied to outputs (OSCO3, O3MR1). (Output (OSCO3) measures on condition that input (OSCI3) level is 0 V or VDD3.) 7. Applied to output (O6M32). 8. Applied to output (O8M43).
8
LR38620
PACKAGE OUTLINES 48 QFP (P-QFP048-0707)
(Unit : mm)
P-0.5TYP. 36 M 37 0.08
48-0.20.08 (1.0) 25 24 7.00.2 9.00.3
0.150.05 See Detail A
(1.0)
48 1 (1.0)
13 12 (1.0)
0.10
Detail A 0.650.2 1.450.2 Package base plane 0.10.1 1.00.15 0.650.2 1.450.2
7.00.2 9.00.3
0-10 0.5 0.60.15 0.10.1 0.25
Seating plane
9

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