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| 5 4 3 2 1 D STAC9750_MB - Main Board Audio Reference Design Overview SCOPE: The STAC9750 Main Board reference design provides a complete 2-channel audio solution with digital audio I/O. REVISION HISTORY: 1) 7/06/01 - Original release. 2) 8/21/01 - Changed PLL mode table for CA3. 2) 12/28/01 - changed AFILT caps to 820pF. 3) 5/9/03 - Added SPDIF Enable/Disable resistor option. D CDROM In MIC In BLOCK DIAGRAM: AUX In C UNIQUE COMPONENTS: 1) STAC9750 Audio Codec with 48-TQFP, 9.0mm tip-to-tip, package. 2) 24.576 MHz crystal in Epson MA-306 package, use dual MA-306/CA-301 layout. 3) ZR78L05 in SOT-223. 4) Radial lead capacitors PCB footprints are listed in PackageDiameter/LeadSpacing/LeadDiameter form. 5) EIA prefix footprint surface mount components (EIA abcd) have dimensions of a.b mm by c.d mm. 6) SMT prefix footprint surface mount components (SMT wxyz) have dimensions of 0.wx inches by 0.yz inches. LINE In C TAD PNONE Analog In Main Board AC Link Analog Out MONO Out STAC9750 Power Conditioning: +5V AVDD +3.3V DVDD Headphone Out B S/PDIF Out B CODEC Clocking This design is the property of SigmaTel Inc. It is offered on an "as is" basis, and carries no implied warranty. 3815 Capital of Texas Hwy. Suite 300 Austin, TX 78704 tel: (512)381-3700 fax: (512)744-1700 Title SigmaTel, Inc. A A Sigmatel Main Board Reference Design Overview Size A 5 4 3 STAC9750_MB 2 2-9750-RD1-4.0-0503 Sheet 1 1 Rev A3 of 7 Date: Friday, May 09, 2003 A B C D E DVDD INSTALL PULL-UP TO DISABLE SPDIF. 5 R36 R37 10K_NA 10K R1 R2 5 5 INSTALL PULL-DOWN TO ENABLE SPDIF. SPDIF_OUT EAPD CID1 CID0 GPIO1 GPIO0 HP_OUT_R HP_OUT_L MONO_OUT 6 7 7 6 4 4 5 * Use series resistors on headphone outputs when driving low impedance, highly reactive loads (headphones) to improve amplifier stability. AVDD 5 DVDD Place 0.1uF decoupling caps as close to Codec as possible. 4 SPDIF EAPD CID1 CID0 GPIO1 GPIO0 AVSS2 HP_OUT_R HP_COMM HP_OUT_L AVDD2 MONO_OUT 48 47 46 45 44 43 42 41 40 39 38 37 C3 0.1uF C4 1uF U1 STAC9750 C1 1uF C2 0.1uF Place 0.1uF decoupling caps as close to Codec as possible. 4 7 7 XTAL_IN XTAL_OUT AC97_SDATA_OUT AC97_SDATA_IN0 AC97_SYNC 3 CODEC_RST# PCBEEP 3 PHONE AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND CD_R MIC1 MIC2 LINE_IN_L LINE_IN_R 1 2 3 4 5 6 7 8 9 10 11 12 DVDD1 XTL_IN XTL_OUT DVSS1 SDATA_OUT BIT_CLK DVSS2 SDATA_IN DVDD2 SYNC RESET# PC_BEEP LINE_R LINE_L NC NC CAP2 NC AFILT2 AFILT1 VREFOUT VREF AVSS1 AVDD1 36 35 34 33 32 31 30 29 28 27 26 25 LINE_OUT_R LINE_OUT_L 4 4 VREFOUT 4 C5 0.1uF C6 1uF 3 **C7 1uF AC97_BITCLK C10 27pF R3 22R C8 C9 820pF 820pF 13 14 15 16 17 18 19 20 21 22 23 24 2 OPTIONAL EMI FILTER: Capacitor value selected to minimize high-frequency components in clock output. Capacitor should be selected to critically damp, or slightly under damp the BIT_CLK signal. Tie analog and digital grounds together near codec. JP1 1 2 MIC2 LINE_IN_R LINE_IN_L MIC1 CD_R CD_GND CD_L AUX_IN_R AUX_IN_L PHONE 4 4 4 5 5 5 5 5 5 ** Vref CAP filters Vref and controlls internal anti-pop circuitry. Values greater than 10uF not recommended. 2 VIDEO_IN_R VIDEO_IN_L JP2 4 1 MIC_GND 1 2 Route microphone ground with microphone signal and connect microphone ground to analog ground near codec to reduce noise. A B Unused inputs C11 grounded 0.1uF through capacitor. VIDEO_IN_R VIDEO_IN_L MIC2 C12 0.1uF Title 3815 Capital of Texas Hwy. Suite 300 Austin, TX 78704 tel: (512)381-3700 fax: (512)744-1700 1 SigmaTel, Inc. STAC9750 AC'97 Audio Codec Size A STAC9750_MB D 2-9750-RD1-4.0-0503 Sheet 2 E Rev C of 7 Date: Friday, May 09, 2003 C 5 4 3 2 1 CODEC DISABLE CIRCUIT AC97_RESET# D C14 0.1uF DVDD DVDD C13 0.1uF D 5 1 4 2 3 5 PRIMARY_DN# CDC_DN_ENAB# 2 4 CODEC_RST# 2 U3 SN74LVC1G04DBVR U2 SN74LVC1G08DBVR Single Gate devices available from Texas Instruments. http://www.ti.com/ C 3 J1 C R4 10K 1 2 3 DVDD CON3 R5 10K J1 (3 pin header) Pins shorted Onboard Codec 1-2 Disabled 2-3 Enabled POWER SUPPLY L1 B DVDD +3.3V_main EXC-CL3225U EIA 3225 + +10uF/6.3V C15 Audio Codec Digital Power LAYOUT NOTE FOR ZSR500G: 1 2 3 2 Codec digital powered from +3.3Vmain since audio codecs are not required to retain their register states locally during suspend modes. L2 +12V TOP VIEW Device requires large copper pad for proper thermal regulation. Please consult Zetex at http://www.zetex.com/ SOT-223 B U4 ZSR500/SOT 3 IN OUT 1 AVDD EXC-CL3225U EIA 3225 + C16 +10uF/16V + 2 Audio Codec Analog Power C17 +10uF/6.3V Title GND A 3815 Capital of Texas Hwy. Suite 300 Austin, TX 78704 tel: (512)381-3700 fax: (512)744-1700 SigmaTel, Inc. A CODEC DISABLE CIRCUITS This design is the property of SigmaTel Inc. It is offered on an "as is" basis, and carries no implied warranty. 5 4 3 Size A Date: STAC9750_MB Friday, May 09, 2003 2 2-9750-RD1-4.0-0503 Sheet 3 1 Rev A of 7 5 4 3 2 1 Headphone (Line) Out 2 2 LINE_OUT_R LINE_OUT_L D C18 +3.3uF/16V + C19 1000pF R6 47K L3 EXC-CL3225U 2 3 4 5 1 J2 CUI SJ-3505 + D Primary AC-Coupling Capacitors *** C21 220uF/6.3V C20 +3.3uF/16V L4 EXC-CL3225U Only install one set of capacitors. 2 2 HP_OUT_R HP_OUT_L C22 1000pF C23 220uF/6.3V + R7 47K Alternate AC-Coupling Capacitors *** *** Note: 220uF ac-coupling capacitors will drive loads of 32 ohms and greater and still meet the bandwidth requirements of PC2001. 3.3uF ac-coupling capacitors will drive loads of 10K ohms and greater and still meet the bandwidth requirements of PC2001. + C Microphone Input Circuit Supports 3-Terminal and 2-Terminal MIC input. AVDD C This node 2.0V min at 800uA, as required by PC2001. Do not install pull-up to AVdd if VREFOUT is used to power microphone. R9 R8 1.8K REAR PANEL B OPTIONAL 500R R10 2K 2 3 4 5 1 J3 CUI SJ-3505 B 2 2 VREFOUT MIC1 C24 0.068uF C26 +4.7uF/6.3V + R11 3.3K External LINE-IN Circuit 2 2 LINE_IN_R LINE_IN_L 0.33uF 0.33uF C27 C28 C25 3300pF L5 EXC-CL3225U 2 3 4 5 1 J4 CUI SJ-3505 2 MIC_GND Microphone ground should be routed back to codec along with the main microphone signal trace. Improper microphone grounding can result in audible mouse and CDROM noise. Tie MIC_GND to AGND at a point near the codec. R12 47K R13 47K L6 EXC-CL3225U A 3815 Capital of Texas Hwy. Suite 300 Austin, TX 78704 tel: (512)381-3700 fax: (512)744-1700 Title SigmaTel, Inc. A Rear Panel Jacks This design is the property of SigmaTel Inc. It is offered on an "as is" basis, and carries no implied warranty. 5 4 3 Size A STAC9750_MB 2 2-9750-RD1-4.0-0503 Sheet 4 1 Rev A of 7 Date: Friday, May 09, 2003 A B C D E INTERNAL AUDIO JACKS 4 CDROM Circuit with 4.5dB Attenuation J5 4 3 2 1 MOLEX 70553-0038 R14 R15 R16 5.6K 5.6K 5.6K C29 C30 C31 0.33uF 0.33uF 0.33uF CD_R CD_GND CD_L 2 2 2 4 3 1 2 3 4 R17 10K R18 10K R19 10K Attenuation circuit protects against possible clipping from DVD and CD drives with output levels greater than 1.0V RMS. 3 TAD 1 2 3 4 J7 MOLEX 70553-0038 R20 0 R21 47K C32 1uF PHONE 2 AUX Input Circuit J6 4 3 2 1 MOLEX 70553-0038 MONO_OUT 2 1 2 3 4 C33 C34 0.33uF 0.33uF AUX_IN_R AUX_IN_L 2 2 2 2 C35 1uF R24 0 R25 47K C36 1000pF R22 47K R23 47K 1 2 3 4 This design is the property of SigmaTel Inc. It is offered on an "as is" basis, and carries no implied warranty. 3815 Capital of Texas Hwy. Suite 300 Austin, TX 78704 tel: (512)381-3700 fax: (512)744-1700 Title SigmaTel, Inc. 1 1 Analog Audio Jacks Size A A B C STAC9750_MB D 2-9750-RD1-4.0-0503 Sheet 5 E Rev A of 7 Date: Friday, May 09, 2003 A B C D E S/PDIF RCA OUTPUT 4 R26 OPT 0 Install if Transformer not used 4 C37 2 SPDIF_OUT R27 200 0.1uF 4 2 R28 120 8 1 J8 RCA JACK 1 6 5 2 T1 SC979-03 C38 100pF Scientific Conversion SC979-03 1:1 3 http://www.scientificonversion.com C39 100pF 3 Please do not populate both the 3.5mm and the RCA SPDIF options. 2 S/PDIF SERIAL OUTPUT AVDD R29 10K GPIO0 J9 C40 470pF R30 110 4 5 6 3 2 2 2 C41 0.1uF R31 220 1 2 SPDIF_OUT R32 110 This design is the property of SigmaTel Inc. It is offered on an "as is" basis, and carries no implied warranty. Drive IC Title 1 Some optical trasmitters float high when the codec is reset which causes the codec to disable the S/PDIF output. Install R38 to prevent unwanted S/PDIF disable. A B R33 OPT 100K 8 7 9 C42 0.1uF 3815 Capital of Texas Hwy. Suite 300 Austin, TX 78704 tel: (512)381-3700 fax: (512)744-1700 SigmaTel, Inc. 1 GP1FE500TK S/PDIF Output Size A STAC9750_MB D Datasheet available at: http://www.sharp.co.jp/ecg/opto/ C 2-9750-RD1-4.0-0503 Sheet 6 E Rev A of 7 Date: Friday, May 09, 2003 5 4 3 2 1 D D Optional Main Board Clock Source Do not populate C44 or Y1 when using an external clock. Replace C45 with 0 ohm resistor SEE TABLE BELOW C43 OPT 0.01uF ** 14.318MHz C C C44 27pF XTAL_IN Y1 24.576MHz XTAL_OUT C45 27pF B B 2 2 Motherboard Clock Frequency determines the CID0/CID1 values when external clock is selected (XTAL_OUT must be grounded by replacing C45 with a 0 ohm resistor) Clock Source A **14.318 MHz 27 MHz 48 Mhz 24.576 MHz R40 CID1 open open 1K 1K R39 CID0 open 1K open 1K C45 XTAL_OUT GND GND GND GND 2 2 CID0 CID1 R34 R35 OPT 1K OPT 1K Title 3815 Capital of Texas Hwy. Suite 300 Austin, TX 78704 tel: (512)381-3700 fax: (512)744-1700 SigmaTel, Inc. A Codec Clocking Size A Date: 3 STAC9750_MB Friday, May 09, 2003 2 *STAC9750 CA1 and CA2 revisions differ from this chart. 5 4 2-9750-RD1-4.0-0503 Sheet 7 1 Rev B of 7 |
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