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R8C/11 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
REJ03B0034-0120Z Rev.1.20 2003.10.31
1. Overview
This MCU is built using the high-performance silicon gate CMOS process using a R8C/Tiny Series CPU core and is packaged in a 32-pin plastic molded LQFP. This MCU operates using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, it is capable of executing instructions at high speed.
1.1 Applications
Electric household appliance, office equipment, housing equipment (sensor, security), general industrial equipment, audio, etc.
Rev.1.20
Oct.31.2003
page 1 of 26
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
1. Overview
1.2 Performance Outline
Table 1.1. lists the performance outline of this MCU. Table 1.1 Performance outline Item Performance CPU Number of basic instructions 89 instructions Shortest instruction execution time 50 ns (f(XIN) = 20 MHZ, VCC = 3.0 to 5.5 V) 100 ns (f(XIN) = 10 MHZ, VCC = 2.7 to 5.5 V) Operating mode Single-chip Address space 1M bytes Memory capacity See Table 1.2. Peripheral Interrupt Internal: 10 sources, External: 5 sources, function Software: 4 sources, Priority level: 7 levels Watchdog timer 15 bits x 1 (with prescaler) Timer Timer X: 8 bits x 1 channel, Timer Y: 8 bits x 1 channel, Timer Z: 8 bits x 1 channel (Each timer equipped with 8-bit prescaler) Timer C: 16 bits x 1 channel Circuits of input capture and output compare. Serial I/O *1 channel Clock synchronous, UART *1 channel UART A-D converter 10-bit A-D converter: 1 circuit, 12 channels Clock generation circuit 2 circuits *Main clock generation circuit (Equipped with a built-in feedback resistor) *Ring oscillator (high speed, low speed) On High-speed ring oscillator the frequency adjustment function is usable. Oscillation stop detection function Stop detection of main clock oscillation Voltage detection circuit Included Power on reset circuit Included Port Input/Output: 22 (including LED drive port), Input: 2 (LED drive I/O port: 8, max. 20 mA) Electrical Power supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHZ) characteristics VCC = 2.7 to 5.5 V (f(XIN) = 10 MHZ) Power consumption Typ. 9 mA (VCC = 5.0 V, (f(XIN) = 20 MHZ, High-speed mode) Typ. 5 mA (VCC = 3.0 V, (f(XIN) = 10 MHZ, High-speed mode) Typ. 35 A (VCC = 3.0 V, Wait mode, Peripheral clock off) Typ. 0.7 A (VCC = 3.0 V, Stop mode) Flash memory Program/erase voltage VCC = 2.7 to 5.5 V Number of program/erase 100 times Operating ambient temperature -20 to 85 C -40 to 85 C (option) Package 32-pin plastic mold LQFP Option: If you require this option, please specify so.
Rev.1.20
Oct.31.2003
page 2 of 26
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
1. Overview
1.3 Block Diagram
Figure 1.1 shows this MCU block diagram.
8
8
5
1
2
I/O port
Port P0
Port P1
Port P3
Port P4
Peripheral functions
Timer A-D converter (10 bits 12 channels) System clock generator UART or Clock synchronous serial I/O (8 bits 1 channel) UART (8 bits 1 channel) XIN-XOUT High-speed ring oscillator Low-speed ring oscillator
Timer X (8 bits) Timer Y (8 bits) Timer Z (8 bits) Timer C (16 bits)
R8C Series CPU core
Watchdog timer (15 bits)
R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC FLG
Memory
ROM (Note 1) RAM (Note 2)
Multiplier
Note 1: ROM size depends on MCU type. Note 2: RAM size depends on MCU type.
Figure 1.1 Block Diagram
Rev.1.20
Oct.31.2003
page 3 of 26
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
1. Overview
1.4 Product List
Table 1.2 lists the products. Table 1.2 Product List
Type No. ROM capacity 8K bytes 12K bytes 16K bytes 8K bytes 12K bytes 16K bytes RAM capacity 512 bytes 768 bytes 1K bytes 512 bytes 768 bytes 1K bytes Package type 32P6U-A 32P6U-A 32P6U-A 32P6U-A 32P6U-A 32P6U-A D version As of Oct. 2003 Remarks Flash memory version
** R5F21113FP ** R5F21114FP ** R5F21112DFP ** R5F21113DFP ** R5F21114DFP ** : Under development **
R5F21112FP
Type No. R 5 F
21 11 4 D FP
Package type: FP : 32P6U Shows characteristics and others. D: Operating ambient temperature -40 C to 85 C No symbol: Operating ambient temperature -20 C to 85 C ROM capacity: 2 : 8 KBytes. 3 : 12 KBytes. 4 : 16 KBytes. R8C/11 group
R8C/Tiny series
Memory type: F: Flash memory version
Renesas MCU Renesas semiconductors
Figure 1.2 Type No., Memory Size, and Package
Rev.1.20
Oct.31.2003
page 4 of 26
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
1. Overview
1.5 Pin Configuration
Figure 1.3 shows the pin configuration (top view).
PIN CONFIGURATION (top view)
P30/CNTR0/CMP10 AVSS P31/TZOUT/CMP11 AVCC/VREF P32/INT2/CNTR1/CMP12 P33/INT3/ TCIN
24 23 22 21 20 19 18 17 P06/AN1 P05/AN2 P04/AN3 MODE P03/AN4 P02/AN5 P01/AN6 P00/AN7/TxD11 25 26 27 28 29 30 31 32 16 15 14 13 12 11 10 9 P45/INT0 P10/KI0/AN8/CMP00 P11/KI1/AN9/CMP01 P12/KI2/AN10/CMP02 P13/KI3/AN11 P14/TxD0 P15/RxD0 P16/CLK0
12345678
P07/AN0 IVCC P37/TxD10/RxD1 CNVSS
R8C/11 Group
Notes: 1. P47 functions only as an input port. 2. When using On-chip debugger, do not use pins P00/AN7/TxD11 and P37/TxD10/RxD1.
RESET XOUT/P47 (Note 1) VSS XIN/P46 VCC P17/INT1/CNTR0
Package: 32P6U-A
Figure 1.3 Pin Configuration (Top View)
Rev.1.20
Oct.31.2003
page 5 of 26
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
1. Overview
1.6 Pin Description
Table 1.3 shows the pin description Table 1.3 Pin description Signal name Power supply input IVcc Analog power supply input Reset input CNVss MODE Main clock input Pin name Vcc, Vss IVcc AVcc, AVss
___________
I/O type Input Output Input
RESET CNVss MODE XIN
Input Input Input Input Output
_______
Main clock output XOUT
_____ _______
INT interrupt input INT0 to INT3 _____ _____ Key input interrupt KI0 to KI3 input Timer X CNTR0 ____________ CNTR0 Timer Y CNTR1 Timer Z TZOUT Timer C TCIN CMP00 to CMP03, CMP10 to CMP13 Serial interface CLK0 RxD0, RxD1 TxD0, TxD10, TxD11 Reference voltage VREF input A-D converter AN0 to AN11 I/O port P00 to P07, P10 to P17, P30 to P33, P37, P45
Input Input Input/Output Output Input/Output Output Input Output Input/Output Input Output Input Input Input/Output
Function Apply 2.7 V to 5.5 V to the Vcc pin. Apply 0 V to the Vss pin. Connect this pin to Vss via a capacitor (0.1 F). These are power supply input pins for A-D converter. Connect the AVss pin to Vss. Connect a capacitor between pins AVcc and AVss. "L" on this input resets the MCU. Connect this pin to Vss via a resistor. Connect this pin to Vcc via a resistor. These pins are provided for the main clock generating circuit input/output. Connect a ceramic resonator or a crystal oscillator between the XIN and XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open. ______ These are INT interrupt input pins. These are key input interrupt input pins. This is the timer X I/O pin. This is the timer X output pin. This is the timer Y I/O pin. This is the timer Z output pin. This is the timer C input pin. These are the timer C output pins. This is a transfer clock I/O pin. These are serial data input pins. These are serial data output pins. This is a reference voltage input pin for A-D converter. These are analog input pins for A-D converter. These are 8-bit CMOS I/O ports. Each port has an input/output select direction register, allowing each pin in that port to be directed for input or output individually. Any port set to input can select whether to use a pullup resistor or not by program. P10 to P17 also function as LED drive ports. These are input only pins.
Input port
P46, P47
Input
Rev.1.20
Oct.31.2003
page 6 of 26
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. There are two register banks.
b31
b15
b8 b7
b0
R2 R3
R0H(R0's high bits) R0L(R0's low bits) R1H(R1's high bits) R1L(R1's low bits) R2 R3 A0 A1 FB Address registers (Note 1) Frame base registers (Note 1)
b0
Data registers (Note 1)
b19
b15
INTBH
INTBL
Interrupt table register
The upper 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL.
b19 b0
PC
b15 b0
Program counter
USP ISP SB
b15 b0
User stack pointer Interrupt stack pointer Static base register
FLG
b15 b8 b7 b0
Flag register
IPL
U I OB SZ DC
Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area
Note 1: These registers comprise a register bank. There are two register banks.
Figure 2.1. Central Processing Unit Register
2.1 Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to R3 are the same as R0. The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers. R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32bit data register (R2R0). R3R1 is the same as R2R0.
Rev.1.20
Oct.31.2003
page 7 of 26
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
2. Central Processing Unit (CPU)
2.2 Address Registers (A0 and A1)
The register A0 consists of 16 bits, and is used for address register indirect addressing and address register relative addressing. They also are used for transfers and logic/logic operations. A1 is the same as A0. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
2.3 Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7 Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8 Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status. 2.8.1 Carry Flag (C Flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. 2.8.2 Debug Flag (D Flag) The D flag is used exclusively for debugging purpose. During normal use, it must be set to "0". 2.8.3 Zero Flag (Z Flag) This flag is set to "1" when an arithmetic operation resulted in 0; otherwise, it is "0". 2.8.4 Sign Flag (S Flag) This flag is set to "1" when an arithmetic operation resulted in a negative value; otherwise, it is "0". 2.8.5 Register Bank Select Flag (B Flag) Register bank 0 is selected when this flag is "0" ; register bank 1 is selected when this flag is "1". 2.8.6 Overflow Flag (O Flag) This flag is set to "1" when the operation resulted in an overflow; otherwise, it is "0". 2.8.7 Interrupt Enable Flag (I Flag) This flag enables a maskable interrupt. Maskable interrupts are disabled when the I flag is "0", and are enabled when the I flag is "1". The I flag is cleared to "0" when the interrupt request is accepted. 2.8.8 Stack Pointer Select Flag (U Flag) ISP is selected when the U flag is "0"; USP is selected when the U flag is "1". The U flag is cleared to "0" when a hardware interrupt request is accepted or an INT instruction for software interrupt Nos. 0 to 31 is executed. 2.8.9 Processor Interrupt Priority Level (IPL) IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than IPL, the interrupt is enabled. 2.8.10 Reserved Area When write to this bit, write "0". When read, its content is indeterminate.
Rev.1.20
Oct.31.2003
page 8 of 26
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
3. Memory
3. Memory
Figure 3.1 is a memory map of this MCU. The address space extends the 1M bytes from address 0000016 to FFFFF16. The internal ROM is allocated in a lower address direction beginning with address 0FFFF16. For example, a 16-Kbyte internal ROM is allocated to the addresses from 0C00016 to 0FFFF16. The fixed interrupt vector table is allocated to the addresses from 0FFDC16 to 0FFFF16. Therefore, store the start address of each interrupt routine here. The internal RAM is allocated in an upper address direction beginning with address 0040016. For example, a 1-Kbyte internal RAM is allocated to the addresses from 0040016 to 007FF16. In addition to storing data, the internal RAM also stores the stack used when calling subroutines and when interrupts are generated. Special function registers (SFR) are allocated to the addresses from 0000016 to 002FF16. Peripheral function control registers are located here. Of the SFR, any space which has no functions allocated is reserved for future use and cannot be used by users.
0000016 SFR
(See Chapter 4 for details.)
002FF16
0040016 Internal RAM 0XXXX16 0FFDC16 Undefined instruction Overflow BRK instruction Address match Single step
Watchdog timer,Oscillation stop detection,Voltage detection
0YYYY16 Internal ROM 0FFFF16 Expanding area FFFFF16 0FFFF16
(Reserved) (Reserved) Reset
Type name
R5F21114FP, R5F21114DFP R5F21113FP, R5F21113DFP R5F21112FP, R5F21112DFP
Internal ROM Address 0YYYY16 Size
16K bytes 12K bytes 8K bytes 0C00016 0D00016 0E00016
Internal RAM Address 0XXXX16 Size
1K bytes 768 bytes 512 bytes 007FF16 006FF16 005FF16
Figure 3.1 Memory Map
Rev.1.20
Oct.31.2003
page 9 of 26
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
4. Special Function Register (SFR)
4. Special Function Register (SFR)
Address 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16
Register
Symbol
After reset
Processor mode register 0 1 Processor mode register 1 System clock control register 0 System clock control register 1 High-speed ring control register 0 Address match interrupt enable register Protect register High-speed ring control register 1 Oscillation stop detection register Watchdog timer reset register Watchdog timer start register Watchdog timer control register Address match interrupt register 0
PM0 PM1 CM0 CM1 HR0 AIER PRCR HR1 OCD WDTR WDTS WDC RMAD0
0016 0016 011010002 001000002 0016 XXXXXX002 00XXX0002 4016 000001002 XX16 XX16 000XXXXX2 0016 0016 X016 0016 0016 X016
Address match interrupt register 1
RMAD1
Voltage detection register 1 2 Voltage detection register 2 2
VCR1 VCR2
0016 XXX0000016
INT0 input filter select register Voltage detection interrupt register 2
INT0F D4INT
XXXXX0002 0016 3
010000012 4
X : Undefined Blank columns are all reserved space. No access is allowed. Notes: 1. Software reset or the watchdog timer reset does not affect bits 0 to 1 of PM0 register. 2. Software reset or the watchdog timer reset does not affect this register. 3. Owing to Reset input. 4. In the case of RESET pin = "H" retaining.
Rev.1.20
Oct.31.2003
page 10 of 26
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
4. Special Function Register (SFR)
Address 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16 006016 006116 006216 006316 006416 006516 006616 006716 006816 006916 006A16 006B16 006C16 006D16 006E16 006F16 007016 007116 007216 007316 007416 007516 007616 007716 007816 007916 007A16 007B16 007C16 007D16 007E16 007F16
Register
Symbol
After reset
Key input interrupt control register A-D conversion interrupt control register
Compare 1 interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register
KUPIC ADIC CMP1IC S0TIC S0RIC S1TIC S1RIC INT2IC TXIC TYIC TZIC INT1IC INT3IC TCIC CMP0IC INT0IC
XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XX00X0002
INT2 interrupt control register Timer X interrupt control register Timer Y interrupt control register Timer Z interrupt control register INT1 interrupt control register INT3 interrupt control register Timer C interrupt control register
Compare 0 interrupt control register
INT0 interrupt control register
X : Undefined Blank columns are all reserved space. No access is allowed.
Rev.1.20
Oct.31.2003
page 11 of 26
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
Register Timer Y, Z mode register Prescaler Y Timer Y secondary Timer Y primary Timer Y, Z waveform output control register Prescaler Z Timer Z secondary Timer Z primary Symbol TYZMR PREY TYSC TYPR PUM PREZ TZSC TZPR
4. Special Function Register (SFR)
After reset 0016 FF16 FF16 FF16 0016 FF16 FF16 FF16
Address 008016 008116 008216 008316 008416 008516 008616 008716 008816 008916 008A16 008B16 008C16 008D16 008E16 008F16 009016 009116 009216 009316 009416 009516 009616 009716 009816 009916 009A16 009B16 009C16 009D16 009E16 009F16 00A016 00A116 00A216 00A316 00A416 00A516 00A616 00A716 00A816 00A916 00AA16 00AB16 00AC16 00AD16 00AE16 00AF16 00B016 00B116 00B216 00B316 00B416 00B516 00B616 00B716 00B816 00B916 00BA16 00BB16 00BC16 00BD16 00BE16 00BF16
Timer Y, Z output control register Timer X mode register Prescaler X Timer X register Count source set register Timer C register
TYZOC TXMR PREX TX TCSS TC
0016 0016 FF16 FF16 0016 0016 0016
External input enable register Key input enable register Timer C control register 0 Timer C control register 1 Capture, compare 0 register Compare 1 register
UART0 transmit/receive mode register
INTEN KIEN TCC0 TCC1 TM0 TM1 U0MR U0BRG U0TB U0C0 U0C1 U0RB U1MR U1BRG U1TB U1C0 U1C1 U1RB UCON
0016 0016 0016 0016 XX16 XX16 XX16 XX16 0016 XX16 XX16 XX16 000010002 000000102 XX16 XX16 0016 XX16 XX16 XX16 000010002 000000102 XX16 XX16 0016
UART0 bit rate generator UART0 transmit buffer register
UART0 transmit/receive control register 0 UART0 transmit/receive control register 1
UART0 receive buffer register
UART1 transmit/receive mode register
UART1 bit rate generator UART1 transmit buffer register
UART1 transmit/receive control register 0 UART1 transmit/receive control register 1
UART1 receive buffer register
UART transmit/receive control register 2
X : Undefined Blank columns are all reserved space. No access is allowed.
Rev.1.20
Oct.31.2003
page 12 of 26
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
4. Special Function Register (SFR)
Address
00C016 00C116 00C216 00C316 00C416 00C516 00C616 00C716 00C816 00C916 00CA16 00CB16 00CC16 00CD16 00CE16 00CF16 00D016 00D116 00D216 00D316 00D416 00D516 00D616 00D716 00D816 00D916 00DA16 00DB16 00DC16 00DD16 00DE16 00DF16 00E016 00E116 00E216 00E316 00E416 00E516 00E616 00E716 00E816 00E916 00EA16 00EB16 00EC16 00ED16 00EE16 00EF16 00F016 00F116 00F216 00F316 00F416 00F516 00F616 00F716 00F816 00F916 03FA16 00FB16 00FC16 00FD16 00FE16 00FF16
Register A-D register
Symbol AD
After reset XX16 XX16
A-D control register 2 A-D control register 0 A-D control register 1
ADCON2 ADCON0 ADCON1
0016 00000XXX2 0016
Port P0 register Port P1 register Port P0 direction register Port P1 direction register Port P3 register Port P3 direction register Port P4 register Port P4 direction register
P0 P1 PD0 PD1 P3 PD3 P4 PD4
XX16 XX16 0016 0016 XX16 0016 XX16 0016
Pull-up control register 0 Pull-up control register 1 Port P1 drivability control register Timer C output control register
PUR0 PUR1 DRR TCOUT
00XX00002 XXXXXX0X2 0016 0016
01B316 01B416 01B516 01B616 01B716
Flash memory control register 4 Flash memory control register 1 Flash memory control register 0
FMR4 FMR1 FMR0
0100000X2 0100XX0X2 XX0000012
X : Undefined Blank columns are all reserved space. No access is allowed.
Rev.1.20
Oct.31.2003
page 13 of 26
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
5. Electrical Characteristics
5. Electrical Characteristics
Table 5.1 Absolute Maximum Ratings
Symbol
VCC AVCC VI VO Pd Topr Tstg Supply voltage Analog supply voltage Input voltage Output voltage Power dissipation Operating ambient temperature Storage temperature Topr=25 C
Parameter
Condition
VCC=AVCC VCC=AVCC
Rated value
-0.3 to 6.5 -0.3 to 6.5 -0.3 to VCC+0.3 -0.3 to VCC+0.3 300 -20 to 85 / -40 to 85 (D version) -65 to 150
Unit
V V V V mW C C
Table 5.2 Recommended Operating Conditions
Symbol
VCC AVcc Vss AVss VIH VIL I OH (sum) I OH (peak) I OH (avg) I OL (sum) I OL (peak)
Parameter
Supply voltage Analog supply voltage Supply voltage Analog supply voltage "H" input voltage "L" input voltage Sum of all pins' IOH "H" peak all output currents (peak) "H" peak output current "H" average output current Sum of all pins' IOL "L" peak all output currents (peak) "L" peak output Except P10 to P17 current P10 to P17 "L" average output current Except P10 to P17 P10 to P17
Conditions
Min.
2.7
Standard Typ.
5.0 VCC 0 0
Max.
5.5
Unit
V V V V
0.8VCC 0
VCC 0.2VCC -60.0 -10.0 -5.0 60 10
V V mA mA mA mA mA mA mA mA mA mA MHz MHz
Drive ability HIGH Drive ability LOW
30 10 5 15 5 20 10
I OL (avg)
f (XIN)
Drive ability HIGH Drive ability LOW Main clock input oscillation frequency 3.0V Vcc 5.5V 2.7V Vcc < 3.0V
0 0
Note 1: Referenced to VCC = AVCC = 2.7 to 5.5V at Topr = -20 to 85 C / -40 to 85 C unless otherwise specified. 2: The mean output current is the mean value within 100ms.
Rev.1.20
Oct.31.2003
page 14 of 26
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
5. Electrical Characteristics
Table 5.3 A-D Conversion Characteristics
Symbol
- - Resolution
Parameter Absolute accuracy
Measuring condition
Vref =VCC
Standard Unit Min. Typ. Max.
10 3 2 5 2 10 3.3 2.8 2.0 0 0.25 1.0 VCC Vref 10 40 Bit LSB LSB LSB LSB k s s V V MHz
10 bit mode 8 bit mode 10 bit mode 8 bit mode
f(XIN)=oAD=10 MHz, Vref=Vcc=5.0V f(XIN)=oAD=10 MHz, Vref=Vcc=5.0V f(XIN)=oAD=10 MHz, Vref=Vcc=3.3V f(XIN)=oAD=10 MHz, Vref=Vcc=3.3V
RLADDER tCONV VREF VIA -
Ladder resistance Conversion time Reference voltage Analog input voltage
VREF=VCC
10 bit mode 8 bit mode
f(XIN)=oAD=10 MHz, Vref=Vcc=5.0V f(XIN)=oAD=10 MHz, Vref=Vcc=5.0V
10 MHz Note 1: Referenced to VCC=AVCC=2.7 to 5.5V at Topr = -20 to 85 C / -40 to 85 C unless otherwise specified. 2: When fAD is 10 MHz more, divide the fAD and make A-D operation clock frequency (OAD) lower than 10 MHz. 3: When the Vcc is less than 4.2V, divide the fAD and make A-D operation clock frequency (OAD) lower than fAD/2.
A-D operation Without sample & hold clock frequency2 With sample & hold
Table 5.4 Flash Memory Version Electrical Characteristics
Symbol
- - - - -
Parameter
Byte program time Block erase time Program, Erase Voltage Read Voltage Program, Erase Temperature
Measuring condition
Min.
Standard Typ.
75 400
Max
TBD TBD 5.5 5.5 60
Unit
s ms V V C
2.7 2.7 0
Note 1: Referenced to VCC1=AVcc=2.7 to 5.5V at Topr = 0 to 60 C unless otherwise specified.
Table 5.5 Voltage Detection Circuit Electrical Characteristics
Symbol
Vdet4 Voltage detection level Voltage detection interrupt request generating time2 Voltage detection circuit self consumption current td(E-A) Waiting time till voltage detection circuit operation starts3 VC27="1"
Parameter
Measuring condition
Min.
3.3
Standard Typ.
3.8 40 TBD
Max.
4.3
Unit
V V V
20
V
Note 1: The measureing condition is Vcc=AVcc=5.0 V and Topr=25 C. 2: This shows the time till the voltage detection interrupt request is generated since the voltage passes Vdet. 3: This shows the required time till the voltage detection circuit operates when setting to "1" again.
Rev.1.20
Oct.31.2003
page 15 of 26
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
5. Electrical Characteristics
Table 5.6 Power-on Reset Circuit Electrical Characteristics
Symbol Parameter
Power-on reset start time2 Power-on reset cancel operation start voltage Hardware reset 2 cancel operation start voltage Supply start up condition when using power-on reset circuit Intergradation time to 0V<2.7V Vcc<0.5V
Measuring condition
Min.
TBD 3.3 3.3
Standard Typ.
3.8 3.8
Max.
4.3 4.3 TBD
Unit
ms V V ms
Note 1: The measuring condition is Vcc=AVcc=5.0 V and Topr=25 C. 2: Keep Vcc<0.5V for over regulated time to execute the reset operation.
Table 5.7 High-speed Ring Oscillator Circuit Electrical Characteristics
Symbol Parameter
Settable high-speed ring oscillator minimum period High-speed ring oscillator adjusted unit
Measuring condition
Set "0016" in the HR1 register Differences when setting "0116" and "0016" in the HR register
Min.
Standard Typ.
TBD 1
Max.
Unit
ns ns
Note 1: The measuring condition is Vcc=AVcc=5.0 V and Topr=25 C.
Table 5.8 Power Circuit Timing Characteristics
Symbol
td(P-R) td(R-S)
Parameter
Time for internal power supply stabilization during powering-on2 STOP release time3
Measuring condition
Min.
Standard Typ.
Max.
2 150
Unit
ms s
Note 1: The measuring condition is Vcc=AVcc=2.7 to 5.0 V and Topr=25 C. 2: This shows the wait time untill the internal power supply generating circuit is stabilized during power-on. 3: This shows the time till BCLK starts from the interrupt acknowledgement to cancel stop mode.
Rev.1.20
Oct.31.2003
page 16 of 26
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
5. Electrical Characteristics
P0 P1 P2 P3 P4 30pF
Figure 5.1 Port P0 to P4 measurement circuit
Rev.1.20
Oct.31.2003
page 17 of 26
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
5. Electrical Characteristics
Table 5.9 Electrical Characteristics (1)
Symbol
"H" output voltage VOH XOUT "L" output voltage VOL P10 to P17 Except XOUT P10 to P17
[Vcc=5V]
Measuring condition
IOH=-5mA IOH=-200A Drive ability HIGH Drive ability LOW IOH= 5 mA IOH= 200 A Drive ability HIGH Drive ability LOW Drive ability HIGH Drive ability LOW IOH= 10 mA IOH= 5 mA IOH= 1 mA IOH=500A 0.2 IOH=-1 mA IOH=-500A
Parameter
Except XOUT
Min.
VCC-2.0 VCC-0.3 VCC-2.0 VCC-2.0
Standard Typ. Max.
VCC VCC VCC VCC 2.0 0.45 2.0 2.0 2.0 2.0 1.0
Unit
V V V V V V V V V V V
XOUT VT+-VTHysteresis INT0, INT1, INT2, INT3, KI0, KI1, KI2, KI3, CNTRo, CNTR1, TCIN, RxD0, RxD1 RESET IIH IIL RPULLUP RfXIN fRING-S VRAM "H" input current "L" input current Pull-up resistance XIN Feedback resistance Low-speed ring oscillator frequency RAM retention voltage
0.2 VI=5V VI=0V VI=0V 30 40 At stop mode 2.0 50 1.0 125
2.2 5.0
V A A k M kHz V
-5.0
167 250
Note 1 : Referenced to VCC=AVCC=4.2 to 5.5V at Topr = -20 to 85 C / -40 to 85 C, f(BCLK)=20MHz unless otherwise specified.
Rev.1.20
Oct.31.2003
page 18 of 26
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
5. Electrical Characteristics
Table 5.10 Electrical Characteristics (2)
Symbol Parameter
[Vcc=5V]
Measuring condition
High-speed mode
XIN=20 MHz (square wave) High-speed ring oscillator off Low-speed ring oscillator on=125 kHz No division XIN=16 MHz (square wave) High-speed ring oscillator off Low-speed ring oscillator on=125 kHz No division XIN=10 MHz (square wave) High-speed ring oscillator off Low-speed ring oscillator on=125 kHz No division XIN=20 MHz (square wave) High-speed ring oscillator off Low-speed ring oscillator on=125 kHz Division by 8 XIN=16 MHz (square wave) High-speed ring oscillator off Low-speed ring oscillator on=125 kHz Division by 8 XIN=10 MHz (square wave) High-speed ring oscillator off Low-speed ring oscillator on=125 kHz Division by 8 Main clock off High-speed ring oscillator on=8 MHz Low-speed ring oscillator on=125 kHz No division Main clock off High-speed ring oscillator on=8 MHz Low-speed ring oscillator on=125 kHz Division by 8 Main clock off High-speed ring oscillator off Low-speed ring oscillator on=125 kHz Division by 8 Main clock off High-speed ring oscillator off Low-speed ring oscillator on=125 kHz When a WAIT instruction is executed2 Peripheral clock operation Main clock off High-speed ring oscillator off Low-speed ring oscillator on=125 kHz When a WAIT instruction is executed2 Peripheral clock off Main clock off High-speed ring oscillator off Low-speed ring oscillator off CM10="1" Peripheral clock off VC27="0"
Min.
Standard Typ.
9
Max.
15
Unit
mA
8
14
mA
5
mA
Medium-speed mode
4
mA
3
mA
ICC
Power supply current (VCC=3.3 to 5.5V) In single-chip mode, the output pins are open and other pins are VSS High-speed ring oscillator mode
2
mA
4
8
mA
1.5
mA
Low-speed ring oscillator mode Wait mode
0.4
2.0
mA
40
80
A
Wait mode
38
76
A
Stop mode
0.8
3.0
A
Note 1: The power supply current measuring is executed using the measuring program on frash memory. 2: Timer Y is operated with timer mode.
Rev.1.20
Oct.31.2003
page 19 of 26
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
5. Electrical Characteristics
Timing requirements (Unless otherwise noted: VCC = 5V, VSS = 0V at Ta = 25 C) [VCC=5V]
Table 5.11 XIN input Symbol tC(XIN) tWH(XIN) tWL(XIN) Parameter Standard Min. Max. 62.5 30 30 Unit ns ns ns
XIN input cycle time XIN input HIGH pulse width XIN input LOW pulse width
________
Table 5.12 CNTR0 input, CNTR1 input, INT2 input Symbol Parameter tC(CNTR0) tWH(CNTR0) tWL(CNTR0) CNTR0 input cycle time CNTR0 input HIGH pulse width CNTR0 input LOW pulse width
Standard Min. Max. 100 40 40
Unit ns ns ns
________
Table 5.13 TCIN input, INT3 input Symbol Parameter Standard Min. Max. Unit ns ns ns
tC(TCIN) 400 1 TCIN input cycle time tWH(TCIN) 200 2 TCIN input HIGH pulse width tWL(TCIN) 200 2 TCIN input LOW pulse width Note 1 : Use the greater value,either ( 1/ digital filter clock frequency x 6) or min. value. 2 : Use the greater value,either ( 1/ digital filter clock frequency x 3) or min. value. Table 5.14 Serial I/O Symbol tC(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Parameter CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time
________
Standard Min. Max. 200 100 100 80 0 35 90
Unit ns ns ns ns ns ns ns
Table 5.15 External interrupt INT0 input Symbol tW(INH) tW(INL)
________
Parameter INT0 input HIGH pulse width ________ INT0 input LOW pulse width
Standard Max. Min.
250 1 250 2
Unit ns ns
Note ________ ________ 1 : When the INT0 input filter select bit selects the digital filter, use the INT0 input HIGH pulse width to the greater value,either ( 1/ digital filter clock frequency x 3) or min. value. ________ ________ 2 : When the INT0 input filter select bit selects the digital filter, use the INT0 input LOW pusle width to the greater value,either ( 1/ digital filter clock frequency x 3) or min. value.
Rev.1.20
Oct.31.2003
page 20 of 26
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
5. Electrical Characteristics
VCC = 5V
tc(CNTR0) tWH(CNTR0) CNTR0 input tWL(CNTR0)
tc(TCIN) tWH(TCIN) TCIN input tWL(TCIN) tc(XIN) tWH(XIN) XIN input tWL(XIN)
tc(CK) tW(CKH) CLKi tW(CKL) th(C-Q) TxDi td(C-Q) RxDi tW(INL) INTi tW(INH) tsu(D-C) th(C-D)
Figure 5.2 Vcc=5V timing diagram
Rev.1.20
Oct.31.2003
page 21 of 26
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
5. Electrical Characteristics
Table 5.16 Electrical Characteristics (3)
Symbol
"H" output voltage VOH "L" output voltage VOL
[Vcc=3V]
Measuring condition
IOH=-1mA Drive ability HIGH Drive ability LOW IOH= 1 mA Drive ability HIGH Drive ability LOW Drive ability HIGH Drive ability LOW IOH= 2 mA IOH= 1 mA IOH= 0.1 mA IOH=50 A 0.2 IOH=-0.1 mA IOH=-50 A
Parameter
Except XOUT XOUT P10 to P17 Except XOUT P10 to P17 XOUT
Min.
VCC-0.5 VCC-0.5 VCC-0.5
Standard Typ. Max.
VCC VCC VCC 0.5 0.5 0.5 0.5 0.5 0.8
Unit
V V V V V V V V V
VT+-VT-
Hysteresis
INT0, INT1, INT2, INT3, KI0, KI1, KI2, KI3, CNTRo, CNTR1, TCIN, RxD0, RxD1 RESET VI=3V VI=0V VI=0V XIN
0.2
IIH IIL RPULLUP RfXIN fRING-S VRAM
"H" input current "L" input current Pull-up resistance Feedback resistance
Low-speed ring oscillator frequency
1.8 4.0
V A A k M kHz V
-4.0
66 40 160 3.0 125 250 500
RAM retention voltage
At stop mode
2.0
Note 1 : Referenced to VCC=AVCC=2.7 to 3.3V at Topr = -20 to 85 C / -40 to 85 C, f(BCLK)=10MHz unless otherwise specified.
Rev.1.20
Oct.31.2003
page 22 of 26
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
5. Electrical Characteristics
Table 5.17 Electrical Characteristics (4)
Symbol Parameter
[Vcc=3V]
Measuring condition
High-speed mode
XIN=20 MHz (square wave) High-speed ring oscillator off Low-speed ring oscillator on=125 kHz No division XIN=16 MHz (square wave) High-speed ring oscillator off Low-speed ring oscillator on=125 kHz No division XIN=10 MHz (square wave) High-speed ring oscillator off Low-speed ring oscillator on=125 kHz No division XIN=20 MHz (square wave) High-speed ring oscillator off Low-speed ring oscillator on=125 kHz Division by 8 XIN=16 MHz (square wave) High-speed ring oscillator off Low-speed ring oscillator on=125 kHz Division by 8 XIN=10 MHz (square wave) High-speed ring oscillator off Low-speed ring oscillator on=125 kHz Division by 8 Main clock off High-speed ring oscillator on=8 MHz Low-speed ring oscillator on=125 kHz No division Main clock off High-speed ring oscillator on=8 MHz Low-speed ring oscillator on=125 kHz Division by 8 Main clock off High-speed ring oscillator off Low-speed ring oscillator on=125 kHz Division by 8 Main clock off High-speed ring oscillator off Low-speed ring oscillator on=125 kHz When a WAIT instruction is executed2 Peripheral clock operation Main clock off High-speed ring oscillator off Low-speed ring oscillator on=125 kHz When a WAIT instruction is executed2 Peripheral clock off Main clock off High-speed ring oscillator off Low-speed ring oscillator off CM10="1" Peripheral clock off VC27="0"
Min.
Standard Typ.
8
Max.
13
Unit
mA
7
12
mA
5
mA
Medium-speed mode
3
mA
2.5
mA
ICC
Power supply current (VCC=2.7 to 3.3V) In single-chip mode, the output pins are open and other pins are VSS High-speed ring oscillator mode
1.6
mA
3.5
7.5
mA
1.5
mA
Low-speed ring oscillator mode Wait mode
0.4
2.0
mA
37
74
A
Wait mode
35
70
A
Stop mode
0.7
3.0
A
Note 1: The power supply current measuring is executed using the measuring program on frash memory. 2: Timer Y is operated with timer mode.
Rev.1.20
Oct.31.2003
page 23 of 26
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
5. Electrical Characteristics
Timing requirements (Unless otherwise noted: VCC = 3V, VSS = 0V at Ta = 25 C) [VCC=3V]
Table 5.18 XIN input Symbol tC(XIN) tWH(XIN) tWL(XIN) Parameter Standard Min. Max. 143 70 70 Unit ns ns ns
XIN input cycle time XIN input HIGH pulse width XIN input LOW pulse width
________
Table 5.19 CNTR0 input, CNTR1 input, INT2 input Symbol Parameter tC(CNTR0) tWH(CNTR0) tWL(CNTR0) CNTR0 input cycle time CNTR0 input HIGH pulse width CNTR0 input LOW pulse width
Standard Min. Max. 300 120 120
Unit ns ns ns
________
Table 5.20 TCIN input, INT3 input Symbol Parameter Standard Min. Max. Unit ns ns ns
tC(TCIN) 1200 1 TCIN input cycle time tWH(TCIN) 600 2 TCIN input HIGH pulse width tWL(TCIN) 600 2 TCIN input LOW pulse width Note 1 : Use the greater value,either ( 1/ digital filter clock frequency x 6) or min. value. 2 : Use the greater value,either ( 1/ digital filter clock frequency x 3) or min. value. Table 5.21 Serial I/O Symbol tC(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Parameter CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time
________
Standard Min. Max. 300 150 150 160 0 55 90
Unit ns ns ns ns ns ns ns
Table 5.22 External interrupt INT0 input Symbol tW(INH) tW(INL)
________
Parameter INT0 input HIGH pulse width ________ INT0 input LOW pulse width
Standard Max. Min.
380 1 380 2
Unit ns ns
Note ________ ________ 1 : When the INT0 input filter select bit selects the digital filter, use the INT0 input HIGH pulse width to the greater value,either ( 1/ digital filter clock frequency x 3) or min. value. ________ ________ 2 : When the INT0 input filter select bit selects the digital filter, use the INT0 input LOW pusle width to the greater value,either ( 1/ digital filter clock frequency x 3) or min. value.
Rev.1.20
Oct.31.2003
page 24 of 26
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
5. Electrical Characteristics
VCC = 3V
tc(CNTR0) tWH(CNTR0) CNTR0 input tWL(CNTR0)
tc(TCIN) tWH(TCIN) TCIN input tWL(TCIN) tc(XIN) tWH(XIN) XIN input tWL(XIN)
tc(CK) tW(CKH) CLKi tW(CKL) th(C-Q) TxDi td(C-Q) RxDi tW(INL) INTi tW(INH) tsu(D-C) th(C-D)
Figure 5.3 Vcc=3V timing diagram
Rev.1.20
Oct.31.2003
page 25 of 26
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
R8C/11 Group
Package Dimensions
Package Dimensions
32P6U-A
MMP
JEDEC Code - HD D
32 25
Plastic 32pin 77mm body LQFP
Weight(g) Lead Material Cu Alloy e MD
EIAJ Package Code LQFP32-P-0707-0.80
I2
1 24
Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 Lp
A3
8
17
9
16
E HE
A
L1 A2
A3
e
F
A1
L
Lp
b
c
x y b2 I2 MD ME
x
M
y
Detail F
Rev.1.20
Oct.31.2003
page 26 of 26
b2
Dimension in Millimeters Min Nom Max - - 1.7 0.1 0.2 0 - - 1.4 0.32 0.37 0.45 0.105 0.125 0.175 6.9 7.0 7.1 6.9 7.0 7.1 0.8 - - 8.8 9.0 9.2 8.8 9.0 9.2 0.3 0.5 0.7 1.0 - - 0.45 0.6 0.75 - 0.25 - - - 0.2 0.1 - - 0 10 - 0.5 - - 1.0 - - 7.4 - - - - 7.4
ME
REVISION HISTORY
Rev. Date Page 1.00 Jun. 19, 2003 1.10 Sep. 08, 2003 2 5 6 10 12 14 2 6 11 14 15 17 19 First edition issued
R8C/11 Group Data Sheet
Description Summary
Table 1.1: Shortest instruction execution time ____________ changed and f(XIN) Figure 1.3: Pin name changed from TXOUT to____________ CNTR0 Table 1.3: Pin name changed from TXOUT to CNTR0 The value of HR1 register after reset changed The value of TC register after reset changed Chapter "5. Electrical Characteristics" added Table 1.1: Power consumption values added Table 1.3: Resistor value for CNVss and MODE deleted Register name of address 005016 modified from CMP2IC to CMP1IC, register name of address 005C16 modified from CMP1IC to CMP0IC Table 5.2: Note 3 and Note 4 deleted tsamp in Table 5.3 deleted Figure 5.1 added Table 5.10: Vcc changed from "4.2 to 5.5V" to "3.3V to 5.5V", low-power ring oscillator changed from "on 100kHz" to "125kHz", XIN=5MHz deleted and XIN=10MHz added in high-speed mode and medium-speed mode, VC27="0" added in stop mode measuring condition, data added and modified Table 11 to Table 15 added Figure 5.2 added Table 5.16: Note 1, f(BCLK)=5 MHz changed to 10 MHz Table 5.17: low-power ring oscillator changed from "on 100kHz" to "125kHz", XIN=5MHz deleted and XIN=10MHz added in high-speed mode and medium-speed mode, VC27="0" added in stop mode measuring condition, data added and modified Table 5.18 to Table 5.22 added Figure 5.3 added
1.20 Oct. 31, 2003
20 21 22 23
24 25
A-1
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