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Flash Application Design Guidelines
ADE-603-010A Rev. 2.0 12/5/00 Hitachi, Ltd.
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Preface
This document presents flash application guidelines, including points requiring special attention, for developing systems using Hitachi AND flash memory.
System design
System amendment
Relevant Sections in Flash Application Design Guidelines Rev. 2.0 Page
NG
Start of system study
Next Step
Hitachi AND Flash Write Commands (List of Program Functions, Areas Subject to Programming, Programming Example) Concept of Number of Rewrites Sample SH Interface
: P1 to P4
: P11, P12 : P13 to P16
NG
Start of system design
Next Step
Hitachi AND Flash Write Commands Error Handling and Bad Sector Processing (Errors during reading, erasing, and writing) Sample SH Interface (Input Waveforms) Power Shutdown Processing
: P3 to P5 : P6 to P10 : P17 to P20 : P24, P25
NG
Start of system evaluation
Next Step
Hitachi AND Flash Write Commands Error Handling and Bad Sector Processing (Errors during reading, erasing, and writing) Concept of Number of Rewrites Sample SH Interface (Basic Specifications, Overview, Sample Circuit, Input Waveforms) Sample H8S Interface (Operating Mode, Control Method, Sample Circuit, Port Settings, Data Transfer to On-Chip RAM) Power Shutdown Processing
: P1 to P5 : P6 to P10 : P11, P12 : P13 to P20
: P20 to P22
: P24, P25
NG
Data Sheet check Next Step
Data Sheet
: Next page
Contact Hitachi representative
OK
Please contact a Hitachi representative in the event of problems relating to flash memory. Early diagnosis is vital for solving problems.
Rev. 2.0, 12/00, page iii of 6
Data Sheet pages for reference during the design of a system using Hitachi AND flash memory are shown below.
System design System amendment Pin functions NG Mode setting NG Pin arrangement NG Absolute maximum ratings Capacitance NG Command descriptions State transitions NG Mode descriptions NG Reading Auto-erase Auto-program Status register read Product ID read Data recovery read/write Serial read Single-sector erase Programming Product ID code read Data recovery read/write : P10 : P10 : P10 : P11 : P11 : P12 : P13 : P13 : P14, 15 : P15 : P15 P8, 9 P17 P3 P7 Relevant section and page in HN29W25611 Series Data Sheet ADE-203-1178A Rev. 1.0 P6
NG
P17
NG
P16
NG
Command/address/ data input order
Function descriptions NG DC characteristics NG AC characteristics NG
P36
P18
Test conditions Parameters Power-on/off, serial mode Program, erase, and erase-verify Timing waveforms Power-on/off Serial read Erase and status data polling Program and status polling Product ID and status register Data recovery read/write Clear status register Spec for system use Handling of invalid sectors Securing system reliability
: P18 : P19, 20 : P21, 22 : P23 : P24, 25 : P25 : P26 to 31 : P32 : P33, 34 : P35
NG
Concerning system use
: P36 : P37 : P38
OK
Rev. 2.0, 12/00, page iv of 6
Contents
1. Hitachi AND Flash Write Commands .......................................................... 2. Error Handling and Bad Sector Processing .................................................. 1 6
3. Concept of Number of Rewrites ................................................................... 11 4. Sample Microcomputer Interfaces ................................................................ 13 5. Power Shutdown Recovery Method ............................................................. 24 6 Examples of Sector Management Method..................................................... 26 7 8. Some Common Questions ............................................................................. 34 Check List ..................................................................................................... 46
Rev. 2.0, 12/00, page v of 6
Rev. 2.0, 12/00, page vi of 6
1.
1.1 Overview
Hitachi AND Flash Write Commands
This section describes the differences between the four kinds of auto-program commands, Program (1) to Program (4). Programming operations can be broadly classified into the following three kinds: * Additional write Performs additional writing to arbitrary bytes in the erased state (FFH) within a sector. (Program1, Program3) * Write Performs writing to a sector in the erased state. (Program2) * Rewrite Rewrites data regardless of the write target byte data. (Program4)
Rev. 2.0, 12/00, page 1 of 46
1.2
List of Hitachi AND Flash Program Functions
Target Area (Column Address CA Range) Data area (CA0 to CA2047) + Control area (CA2048 to CA2111) Column Address Yes
Program No. Program(1) Additional write
Function
Figure No.
Figure 1.2 * Performs additional writes starting at byte indicated by input column address. * Additional writes are possible on unwritten (FFH) bytes. * FFH is input for bytes on which writes are not performed. * Performs additional writes on sector. * Additional writes are possible on unwritten (FFH) bytes. * FFH is input for bytes on which writes are not performed. * Performs additional writes on sectors in erased state (all FFH). * FFH is input for bytes on which writes are not performed. * Performs additional writes on control area. * Additional writes are possible on unwritten (FFH) bytes. * FFH is input for bytes on which writes are not performed. Figure 1.3
No
Program(2) Write
Data area (CA0 to CA2047) + Control area (CA2048 to CA2111) Control area (CA2048 to CA2111)
No
Figure 1.4
Program(3) Control area additional write
No
Figure 1.5
Program(4) Rewrite
Data area (CA0 to CA2047) + Control area (CA2048 to CA2111)
Yes
Figure 1.6 * Performs rewrites starting at byte indicated by input column address. * Rewrites with input data (including FFH data). Figure 1.7 * Performs rewrites on sector. * Rewrites with input data (including FFH data).
No
Notes on Use of Additional Writes * As additional writes by Program(1) and Program(3) are also counted in the number of rewrites, the stipulated number of rewrites should not be exceeded. For the method of counting rewrites, see section 3, Concept of Number of Rewrites. * Additional rewrites are performed in byte units.
Rev. 2.0, 12/00, page 2 of 46
1.3
Areas Subject to Hitachi AND Flash Programming
* Program(1) without CA * Program(2) * Program(4) without CA (Sector) Memory array 16383 * Program(1) with CA * Program(4) with CA (Sector) Memory array 16383 * Program(3)
(Sector) Memory array 16383
Sector address
Sector address
Sector address
0 0 Register 0 2111 2111 (Column)
0 0 Register 0 Column address 2111 2111 (Column)
0 0 Register 0 2048 2111 2048 2111
Figure 1.1 Areas Subject to Hitachi AND Flash Programming
1.4
Examples of Use of Hitachi AND Flash Program Modes
Examples of the use of the various program modes are shown below. 1. Program(1) with CA (additional write) Writes are performed on bytes with a value of FFH. (Byte-unit additional writes) Note: When FFH is input, the result is no change to the existing stored data.
Memory cell data before writing Write data from outside Buffer data in actual writes 0 2111 (Column address) 10 20 30 40 FF FF FF FF 50 60 70 80 FF FF FF FF 90 A0 B0 C0 FF FF ... FF (Data) 10 20 30 40 FF FF FF FF 50 60 70 80 No data 10 20 30 40 10 20 30 40 50 60 70 80 50 60 70 80 90 A0 B0 C0 FF FF ... FF
Figure 1.2 Program Mode Example 1 2. Program(1) without CA (additional write)
Memory cell data before writing Write data from outside Buffer data in actual writes 0 2111 (Column address) 10 20 30 40 FF FF FF FF 50 60 70 80 FF FF FF FF 90 A0 B0 C0 FF FF ... FF (Data) FF FF FF FF 10 20 30 40 FF FF FF FF 50 60 70 80 No data 10 20 30 40 10 20 30 40 50 60 70 80 50 60 70 80 90 A0 B0 C0 FF FF ... FF
Figure 1.3 Program Mode Example 2
Rev. 2.0, 12/00, page 3 of 46
3. Program(2) (write for pre-erased sectors) Writing is performed on sectors in the erased state. Note: When FFH is input, the result is no change to the existing stored data.
Memory cell data before writing Write data from outside Buffer data in actual writes 0 2111 (Column address) FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ... FF (Data) FF FF FF FF 10 20 30 40 FF FF FF FF 50 60 70 80 No data FF FF FF FF 10 20 30 40 FF FF FF FF 50 60 70 80 FF FF FF FF FF FF ... FF
Figure 1.4 Program Mode Example 3 4. Program(3) (additional write to control area) Writing is performed on bytes with a value of FFH in the control area. Note: When FFH is input, the result is no change to the existing stored data.
Memory cell data before writing Write data from outside Buffer data in actual writes 0 2048 2111 (Column address) 10 20 30 40 ... 20 30 40 50 60 70 80 FF FF FF FF 90 A0 B0 C0 FF FF ... FF (Data) FF FF FF FF 50 60 70 80 No data 10 20 30 40 ... 20 30 40 50 60 70 80 50 60 70 80 90 A0 B0 C0 FF FF ... FF
Figure 1.5 Program Mode Example 4 5. Program(4) with CA (rewrite) Performs rewriting. Addresses for which data has been entered from outside are rewritten. (FFH data rewriting is also performed.)
0 2111 (Column address) 10 20 30 40 FF FF FF FF 50 60 70 80 FF FF FF FF 90 A0 B0 C0 FF FF ... FF (Data) 50 60 70 80 10 20 30 40 FF FF FF FF 50 60 70 80 No data 50 60 70 80 10 20 30 40 FF FF FF FF 50 60 70 80 90 A0 B0 C0 FF FF ... FF
Memory cell data before writing Write data from outside Buffer data in actual writes
Figure 1.6 Program Mode Example 5 6. Program(4) without CA (rewrite)
0 2111 (Column address) 10 20 30 40 FF FF FF FF 50 60 70 80 FF FF FF FF 90 A0 B0 C0 FF FF ... FF (Data) 50 60 70 80 10 20 30 40 FF FF FF FF 50 60 70 80 No data 50 60 70 80 10 20 30 40 FF FF FF FF 50 60 70 80 90 A0 B0 C0 FF FF ... FF
Memory cell data before writing Write data from outside Buffer data in actual writes
Figure 1.7 Program Mode Example 6
Rev. 2.0, 12/00, page 4 of 46
Conditions for the use of the Program(1) to Program(4) modes are summarized below.
Write execution
Write target sector in erased state? Yes
No
Write target byte in erased state? Yes
No
Write of control bytes only? Yes
No
Program(1) Program(2) Program(3) Program(4) can be used
Program(1) Program(3) Program(4) can be used
Program(1) Program(4) can be used
Program(4) can be used
Figure 1.8 Conditions for Use of Each Program Mode
Rev. 2.0, 12/00, page 5 of 46
2. Error Handling and Bad Sector Processing
A read, erase, or rewrite error may occur when Hitachi AND flash memory is programmed. To secure system reliability, provisions must be made to handle such errors when they occur. The approach to error handling and bad sector processing is outlined below. The most appropriate processing should be incorporated into the system after checking details of flash memory state transitions, status information, etc., in the Data Sheet.
2.1
Errors during Reading
When a data read is performed, the read data may differ from the written data. Therefore, an ECC correction function of 3 or more bits per sector (2 kbytes) should be provided.
ECC Generation when Writing Start Start ECC Check when Reading Start
2-kbyte data preparation
Read data + ECC code
ECC code generation ECC check NG Error correction
OK
Write data + ECC code
End
Write data + ECC code (Rewrite corrected data)
... Flash processing ... Controller processing End
Figure 2.1 Example of Read Error Handling
Rev. 2.0, 12/00, page 6 of 46
2.2
Errors during Erasing
The main points for attention when an error occurs during erasing are given below. (1) Factory shipped bad sectors, or sectors that have become bad due to erasing or writing, should not be erased or written. (2) Carry out a good sector code check before writing or erasing. One option may be to create a check table in which such sectors are recorded. (3) Data in a sector in which an error has occurred during erasing will be undefined, and meaningless data will be returned if the sector is read. (4) If an error occurs, record the bad sector, and then issue a Clear Status Register command and restore the flash memory to the state in which commands can be received.
Start
Read good sector code
Code check Good sector Erase
Bad sector
Record bad sector
End
Ready/Busy Ready
Busy
Status read OK
NG
Record bad sector
Clear status register
... Flash processing End ... Controller processing
Figure 2.2 Example of Erase Error Handling
Rev. 2.0, 12/00, page 7 of 46
2.3
Errors during Writing
The main points for attention when an error occurs during writing are given below. (1) Factory shipped bad sectors, or sectors that have become bad due to erasing or writing, should not be erased or written. (2) Carry out a good sector code check before writing or erasing. One option may be to create a check table in which such sectors are recorded. (3) Error confirmation can be achieved by performing a status register read after writing. (4) Data in a sector in which a write error has occurred will be indeterminate, and should not be used for rewriting to a spare sector. (5) Any of the following three methods can be used for rewriting. (a) Writing data reloaded from an external buffer (See figure 2.4.) Requires host to maintain data buffer until successful completion of write command. (b) Data recovery read (See figure 2.5.) (c) Data recovery write (See figure 2.6.) (6) Do not perform any further accesses to a sector in which an error has occurred.
Rev. 2.0, 12/00, page 8 of 46
Start
Write
(a) Writing data reloaded from an external buffer (See figure 2.4.) Requires host to maintain data buffer until successful completion of write command. (b) Data recovery read (See figure 2.5.) (c) Data recovery write (See figure 2.6.)
Ready/Busy Ready
Busy
Status read OK
NG
Clear status register
(a)
External buffer data load
(b)
Data recovery read
Record bad sector
Record bad sector
Find spare sector
Find spare sector
Write
(c)
Data recovery write
Status read OK
NG
... Flash processing End ... Controller processing
Figure 2.3 Example of Write Error Handling
Rev. 2.0, 12/00, page 9 of 46
Controller (1) NG
Flash
2 kB + ECC
Data buffer (2) Rewrite destination 2 kB + ECC Sector addresses
Figure 2.4 Writing Data Reloaded from an External Buffer
Controller (1) (2) Data buffer (3) Rewrite destination 2 kB + ECC Sector addresses NG 2 kB + ECC Flash
Figure 2.5 Data Recovery Read
Controller (1) NG 2 kB + ECC Data buffer (2) Sector addresses Rewrite destination 2 kB + ECC Flash
Figure 2.6 Data Recovery Write
Rev. 2.0, 12/00, page 10 of 46
3. Concept of Number of Rewrites
3.1 Definition of Number of Rewrites
This is calculated by totaling the number of operations for each process per sector unit (see below). Erase + Write Additional write Rewrite 1.0 1.0 1.0
3.2
Definition of Bad Sector Occurrence Rate [= 1.8(%)]
The probability of a defect occurring when the same sector is rewritten 300,000 times. (See figure 3.1.)
N = Stipulated number of rewrites
Bad sector occurrence rate
1.8%
N Number of rewrites
Figure 3.1 Definition of Bad Sector Occurrence Rate
3.3
Sample Calculation of Number of Spare Sectors
Example: Number of spare sectors needed when the entire area of 98% MGM flash is rewritten 300,000 times Defect rate of 1.8(%) for 300,000 rewrites with total of 16,384 sectors and MGM rate of 98(%) Number of spare sectors needed = 16,384 x 0.98 x 0.018 = 290 (sectors) or more
Rev. 2.0, 12/00, page 11 of 46
3.4
Notes on Number of Rewrites
(1) Do not exceed the stipulated number of rewrites on the same sector. (2) If the stipulated number of rewrites is exceeded, unexpected errors may occur in that sector. (3) Execute processing on the system side to prevent a system crash in the event of such an error.
Rev. 2.0, 12/00, page 12 of 46
4.
4.1
Sample Microcomputer Interfaces
Sample SH Interface
This section shows examples of the interface to a microcomputer. Operation of the sample SH interface circuit has been confirmed with an SH7709. 4.1.1 Basic Specifications
Embedded flash (AND) control is performed from the SH by means of simple flash control logic (TTLIC, GA, etc.). (1) Interfacing is performed via area n (CSn). (2) A register to control the flash pins is provided at an area n (CSn) address (Address: AP). (External ports: CE, WE, CDE, SC) (3) Flash is accessed by area n (CSn) address (Address: AF). (4) 2.5 kbytes of RAM are necessary (5 kbytes recommended) as a buffer for providing a spare sector in the event of a flash memory write or read error.
TTLIC, GA, etc.
RAM
* Minimum requirement: 2.5 kbytes * Can be connected externally
A0 Flash control logic
SH
Data bus
Flash
Figure 4.1 Flash Memory Interface Block Configuration
Rev. 2.0, 12/00, page 13 of 46
4.1.2
Overview
(1) CDE performs command/address switching, and so can be low during polling. (2) CE disables all input (including SC), so is overlapped with WE, SC, etc. (3) Operation is not started by a command not stipulated in the Data Sheet. Ex: 02H, 03H, ... 07H, etc. (4) SC becomes valid after the prescribed procedure. After SA(2) + first access when reading; after SA(2) CDE fall when writing. (5) Polling is performed by I/O7. (R/B not used.)
CPU bus VCC Power on reset Flash VCC RESET
Latch Address Qualifier An to Am, CSn SC R/B D0 to D7 GND I/O0 to I/O7 VSS
Figure 4.2 Flash Memory Interface Block Configuration Description of Blocks * Address Qualifier Selects whether an input value from the data bus is to be latched as a signal for control signal setting, or the latch data is to be held. During the latch data hold period, control signals are output to the flash memory, so command, sector address, or other input is performed from the data bus to the flash memory. * Latch Latches data input from the data bus, and provides the necessary control signal to the flash memory on the basis of that latched data.
Rev. 2.0, 12/00, page 14 of 46
4.1.3
Sample Circuit
Flash Power-on reset Address Qualifier A0 D Q Latch R/B RESET
CPU bus
D
Q
D
Q
D
Q
D7 D6 D5 D4 D3 D2 D1 D0
I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
Figure 4.3 Flash Control Logic Various kinds of processing are performed on the flash memory by combining the states in (1) and (2) below (see section 4.1.4, Input Waveforms, for the flow).
Rev. 2.0, 12/00, page 15 of 46
(1) Address A0 = High & CSn = Low Flash control signals are set in the latch (command setting, sector address setting, data read/write CE, OE, WE, CDE, etc.). Latch Input Signal Name 1) 2) 3) 4) D0 D1 D2 D3 Latch Data 1; 0; 1; 0; 1; 0; 1; 0; (2) Address A0 = Low & CSn = High Latch hold state; command setting and data read/write access executed on the flash memory. Output Signal State WE0 WE WE CDE CDE RD CE CE Fixed high Fixed high Fixed low SC Fixed high Fixed low
WE0 SC
Rev. 2.0, 12/00, page 16 of 46
4.1.4
Input Waveforms
Sample input waveforms in read, program, and erase operations are shown below. * Serial Read * Program * Erase (1) (2) (1) (3) (1) (4)
(1) Command and Address Setting
A0 D0 to D7 01H Com*1 03H SA1*2 SA2*2
SC
Latch set
Command set
Latch set
Address set
Address set
*1 Com flash commands Serial Read: 00H Program2: 1FH Sing Sec Erase: 20H *2 SA1, SA2 sector addresses
Figure 4.4 Example of Timing Waveforms in Command and Address Setting
Rev. 2.0, 12/00, page 17 of 46
(2) Read
A0 D0 to D7 0FH
SC
Data read SB
Data read SB
Data read SB
Data read SB
Latch set
Figure 4.5 Example of Read Timing Waveforms * Read flow
I/O O O O O O O I : O A0 1 1 0 1 0 0 0 : 1 D0 to D7 0FH (Clear) 01H (Com Latch) 00H (Serial Read) 03H (Add Latch) AAH (Sector Add 1) AAH (Sector Add 2) Data (Read Data) : 0FH (Clear)
Rev. 2.0, 12/00, page 18 of 46
(3) Program
Wait
A0 D0 to D7 04H 01H 0FH
Program start SC
Latch set
Data write SB
Data write SB
Latch set
Command set
Status read
Latch set
Figure 4.6 Example of Program Timing Waveforms * Programming flow
I/O O O O O O O O O : O O O A0 1 1 0 1 0 0 1 0 : 1 0 1 D0 to D7 0FH (Clear) 01H (Com Latch) 11H (Program 4) 03H (Add Latch) AAH (Sector Add 1) AAH (Sector Add 2) 04H (SC Latch) DDH (Data Input) : 01H (Com Latch) 40H (Prg Start) (Status Read) 0FH (Clear)
Rev. 2.0, 12/00, page 19 of 46
(4) Erase
Wait
A0 D0 to D7 01H 0FH
Erase start SC
Latch set
Command set
Status read
Latch set
Figure 4.7 Example of Erase Timing Waveforms * Erase flow
I/O O O O O O O O O O A0 1 1 0 1 0 0 1 0 1 D0 to D7 0FH (Clear) 01H (Com Latch) 20H (Single Erase) 03H (Add Latch) AAH (Sector Add 1) AAH (Sector Add 2) 01H (Com Latch) B0H (Erase Start) (Status Read) 0FH (Clear)
4.2
4.2.1
Sample H8S Interface
Operating Mode
Mode 3/EXPE = 0 normal single-chip mode is used.
Rev. 2.0, 12/00, page 20 of 46
4.2.2
Control Method
Control is performed using ports in order to implement simple signal connection and control. Port 1 is used for signal control. Port 2 is used for data input/output.
Port 1 H8S
Control signals
Flash Port 2 Data
Figure 4.8 Control Method 4.2.3 Sample Circuit
P10 P11 P12 P13 P14 P15 P16 P17 OE WE CDE SC CE1 Open RDY /Busy Flash 1 P20 P21 P22 P23 P24 P25 P26 P27 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 RES
H8S/2100
Port 2
Port 1
OE WE CDE SC CE2 RDY /Busy I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 RES Flash 2
Power on reset circuit
Figure 4.9 Sample Circuit
Rev. 2.0, 12/00, page 21 of 46
4.2.4
Port Settings
Port 1 Settings
Port 1 Flash memory Input/output Pull up P10 OE Out Yes P11 WE Out Yes P12 CDE Out Yes P13 SC Out No P14 CE1 Out Yes P15 CE2 Out Yes P16 -- Out Yes P17 RDY/Busy In Yes
Port 2 Settings
Port 2 Flash memory Input/output Pull up P20 I/O0 I/O Yes P21 I/O1 I/O Yes P22 I/O2 I/O Yes P23 I/O3 I/O Yes P24 I/O4 I/O Yes P25 I/O5 I/O Yes P26 I/O6 I/O Yes P27 I/O7 I/O Yes
4.2.5
Data Transfer to On-Chip RAM
If the on-chip RAM capacity is not sufficient for one flash sector of data to be transferred, one sector of data should be divided for transfer as shown in the example below. Example: One sector of data is divided into four parts, which are transferred separately. Taking 2048 + 64 bytes as (512 (data area) + 16 (management area)) x 4 bytes, 528 bytes are transferred at a time.
H8S microcomputer Flash
On-chip RAM
(1) Transfer of 528-byte unit 528 528 528 528
528 (3) Transfer of 528-byte unit
(2) 528-byte data processing
Figure 4.10 Example of Data Transfer
Rev. 2.0, 12/00, page 22 of 46
4.3
Reference Materials
(1) 256-Mbit flash memory (HN29W25611 Series) Data Sheet (2) SH Series Hardware Manual (3) H8S Series Hardware Manual
Rev. 2.0, 12/00, page 23 of 46
5. Power Shutdown Recovery Method
5.1 Internal Circuitry that Executes Erasing/Writing
Figure 5.1 shows the 256-Mbit flash memory circuit configuration and memory cell erase/write operations. Memory cells are linked by a source line, word line, and data line, with each signal line driven by peripheral circuitry. In a write, a charge is injected into the floating gate by setting the word line to positive potential. In an erase, the floating gate charge is discharged by setting the word line to negative potential. When power is shut down, the memory cells themselves in the flash memory are not damaged, but memory cell data may become invalid due to faulty operation of the peripheral circuitry that controls memory cell erasing, writing, etc. (see figure 5.1).
256M flash memory (AND type) Peripheral circuitry
VCC VSS
Word line
Erase/write control circuit
Erase processing Data line Word line
Write processing Word line
Reset IC
Source line Flash memory Word line cell Word line
Source line
Floating gate
Data line
Source line
Floating gate
Data line
e
e
e
e
e
e
Sense amp Data buffer
I/O [7:0]
(b) Flash Memory Erase and Write Operations (Based on 256M Flash Memory)
(a) Image of Flash Memory Circuit Configuration (256M Flash Memory)
Figure 5.1 Flash Memory Circuit Configuration Image and Erase and Write Operations
Rev. 2.0, 12/00, page 24 of 46
5.2
Processing when Power Shutdown Occurs during Erase or Write Operations
If power is shut down during erase or write processing, the following processing should be executed. (1) Execute a reset by activating the RES signal. (The peripheral circuitry will be initialized.) (2) Perform erase/write processing again on any sector in which the data has been corrupted due to erasing/writing when the power shutdown occurred. (3) Read the good sector codes of all sectors, and perform erase/write processing again on any other sectors that have become bad. Note that the processing in (1) and (3) above can be eliminated by connecting an external Reset IC (see figure 5.1). In this case, only the processing in (2) should be carried out.
5.3
When Power Shutdown Occurs during Reset, Read Transfer, or Other Processing
Execute the processing in (1) and (3) above. Note that this processing can be eliminated by connecting an external Reset IC.
5.4
If sectors in which a fault has occurred cannot be restored by means of the above processing, processing should be carried out to prevent use of those sectors in the system.
Rev. 2.0, 12/00, page 25 of 46
6 Examples of Sector Management Method
6.1 Flash Configuration
The flash configuration in the case of a 256-Mbit product is shown in figure 6.1. The (2048 + 64) bytes constituting a sector are divided into four, giving (512 + 16) bytes as the minimum unit of data. In this section, (512 + 16) bytes is called a sector, and (2048 + 64) bytes is called a block. 256-Mbit flash is composed of 16,384 blocks, with each block consisting of four (512 + 16)-byte sectors. For data writing, the Program (4) program command is used. An erase command is only used when erasing data as a block.
(2048 + 64) bytes Block 0 Block 1 Block 2 Block 3 Sector 0 Sector 1 Sector 2 Sector 3
(512 + 16) bytes (512 + 16) bytes (512 + 16) bytes (512 + 16) bytes 4 sectors/block
Block 16382 Block 16383 Total number of blocks: 16,384 Capacity: (2048 + 64) bytes/block
Figure 6.1 Flash Configuration Each sector is composed of a 512-byte data area, ECC bytes, and sector management bytes.
16 bytes ECC + management 16 bytes ECC + management 16 bytes ECC + management 16 bytes ECC + management
512 bytes Data
512 bytes Data
512 bytes Data
512 bytes Data
Rev. 2.0, 12/00, page 26 of 46
6.2
Block Management Method
The block configuration is shown in table 6.1. Table 6.1
Item Bad block recording table Block management table Spare block area (1) Spare block area (2) Data block area
Block Configuration
Number of Blocks Used 1 block 16 blocks Description Stores good/bad block information Manages correspondence between physical block numbers and logical block numbers. Logical block numbers are consecutive Area reserved for bad blocks. For 256-Mbyte flash, from Data Sheet, m = 16,384 x 0.98 x 0.018 290 blocks n blocks 16384 -(m +n +16 +1) Area reserved for initial bad blocks. n = 0 to 328 Area that can be used as data area. For 256Mbyte flash, min = 15,750 blocks, max = 16,078 blocks Stores total number of blocks in data block area
m blocks
Block information
1 block
(1) Bad block recording table This table performs management of good/bad flash blocks. The management information is created when flash formatting is carried out. This data is saved as a backup for the initial good/bad block information. Good/bad information is stored as 1-bit data, and data is held for each physical block.
512 bytess: 4,096 blocks can be recorded 0 1 2 3 4 5 6 ... ... 512
ECC + management
16 bytes
Good block 1
Physical block number
Bad block 1 2 0 3 1 4 1 5 0 6 1 7
1 1
0
Figure 6.2 Block Recording Table
Rev. 2.0, 12/00, page 27 of 46
(2) Block management table This table manages the correspondence between physical block numbers and logical block numbers for usable blocks. The management information is created when flash formatting is carried out. The table is updated whenever a bad block occurs during use. The block information in the block management table is shown in figure 6.3. Two bytes of data are provided for each logical block, holding the physical block number corresponding to the logical block number. The effective capacity information bit indicates whether a logical block corresponds to a data area.
512 bytes: 256 blocks can be recorded
Logical block number
16 bytes ... ... 255
ECC + management
0 0
1 1
2 2
3 3
4 XX
5 5
6 6
XX: Spare block number
Physical block number (14 bits)
Blank Effective capacity information Corresponding physical block present : 0 No corresponding physical block :1
Figure 6.3 Block Management Table (3) Spare block areas The spare block areas are spare areas in the event of a bad block. Figure 6.4 shows the location of each area. The data area is located starting at flash physical block number 0000H. A bad block in the data area is switched to spare block area (1). Starting from the highest physical block number, the bad block recording table, block management table, and spare block areas, are located in that order. When there is a bad block, it is placed in the lower good block. For example, if physical block number 3FFFH is a bad block, the bad block recording table is placed at 3FFEH.
Rev. 2.0, 12/00, page 28 of 46
0000H
Data area
Spare block area (1) Spare block area (2) Block management table Bad block recording table
0 to 328 blocks 290 blocks 16 blocks 1 block
Figure 6.4 Alternate Block Areas
Rev. 2.0, 12/00, page 29 of 46
6.3
Sector Management Codes
Sectors are managed by means of 16-byte management data The management data consists of a sector identification code, block number, good sector identification code, and ECC code.
512 bytes Data
16 bytes ECC + management
512 bytes Data
16 bytes ECC + management
512 bytes Data
16 bytes ECC + management
512 bytes Data
16 bytes ECC + management
Sector identification Block identification
ECC bytes
Blank
Block number
Good block code
Sector management bytes
Figure 6.5 Sector Management Codes (1) Good block code Stores 3 bytes (1C71C7H) of the ex-factory good block code. (2) Block number Stores the logical block number to which the sector belongs. (3) Block identification code Indicates which area (data area, spare block area, block management table, or bad block recording table) the block belongs to. The same code is stored for sectors within the same block (see table 6.2). (4) Sector identification Indicates the sector status (in use or not used) (see table 6.3). (5) ECC bytes These bytes store the EEC code for 512 bytes of data.
Rev. 2.0, 12/00, page 30 of 46
Table 6.2
Block Type Data area
Examples of Block Identification Code
Example of Code 0FH 01H Substituted Not used 10H 1FH 00H F0H Undefined FFH
Spare block area (1) Spare block area (2) Block management table Bad block recording table Ex-factory bad block Acquired bad block
Table 6.3
Examples of Sector Identification Code
Example of Data 00H FFH
Sector Status In use Not used
Rev. 2.0, 12/00, page 31 of 46
6.4
Sector Access Methods
Data area sectors are accessed by sector number. Sector numbers start from 0. The quotient resulting from dividing a sector number by 4 is the flash logical block number, and the remainder is the sector position within the block. Figure 6.6 shows a comparison between physical block numbers and logical block numbers.
Physical format 0 1 2 3 4 5 6 7 block 0 block 1 block 2 bad block (initial) block 4 block 5 bad block (acquired) block 7 Logical format block 0 block 1 block 2 block 3 block 4 block 5 block 6 block 7
...
Spare block area (2) Spare block area (1)
block 3
block 6 Block management table Bad block recording table 16 blocks
Figure 6.6 Comparison of Physical and Logical Formats With this sector management method, except for bad sectors, logical block number = physical block number. Therefore, a method whereby a sector is accessed by performing physical/logical block number conversion, and a method whereby a sector is accessed by performing only bad block physical/logical block number conversion, are possible.
Rev. 2.0, 12/00, page 32 of 46
...
...
...
Access method (1) Start Logical block number sector position calculation Logical block number calculation from block management table
Access method (2) Start Logical block number sector position calculation Bad sector
Sector management information read Good sector
Access to data
Logical block number calculation from block management table Access to data
Access to data
Figure 6.7 Sector Access Methods If a sector error occurs, the block to which the relevant sector belongs is identified as a bad block, and substitution is performed.
Rev. 2.0, 12/00, page 33 of 46
7 Some Common Questions
This section presents a number of technical questions that have been received concerning AND flash memory, in a Q&A format.
7.1
Concerning Flash Memory
[Question] What kind of memory is flash memory? [Answer] Flash memory is a kind of nonvolatile memory (NVM), which retains its data even if power is cut, and features both a high level of integration and electrical programming functions. Flash memory is broadly divided into two kinds: random access type and serial access type. AND flash is serial access flash memory. [Question] What is the difference between AND flash and NAND flash? [Answer] Both are serial access type flash memory for data storage use, featuring large capacity and highspeed reading, wiring, and erasing. A major difference between the two relates to the write/erase units. With AND flash, the write unit and erase unit are the same. For 256-Mbyte flash, this is the (2k + 64)-byte sector unit. With NAND flash, the write unit and erase unit are different, with a (512 + 16)-byte page used for writing, and an 8- to 16-kbyte block unit for erasing. [Question] What is MGM? [Answer] MGM is an abbreviation of Mostly Good Memory. 98% MGM refers to memory in which fewer than 2% of all sectors are invalid (bad) when the product is shipped. This increases chip yield and helps to lower costs.
Rev. 2.0, 12/00, page 34 of 46
[Question] What is multi-level technology? [Answer] In contrast to the two threshold levels, 0 and 1, of conventional memory, this technology controls four threshold levels, 00, 01, 10, and 11, enabling two memory cells' worth of data to be stored in a single memory cell. As multi-level technology enables twice the capacity of conventional technology to be achieved with the same number of memory cells, it is effective in cutting costs by increasing capacity and reducing chip size.
Conventional cell type Multi-level cell type
Memory cell threshold levels
Memory cell distribution
Memory cell threshold levels
Memory cell distribution
Rev. 2.0, 12/00, page 35 of 46
7.2
Concerning the Interface
[Question] Is it possible to design a system that can support future large-capacity products (512 Mbytes and up)? [Answer] Yes. The functions, command system, and electrical characteristics are compatible with current 512-Mbyte flash, but the increase in addresses has to be taken into consideration. The package, also, is identical to the 48-pin TSOP (I), and the pins necessary for control are also the same. [Question] How should AND flash be used? [Answer] The optimum method of use is determined by the requirements for the target system flash. Generally speaking, there are two methods of use, involving a trade-off between mounting area and performance: 1) Using a dedicated controller and a software driver for its interface (PC-ATA or IDE) 2) Incorporating the flash driver in the host CPU firmware, and performing direct control with a CPU of adequate performance (SH-3 80 MHz level)
(1) Using a dedicated controller CPU (2) Direct control by the CPU ROM Firmware Flash Driver PC-ATA/IDE Controller CPU
AND Flash
AND Flash
Rev. 2.0, 12/00, page 36 of 46
7.3
Concerning Power Shutdown
[Question] Are there any points requiring attention when powering on and off? [Answer] The RES pin should be driven low before turning on the power. When powering off, check that the chip is in the Ready state, then drive the RES pin low and cut the power. Using this procedure will ensure that data is protected even if the input signal becomes unstable when powering on or off
VCC ViLR ViHR ViLR
RES Input signal
ViLR = VSS 0.2 V ViHR = VCC 0.2 V
.
Don't care
After power-on, the chip performs internal initialization processing, and automatically goes to the standby state. Operation is possible as soon as the status changes to Ready. [Question] Won't data be lost if a power cut (momentary power interruption) occurs? [Answer] Data will not be lost if the flash status is Ready. In addition, data will not be lost when the status is Busy during reading. If the status is Busy during writing/erasing, operation is forcibly terminated before the memory cells go to the normal write/erase state, and so the data in the relevant sector will be undefined. For the sector recovery method in this case, see section 5, Power Shutdown Recovery Method.
Rev. 2.0, 12/00, page 37 of 46
7.4
Concerning Reset Operations
[Question] Can operation be forcibly reset by issuing a reset command (FFH) in the Busy state? [Answer] No. No commands are accepted in the Busy state. In the case of writing/erasing, it is possible to transit to the standby state by using a reset command (FFH) during the setup state before a start command (writing: 40H, erasing: B0H) is issued. [Question] What happens if a hardware reset (RES: low) is performed in the Busy state? [Answer] All operations are forcibly terminated and a transition is made to the deep standby state. In the case of writing/erasing, the data in the relevant sector will be undefined. The recovery method for a sector with undefined data due to a hardware reset is the same as the sector recovery method after power is cut. See section 5, Power Shutdown Recovery Method.
Rev. 2.0, 12/00, page 38 of 46
7.5
Concerning Write Operations
[Question] How many times can Program (1) and (3) additional writes be performed? [Answer] There is no limit to the number of writes that can be performed with the additional write function. However, an additional write should be counted as one rewrite (programming) operation. For example, when performing additional writes with one sector (2 kbytes) divided into four 512byte units, the number of rewrite operations for that sector should be counted as 4. [Question] What is the difference between Program (1) and (3) additional writes and Program (4) rewriting? [Answer] An additional write can only be performed on FFH data (i.e. data in the erased state) in a sector. Rewriting (programming) is a data contents update and overwrite function. For details, see section 1, Hitachi AND Flash Write Commands. [Question] If writing is performed with Program (4) by specifying a column address, what happens to data outside the specified range? [Answer] For data outside the specified range--that is, areas with no data input from outside--the data prior to the write is retained.
Rev. 2.0, 12/00, page 39 of 46
7.6
Concerning Bad Sectors
[Question] What is a bad sector (invalid sector) in AND flash? [Answer] AND flash memory is based on the MGM (Mostly Good Memory) concept, and allows the existence of sectors that do not operate normally--that is, defective sectors--within the chip. These defective sectors are called bad sectors. Both bad sectors present when the product is shipped from the factory, and bad sectors that arise later within the user system (acquired bad sectors), are permitted. [Question] How many bad sectors can be expected? [Answer] When flash is shipped from the factory, fewer than 2% of all sectors are bad. With 256-Mbyte flash this means 16,384 x 2% 328 sectors. [Question] Do bad sectors occur during use in the system? [Answer] Yes. Of the 98% or more ex-factory good sectors, it is possible that 1.8% (with 256-Mbyte flash: 16,384 (total number of sectors) x 98% x 1.8% 290 sectors) may become bad. [Question] How are ex-factory bad sectors identified? [Answer] The data shown in the table below is written in good sectors. If column addresses 820H to 825H are as shown in the table, the sector is good. Data in a bad sector is undefined.
Column address Data 000H to 81FH 00H 820H 1CH 821H 71H 822H 17H 823H 1CH 824H 71H 825H C7H 826H to 83FH FFH
Rev. 2.0, 12/00, page 40 of 46
[Question] How can the occurrence of bad sectors be identified during use in the system? [Answer] An error during writing/erasing is identified by reading the status register. After writing/erasing has been performed and the Ready state is entered, the relevant bit of the status register (bit 4 for writing, bit 5 for erasing) is checked, and processing ends normally if the bit is 0, or ends with an error if the bit is 1. In a normal end, the memory data values are as expected. Read errors should be detected using a method such as ECCs.
Mode Erase error Write error Read error Detection Method Status register read Status register read ECC check, etc.
[Question] When a sector that did not have a good sector code at the time of shipment was rewritten, the processing ended normally. Can this sector be used as a good sector? [Answer] A sector that does not have a good sector code at the time of shipment is a bad sector. A bad sector is one with a defect of some kind, or one that has a high probability of developing a defect. Even if rewriting is performed normally, there is still a possibility of some kind of problem arising, such as with the reliability of the data, for instance. Therefore, bad sectors should not be accessed. [Question] When a bad sector is read, data of some kind is obtained. Will the same data be obtained however many times that sector is read? [Answer] As data in a bad sector lacks reliability, there is no guarantee that the same data will be obtained again.
Rev. 2.0, 12/00, page 41 of 46
7.7
Concerning Sector Information (Good/Bad Sectors)
[Question] Is it possible to recover ex-factory sector information if it has been erased? [Answer] It is extremely difficult to do so. Ex-factory bad sectors are identified as the result of various tests conducted during the manufacturing process. In addition to simple write/erase/read tests, a test mode is also used that takes past experience into consideration. There are many modes for the occurrence of a bad sector, and only some of these are tested in ordinary write/erase tests. It is important to save sector information in some way, and ensure that it is not lost. [Question] Is it OK for sector codes written at the time of shipment to be overwritten with different codes? [Answer] Yes, this is possible. As long as good/bad sector information can be saved, the method is immaterial. The most appropriate method for the system should be used. [Question] Will any problems occur if ex-factory sector information is not used? [Answer] Bad sectors will be used. If a bad sector is used, the data in that sector will be unreliable. Even if writing/erasing ends normally, there is a possibility of problems occurring such as data become corrupted when left for a short while. [Question] Can bad sectors be managed by writing a bad sector code? [Answer] No. No data whatever can be written to a bad sector. Even if a write is performed successfully, the data will be unreliable.
Rev. 2.0, 12/00, page 42 of 46
7.8
Concerning Sector Management
[Question] What kind of management is necessary? [Answer] The following three kinds of management should be carried out. (1) Preventing ex-factory bad sectors from being accessed (2) Identifying bad sectors that occur during use in the system, and preventing their subsequent access (3) Performing sector replacement processing [Question] If a power interruption occurs after erasing is completed when rewriting data in the system, the good sector code is lost, and when power is restored the relevant sector becomes a bad sector. Is there any way of preventing this conversion to a bad sector? [Answer] One method is to hold a sector management table in the flash together with the good sector codes.
Rev. 2.0, 12/00, page 43 of 46
7.9
Concerning Error Handling and Sector Substitution Processing
[Question] When a write error occurs, is it OK to perform a retry on the same sector? [Answer] There is a possibility of an error occurring again. The retry should be performed on a different sector. [Question] How is the spare block decided when a sector error occurs and sector replacement is performed? [Answer] There is no fixed procedure. A method appropriate to the system should be used, such as reserving a certain area as a spare block area, or finding an empty sector when an error occurs and using that sector as the spare block.
Rev. 2.0, 12/00, page 44 of 46
7.10
Concerning ECCs
[Question] The sector data area is divided into four 512-byte units for use. Is a 3-bit ECC necessary for 512 bytes in this case? [Answer] Yes. [Question] Is it OK to write a code generated by the ECC function to a management area? [Answer] Yes, this can be done. [Question] Why are ECCs necessary? [Answer] They are used for detecting/correcting random bit errors due to data retention, and preventing read errors. A write error can easily be identified by checking the status, but a read error may occur due to data retention after the write has ended normally. As flash outputs data without detecting changes that may have occurred due to data retention, verification of read data is necessary on the system side.
7.11
Concerning Disturbance
[Question] Are there any write patterns that are susceptible to disturbance? [Answer] No. There is no disturbance problem with good sectors.
Rev. 2.0, 12/00, page 45 of 46
8. Check List
When designing a system incorporating Hitachi AND flash memory, the specifications in the following check list should be confirmed before starting the design work.
Item Pin arrangement Absolute ratings Operating environment P3, 6 P17 3.3 0.3 V 0 to 70C 300K times 30 mA 2.0 V VCC - 0.2 V VIL (Max.) tr/tf 0.8 V 0.2 V 5 ns Other Mode setting Power-on sequence Manufacturer's code read Product code read P6, 10, 11, 12 P23 P32 P32 P32 P35 P24, 25 P24, 25 P26, 27 P28 P29 P30, 31 P33 P34 P23 P19 to 22 P1, 18 P17 P36 (290 alternate sectors when using 3-bit ECC) P18 (f = 20 MHz) P18 P18 ( P18 P18 ( P19 ) ) Relevant Page of Data Sheet (ADE-203-1178A(Z)) Check Column Remarks
Basic operational condition
VCC Topr E/W ICC2 (Typ.) VIH (Min.)
Must-do items
Hardware design
Operation command setting
Status register read Clear status register Serial read Programming (1) (2) (1) (2) (3) (4) Recovery read Recovery write
Timing Basic software design System reliability software design
Power-off sequence All timing items
Understood that this is MGM. Possibility of up to 2% random bad sectors out of 16,384 sectors. Only good sectors must be accessed. System should not stop even if a good sector becomes a bad sector when accessed. Good sector code must not be deleted except in case of error occurrence. If power supply (3.0 V min.) cannot be sustained, Hitachi's recommended power-off sequence must be executed. Error provisions (1) Provide alternate sectors (at least 290). (2) Perform at least 3-bit ECC. Power shutdown provisions In case of emergency, perform chip-internal processing with /RES signal before powering off. If there is chain data, system must ensure that there is no problem if chain is broken midway.
Rev. 2.0, 12/00, page 46 of 46
Flash Application Design Guidelines
Publication Date: 1st Edition, March 2000 2nd Edition, December 2000 Published by: Electronic Devices Sales & Marketing Group Semiconductor & Integrated Circuits Hitachi, Ltd. Edited by: Technical Documentation Group Hitachi Kodaira Semiconductor Co., Ltd. Copyright (c) Hitachi, Ltd., 2000. All rights reserved. Printed in Japan.

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