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2 Megabit (256K x 8) SuperFlash MTP
SST27SF020, SST27VF020
Preliminary Specifications
FEATURES: * 5.0-Volt Read Operation for 27SF020 * 2.7-Volt Read Operation for 27VF020 * Superior Reliability - Endurance: Minimum 1000 Cycles - Greater than 100 years Data Retention * Low Power Consumption - Active Current: 20 mA (typical) for 5V and - 10 mA (typical) for 2.7V - Standby Current: 10 A (typical) for both 27SF020 and 27VF020 * Fast Access Time - 5.0-Volt Read - 90 and 120 ns - 2.7-Volt Read - 200 and 250 ns
* Fast Programming Operation - 20 s per byte - 5.4 second for the entire chip * Features Electrical Erase - Does Not Require UV Source - Chip Erase Time: 100 ms * TTL I/O Compatibility * JEDEC Standard Byte-wide EPROM Pinouts * 12V Power Supply for Programming/Erase * Packages Available - 32-Pin PLCC - 32-Pin Plastic DIP - 32-Pin TSOP
1 2 3 4 5 6
PRODUCT DESCRIPTION The 27SF020/27VF020 are a 256K x 8 CMOS, many time programmable (MTP) low cost flash memories, manufactured with SST's proprietary, high performance SuperFlash technology. The split gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The 27SF020/27VF020 can be electrically erased and programmed at least 1000 times using an external programmer. The 27SF020/27VF020 have to be erased prior to programming. The 27SF020/27VF020 conform to JEDEC standard pinouts for byte-wide memories. Featuring high performance byte programming, the 27SF020/27VF020 provide a byte-program time of 20 s. The entire memory can be programmed byte by byte in 5.4 seconds. Designed, manufactured, and tested for a wide spectrum of applications, the 27SF020/ 27VF020 are offered with an endurance of 1000 cycles. Data retention is rated at greater than 100 years. The 27SF020/27VF020 are suited for applications that require infrequent writes and low power nonvolatile storage. The 27SF020/27VF020 will improve flexibility, efficiency, and performance while matching the low cost in nonvolatile applications that currently use UVEPROMs, OTPs, and mask ROMs. To meet surface mount and conventional through hole requirements, the 27SF020/27VF020 are offered in 32-pin PLCC , 32-pin PDIP and 32-pin TSOP packages. See Figures 1 and 2 for pinouts.
Device Operation The 27SF020/27VF020 are low cost flash solutions that can be used to replace existing UV-EPROM, OTP, and mask ROM sockets. It is functionally (read and program) and pin compatible with industry standard EPROM products. In addition to EPROM functionality, the device also supports electrical erase operation via an external programmer. The 27SF020/27VF020 do not require a UV source to erase, and therefore the packages do not have a window. Read The Read operation of the 27SF020/27VF020 are controlled by CE# and OE#. Both CE# and OE# have to be low for the system to obtain data from the outputs. Once the address is stable, the address access time is equal to the delay from CE# to output (TCE). Data is available at the output after a delay of TOE from the falling edge of OE#, assuming that CE# pin has been low and the addresses have been stable for at least TCE - TOE. When the CE# pin is high, the chip is deselected and a typical standby current of 10 A is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Programming operation The 27SF020/27VF020 are programmed by using an external programmer. The programming mode is activated by asserting 12V (5%) on Vpp pin, Vcc = 5V5%, VIL on CE# pin, and VIH on OE# pin. The device is programmed byte by byte with the desired data at the desired address using a single pulse (PGM# pin low) of
7 8 9 10 11 12 13 14 15 16
(c) 1998 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MTP is a trademark of Silicon storage Technology, Inc. 1 319-04 12/97 These specifications are subject to change without notice.
2 Megabit SuperFlash MTP SST27SF020, SST27VF020
Preliminary Specifications 20 s. Using the MTP programming algorithm, the byte programming process continues byte by byte until the entire chip (256K bytes) has been programmed. Chip Erase Operation The only way to change a data from a "0" to "1" is by electrical erase that changes every bit in the device to "1". Unlike traditional EPROMs, which use UV light to do the chip erase, the 27SF020/27VF020 use an electrical chip erase operation. This saves a significant amount of time (about 30 minutes for erase operation). The entire chip can be erased in a single pulse of 100 ms (PGM# pin low). In order to activate the erase mode, the 12V (5%) is applied to VPP and A9 pins, Vcc = 5V5%, VIL on CE# pin, and VIH on OE# pin. All other address and data pins are "don't care". The falling edge of PGM# will start the Chip Erase operation. Once the chip has been erased, all bytes must be verified for FF. Refer to figure 8 for the flow chart. The 27SF020/27VF020 can also be reprogrammed in the system. This requires the availability of 12V for VPP to program and an additional 12V for address A9 to erase. Product Identification Mode The product identification mode identifies the device as the 27SF020/27VF020 and manufacturer as SST. This mode may be accessed by hardware method. To activate this mode, the programming equipment must force VH (12V5%) on address A9 with VPP pin at 5V10%. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0. For details, see Table 3 for hardware operation.
TABLE 1: PRODUCT IDENTIFICATION TABLE Byte Manufacturer's Code 0000 H 27SF020 Device Code 0001 H 27VF020 Device Code 0001 H
Data BF H A6 H C6 H
319 PGM T1.0
FUNCTIONAL BLOCK DIAGRAM OF THE SST27SF020/27VF020
X-Decoder
2,097,152 Bit EEPROM Cell Array
A17 - A0
Address buffer Y-Decoder
CE# OE# A9 VPP PGM#
Control Logic
I/O Buffers
DQ7 - DQ0
319 MSW B1.0
(c) 1998 Silicon Storage Technology, Inc.
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2 Megabit SuperFlash MTP SST27SF020, SST27VF020
Preliminary Specifications
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 Vss DQ2 DQ1 DQ0 A0 A1 A2 A3
319 MSW F01.0
A11 A9 A8 A13 A14 A17 PGM# Vcc Vpp A16 A15 A12 A7 A6 A5 A4
Standard Pinout Top View
1 2 3 4 5
Die up
FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN TSOP PACKAGES
A15
VPP A16 VCC 1
VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 2 3 4 5 6
32 31 30 29 28 27
VCC PGM# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3
A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9
A12
PGM# A17
6
A14 A13 A8 A9 A11 OE# A10 CE# DQ7
4
3
2
32 31 30 29 28 27 26
7 8 9 10
319 MSW F02.0
26 7 32 Pin PDIP 25 8 9 Top View 24 23 10 11 12 13 14 15 16 22 21 20 19 18 17
32-Lead PLCC Top View
25 24 23 22 21
10 11 12 13
14 15 16
17 18 19
20
DQ1 DQ2
VSS
DQ4 DQ6 DQ3 DQ5
FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN PLASTIC DIPS AND 32-LEAD PLCCS TABLE 2: PIN DESCRIPTION Symbol Pin Name A17-A0 Address Inputs DQ7-DQ0 Data Input/Output CE# OE# PGM# VPP VCC VSS Chip Enable Output Enable Program/Erase Pin Power Supply for Program or Erase Power Supply Ground
319 PGM T2.1
11 12 13 14 15 16
Functions To provide memory addresses To output data during read cycles and receive input data during program cycle, the outputs are in tri-state when OE# or CE# is high To activate the device when CE# is low To gate the data output buffers during read operation Used for program or erase (PGM# = VIL pulse during program or erase) High voltage pin during chip erase and programming operation 12-volt (5%) To provide 5-volt supply (10%) for the 27SF020 and 3-volt supply (2.7-3.6 V) for the 27VF020
(c) 1998 Silicon Storage Technology, Inc.
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2 Megabit SuperFlash MTP SST27SF020, SST27VF020
Preliminary Specifications TABLE 3: OPERATION MODES SELECTION Mode CE# OE# PGM# Read VIL VIL X Output Disable Program Standby Chip Erase Program/Erase Inhibit Product Identification VIL VIL VIH VIL VIH VIL VIH VIH X VIH X VIL X VIL X VIL X X
A9 AIN X AIN X VH X VH
VPP VCC or VSS VCC or VSS VPPH VCC or VSS VPPH VPPH VCC or VSS
DQ DOUT High Z DIN High Z High Z High Z Manufacturer Code (BF) Device Code (A6 for 27SF020 & C6 for 27VF020)
Address AIN AIN AIN X X X A17-A1 = VIL, A0 = VIL A17-A1 = VIL, A0 = VIH
Note:
X = VIL or VIH VPPH = 12V5%, VH = 12V5%
319 PGM T3.0
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias ................................................................................................................. -55C to +125C Storage Temperature ...................................................................................................................... -65C to +150C D. C. Voltage on Any Pin to Ground Potential ............................................................................. -0.5V to VCC+ 0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential ......................................................... -1.0V to VCC+ 1.0V Voltage on A9 and VPP Pin to Ground Potential .................................................................................. -0.5V to 14.0V Package Power Dissipation Capability (TA = 25C) ........................................................................................... 1.0W Through Hole Lead Soldering Temperature (10 Seconds) .............................................................................. 300C Surface Mount Lead Soldering Temperature (3 Seconds) ............................................................................... 240C Output Short Circuit Current(1) ............................................................................................................................................................... 100 mA
Note: (1) Outputs shorted for no more than one second. No more than one output shorted at a time.
27SF020 OPERATING RANGE (READ) Range Ambient Temp Commercial 0C to +70C Industrial -40C to +85C
AC CONDITIONS OF TEST VCC 5V10% 5V10% Input Rise/Fall Time ......... 10 ns Output Load ..................... 1 TTL Gate and CL = 100 pF See Figures 6 and 7
27VF020 OPERATING RANGE (READ) Range Ambient Temp Commercial 0C to +70C Industrial -40C to +85C
AC CONDITIONS OF TEST VCC 2.7-3.6V 2.7-3.6V Input Rise/Fall Time ......... 10 ns Output Load ..................... 1 TTL Gate and CL = 100 pF See Figures 6 and 7
(c) 1998 Silicon Storage Technology, Inc.
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2 Megabit SuperFlash MTP SST27SF020, SST27VF020
Preliminary Specifications TABLE 4: 27SF020 READ MODE DC OPERATING CHARACTERISTICS Vcc = 5 V10%, TA = 0C to 70C (Commercial) or -40C to +85C (Industrial) Limits Symbol Parameter Min Max Units Test Conditions ICC VCC Read Current 30 mA CE# = OE# = VIL all I/Os open, Address Input = VIL/VIH at f = 1/TRC Min, VCC = VCC Max IPPR VPP Read Current 100 A CE# = OE# = VIL, all I/Os open, Address Input = VIL/VIH at f = 1/TRC Min, VCC = VCC Max, Vpp = Vcc ISB1 Standby VCC Current 3 mA CE# = OE# = VIH, VCC = VCC Max (TTL input) ISB2 Standby VCC Current 50 A CE#=OE#=VCC -0.3V (CMOS input) VCC = VCC Max. ILI Input Leakage Current 1 A VIN = GND to VCC, VCC = VCC Max ILO Output Leakage Current 10 A VOUT = GND to VCC, VCC = VCC Max VIL Input Low Voltage 0.8 V VCC = VCC Max VIH Input High Voltage 2.0 Vcc+0.5 V VCC = VCC Max VOL Output Low Voltage 0.4 V IOL = 2.1 mA, VCC = VCC Min VOH Output High Voltage 2.4 V IOH = -400A, VCC = VCC Min IH Supervoltage Current 100 A CE# = OE# = VIL, A9 = VH for A9
319 PGM T4.3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
TABLE 5: 27VF020 READ MODE DC OPERATING CHARACTERISTICS Vcc = 2.7-3.6V, TA = 0C to 70C (Commercial) or -40C to +85C (Industrial) Limits Symbol Parameter Min Max Units Test Conditions ICC Vcc Read Current 12 mA CE#=OE#=VIL all I/Os open, Address input = VIL/VIH at f=1/TRC Min., VCC=VCC Max IPPR VPP Read Current 100 A CE# = OE# = VIL, all I/Os open, Address Input = VIL/VIH at f = 1/TRC Min, VCC = VCC Max, Vpp = Vcc ISB1 Standby VCC Current 1 mA CE#=OE#=VIH, VCC =VCC Max. (TTL input) ISB2 Standby VCC Current 15 A CE#=OE#=VCC -0.3V. (CMOS input) VCC = VCC Max. ILI Input Leakage Current 1 A VIN =GND to VCC, VCC = VCC Max. ILO Output Leakage Current 10 A VOUT =GND to VCC, VCC = VCC Max. VIL Input Low Voltage 0.8 V VCC = VCC Max. VIH Input High Voltage 2.0 Vcc+0.5 V VCC = VCC Max. VOL Output Low Voltage 0.4 V IOL = 100 A, VCC = VCC Min. VOH Output High Voltage 2.4 V IOH = -100 A, VCC = VCC Min. IH Supervoltage Current 100 A CE# = OE# = VIL, A9 = VH for A9
319 PGM T5.3
(c) 1998 Silicon Storage Technology, Inc.
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2 Megabit SuperFlash MTP SST27SF020, SST27VF020
Preliminary Specifications TABLE 6: 27SF020/27VF020 PROGRAM/ERASE DC OPERATING CHARACTERISTICS Vcc = 5 V10%, Vpp = VPPH,TA = 25C5C Limits Symbol Parameter Min Max Units Test Conditions ICP VCC Erase or Program 30 mA CE# = VIL, Vpp = 12V5%, VCC = VCC Max Current IPP VPP Erase or Program 1 mA CE# = VIL, Vpp = 12V5%, VCC = VCC Max Current ILI Input Leakage Current 1 A VIN = GND to VCC, VCC = VCC Max ILO Output Leakage Current 10 A VOUT = GND to VCC, VCC = VCC Max VH Supervoltage for A9 11.4 12.6 V CE# = OE# = VIL (1) IH Supervoltage Current 200 A CE# = OE# = VIL, A9 = VH Max for A9 VPPH High Voltage for VPP Pin 11.4 12.6 V
319 PGM T6.0
Note:
(1)
This parameter is measured only for initial qualification and after the design or process change that could affect this parameter.
TABLE 7: POWER-UP TIMINGS Symbol Parameter (1) TPU-READ Power-up to Read Operation
Note:
(1)This
Maximum 100
Units s
319 PGM T7.0
parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: CAPACITANCE (TA = 25 C, f=1 MHz, other pins open) Parameter Description Test Condition CI/O(1) I/O Pin Capacitance VI/O = 0V CIN(1) Input Capacitance VIN = 0V
Maximum 12 pF 6 pF
319 PGM T8.0
Note: (1)This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 9: RELIABILITY CHARACTERISTICS Symbol Parameter NEND Endurance TDR(1) Data Retention VZAP_HBM(1) ESD Susceptibility Human Body Model (1) VZAP_MM ESD Susceptibility Machine Model (1) ILTH Latch Up
Note:
(1)
Minimum Specification 1000 100 2000 300 100
Units Cycles Years Volts Volts mA
Test Method MIL-STD-883, Method 1033 JEDEC Standard A103 JEDEC Standard A114 JEDEC Standard A115 JEDEC Standard 78
319 PGM T9.1
This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
(c) 1998 Silicon Storage Technology, Inc.
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2 Megabit SuperFlash MTP SST27SF020, SST27VF020
Preliminary Specifications AC CHARACTERISTICS TABLE 10: 27SF020 READ CYCLE TIMING PARAMETERS Symbol TRC TCE TAA TOE TCLZ(1) TOLZ(1) TCHZ(1) TOHZ(1) TOH(1) Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change 27SF020-90 Min Max 90 90 90 40 0 0 30 30 0 27SF020-120 Min Max 120 120 120 50 0 0 30 30 0 Units ns ns ns ns ns ns ns ns ns
319 PGM T10.0
1 2 3 4 5 6
TABLE 11: 27VF020 READ CYCLE TIMING PARAMETERS Symbol TRC TCE TAA TOE TCLZ(1) TOLZ(1) TCHZ(1) TOHZ(1) TOH(1) Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change 27VF020-200 Min Max 200 200 200 100 0 0 50 50 0 27VF020-250 Min Max 250 250 250 120 0 0 50 50 0 Units ns ns ns ns ns ns ns ns ns
319 PGM T11.0
7 8 9 10 11 12 13 14 15 16
(c) 1998 Silicon Storage Technology, Inc.
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2 Megabit SuperFlash MTP SST27SF020, SST27VF020
Preliminary Specifications TABLE 12: PROGRAMMING/ERASE CYCLE TIMING PARAMETERS Symbol Parameter Min TCES(1) CE# Setup Time 2 (1) TCEH CE# Hold Time 2 (1) TAS Address Setup Time 2 TAH(1) Address Hold Time 2 TPRT(1) VPP Pulse Rise Time 50 TVPS(1) VPP Setup Time 2 (1) TVPH VPP Hold Time 2 TPW PGM# Program Pulse Width 20 TEW PGM# Erase Pulse Width 100 TDS(1) Data Setup Time 2 (1) TDH Data Hold Time 2 TVR(1) A9 Recovery Time for Erase 2 TART A9 Rise Time to 12V during Erase 50 TA9S(1) A9 Setup Time during Erase 2 (1) TA9H A9 Hold Time during Erase 2 Max Units s s s s ns s s s ms s s s ns s s
319 PGM T12.0
40 500
Note: (1)This parameter is measured only for initial qualification and after the design or process change that could affect this parameter.
(c) 1998 Silicon Storage Technology, Inc.
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2 Megabit SuperFlash MTP SST27SF020, SST27VF020
Preliminary Specifications
TRC ADDRESS TAA
1
TCE
CE#
2
TOHZ TOH
D AT A VALID
OE#
TOE TOLZ
3 4 5 6
319 AC F03.0
TCHZ
DA TA VALID
DQ 7-0
HIG H-Z
TCLZ V CC Vpp V SS V IH PGM# V IL
FIGURE 3: READ CYCLE TIMING DIAGRAM
7 8
ADDRESS (E X C E P T A 9 )
9
CE# TCEH OE# V IH
10 11
D Q 7-0 V PPH V CC V pp V SS V PPH A9 V IH V IL TART TA9H PG M # TCES TEW TA9S TVR TPRT TVPS TVPH
12 13 14 15 16
319 AC F04.0
FIGURE 4: ERASE TIMING DIAGRAM
(c) 1998 Silicon Storage Technology, Inc.
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2 Megabit SuperFlash MTP SST27SF020, SST27VF020
Preliminary Specifications
ADDRESS
ADDRESS VALID
TAH CE# TAS TCEH
OE#
VIH TDS TDH
DQ7-0
HIGH-Z
DATA VALID
VPPH VCC Vpp VSS TPRT TVPS TPW TVPH
PGM# TCES
319 AC F05.0
FIGURE 5: PROGRAM TIMING DIAGRAM
2.4 INPUT
2.0 REFERENCE POINTS 0.8
2.0 OUTPUT 0.8
0.4
319 MSW F06.0
AC test inputs are driven at VOH (2.4 VTTL) for a logic "1" and VOL (0.4 VTTL) for a logic "0". Measurement reference points for inputs and outputs are VIH (2.0 VTTL) and VIL (0.8 VTTL). Inputs rise and fall times (10% 90%) are <10 ns. FIGURE 6: AC INPUT/OUTPUT REFERENCE WAVEFORMS
(c) 1998 Silicon Storage Technology, Inc.
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2 Megabit SuperFlash MTP SST27SF020, SST27VF020
Preliminary Specifications
TEST LOAD EXAMPLE
VCC
TO TESTER
1 2
RL HIGH
3
TO DUT
4
CL RL LOW
5 6
319 MSW F07.0
7 8 9 10 11 12 13 14 15 16
FIGURE 7: TEST LOAD EXAMPLE
(c) 1998 Silicon Storage Technology, Inc.
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2 Megabit SuperFlash MTP SST27SF020, SST27VF020
Preliminary Specifications
Start
A9 = VH , VPP = VPPH
CE# = VIL, OE# = VIH
Erase 100 ms pulse (PGM# = VIL)
PGM# = VIH
A9 = VIL or VIH
A9 Recovery Time
Device into Read mode
No Compare All bytes to FF
Yes Device Passed Device Failed
319 MSW F08.0
FIGURE 8: ERASE ALGORITHM
(c) 1998 Silicon Storage Technology, Inc.
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2 Megabit SuperFlash MTP SST27SF020, SST27VF020
Preliminary Specifications
Start
1
Erase See Figure 8
2
VPP = VPPH
3
Address = First Location
4
CE# = VIL, OE# = VIH
5
Program 20s pulse (PGM# = VIL)
6
Increment Address No Last Address? Yes
7
Device into Read mode
8
No
Compare all bytes to original data Yes
9 10
Device Passed
Device Failed
11
319 ILL F09.1
12 13 14 15 16
FIGURE 9: PROGRAMMING ALGORITHM
(c) 1998 Silicon Storage Technology, Inc.
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2 Megabit SuperFlash MTP SST27SF020, SST27VF020
Preliminary Specifications PRODUCT ORDERING INFORMATION
Device SST27XF020
Speed - XXX -
Suffix1 XX -
Suffix2 XX Package Modifier H = 32 leads Numeric = Die modifier Package Type P = PDIP N = PLCC E = TSOP (die up) U = Unencapsulated die Operating Temperature C = Commercial = 0 to 70C I = Industrial = -40 to 85C Minimum Endurance 3 = 1000 cycles Read Access Speed 90 = 90 ns, 120 = 120 ns 200 = 200 ns, 250 = 250 ns Read Voltage S = 5.0 Volt Read V = 2.7 Volt Read (2.7-3.6V)
(c) 1998 Silicon Storage Technology, Inc.
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2 Megabit SuperFlash MTP SST27SF020, SST27VF020
Preliminary Specifications 27SF020 Valid combinations SST27SF020- 90-3C-EH SST27SF020- 90-3C-NH SST27SF020- 120-3C-EH SST27SF020- 120-3C-NH SST27SF020- 90-3I-EH SST27SF020- 120-3I-EH SST27SF020- 90-3I-NH SST27SF020- 120-3I-NH SST27SF020- 90-3C-PH SST27SF020- 120-3C-PH
1 2 3
SST27SF020- 120-3C-U1
27VF020 Valid combinations SST27VF020- 200-3C-EH SST27VF020- 200-3C-NH SST27VF020- 250-3C-EH SST27VF020- 250-3C-NH SST27VF020- 200-3I-EH SST27VF020- 200-3I-NH
SST27VF020- 200-3C-PH SST27VF020- 250-3C-PH SST27VF020-250-3C-U1
4 5 6 7 8 9 10 11 12 13 14 15 16
Example:Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
(c) 1998 Silicon Storage Technology, Inc.
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2 Megabit SuperFlash MTP SST27SF020, SST27VF020
Preliminary Specifications PACKAGING DIAGRAMS
32pn TSOP EH AC.4
Note: 1. Complies with JEDEC publication 95 MO-142 BD dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in metric (min/max). 3. Coplanarity: 0.1 (.05) mm.
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) SST PACKAGE CODE: EH
32pn PDIP PH AC.2 Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.
32-LEAD PLASTIC DUAL-IN-LINE PACKAGE (PDIP) SST PACKAGE CODE: PH
(c) 1998 Silicon Storage Technology, Inc.
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2 Megabit SuperFlash MTP SST27SF020, SST27VF020
Preliminary Specifications
1 2 3 4 5 6
32pn PLCC NH AC.3
7 8 9 10 11 12 13 14 15 16
Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.
32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE: NH
(c) 1998 Silicon Storage Technology, Inc.
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319-04 12/97

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