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| Preliminary Data Sheet No. PD60030-M IR2213(S) HIGH AND LOW SIDE DRIVER Features * Floating channel designed for bootstrap operation Fully operational to +1200V Tolerant to negative transient voltage dV/dt immune Gate drive supply range from 12 to 20V Undervoltage lockout for both channels 3.3V logic compatible Separate logic supply range from 3.3V to 20V Logic and power ground 5V offset CMOS Schmitt-triggered inputs with pull-down Cycle by cycle edge-triggered shutdown logic Matched propagation delay for both channels Product Summary VOFFSET IO+/VOUT ton/off (typ.) Delay Matching 1200V max. 1.7A / 2A 12 - 20V 280 & 225 ns 30 ns * * * * * * * Outputs in phase with inputs Packages Description The IR2213(S) is a high voltage, high speed power MOSFET and IGBT driver with independent high and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable 16-Lead SOIC (wide body) ruggedized monolithic construction. Logic inputs are 14-Lead PDIP compatible with standard CMOS or LSTTL outputs, down to 3.3V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 1200 volts. Typical Connection up to 1200V HO V DD HIN SD LIN V SS VCC V DD HIN SD LIN V SS V CC COM LO VB VS TO LOAD (Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. www.irf.com 1 IR2213(S) Absolute Maximum Ratings Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air conditions. Symbol VB VS VHO VCC VLO VDD VSS VIN dVs/dt PD RTHJA TJ TS TL Definition High Side Floating Supply Voltage High Side Floating Supply Offset Voltage High Side Floating Output Voltage Low Side Fixed Supply Voltage Low Side Output Voltage Logic Supply Voltage Logic Supply Offset Voltage Logic Input Voltage (HIN, LIN & SD) Allowable Offset Supply Voltage Transient (Figure 2) Package Power Dissipation @ TA +25 C Thermal Resistance, Junction to Ambient Junction Temperature Storage Temperature Lead Temperature (Soldering, 10 seconds) (14 Lead PDIP) (16 Lead SOIC) (14 Lead PDIP) (16 Lead SOIC) Min. -0.3 VB - 25 VS - 0.3 -0.3 -0.3 -0.3 VCC - 25 VSS - 0.3 -- -- -- -- -- -- -55 -- Max. 1225 VB + 0.3 VB + 0.3 25 VCC + 0.3 VSS + 25 VCC + 0.3 VDD + 0.3 50 1.6 1.25 75 100 125 150 300 Units V V/ns W C/W C Recommended Operating Conditions The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the recommended conditions. The V S and VSS offset ratings are tested with all supplies biased at 15V differential. Symbol VB VS VHO VCC VLO VDD VSS VIN Definition High Side Floating Supply Absolute Voltage High Side Floating Supply Offset Voltage High Side Floating Output Voltage Low Side Fixed Supply Voltage Low Side Output Voltage Logic Supply Voltage Logic Supply Offset Voltage Logic Input Voltage (HIN, LIN & SD) Min. VS + 12 Note 1 VS 12 0 VSS + 3 -5 (Note 2) VSS Max. VS + 20 1200 VB 20 VCC VSS + 20 5 VDD Units V Note 1: Logic operational for V S of -5 to +1200V. Logic state held for VS of -5V to -V BS. (Please refer to the Design Tip DT97-3 for more details). Note 2: When VDD<5V, the minimum VSS offset is limited to -VDD 2 www.irf.com IR2213(S) Dynamic Electrical Characteristics VBIAS (VCC, V BS, VDD ) = 15V, CL = 1000 pF, TA = 25C and V SS = COM unless otherwise specified. The dynamic electrical characteristics are measured using the test circuit shown in Figure 3. Symbol ton toff tsd tr tf MT Definition Turn-On Propagation Delay Turn-Off Propagation Delay Shutdown Propagation Delay Turn-On Rise Time Turn-Off Fall Time Delay Matching, HS & LS Turn-On/Off Min. Typ. Max. Units Test Conditions -- -- -- -- -- -- 280 225 230 25 17 -- -- -- -- -- -- 30 Figure 5 VS = 0V VS = 1200V VS = 1200V ns Static Electrical Characteristics VBIAS (VCC, V BS, VDD) = 15V, TA = 25C and VSS = COM unless otherwise specified. The V IN, VTH and IIN parameters are referenced to VSS and are applicable to all three logic input leads: HIN, LIN and SD. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO. Symbol VIH VIL VOH VOL ILK IQBS IQCC IQDD IIN+ IINVBSUV+ VBSUVVCCUV+ VCCUVIO+ IO- Definition Logic "1" Input Voltage Logic "0" Input Voltage High Level Output Voltage, VBIAS - VO Low Level Output Voltage, VO Offset Supply Leakage Current Quiescent VBS Supply Current Quiescent VCC Supply Current Quiescent VDD Supply Current Logic "1" Input Bias Current Logic "0" Input Bias Current VBS Supply Undervoltage Positive Going Threshold VBS Supply Undervoltage Negative Going Threshold VCC Supply Undervoltage Positive Going Threshold VCC Supply Undervoltage Negative Going Threshold Output High Short Circuit Pulsed Current Output Low Short Circuit Pulsed Current Min. Typ. Max. Units Test Conditions 9.5 -- -- -- -- -- -- -- -- -- 8.7 7.9 8.7 7.9 1.7 2.0 -- -- -- -- -- 125 180 15 20 -- 10.2 9.3 10.2 9.3 2.0 2.5 -- 6.0 1.2 0.1 50 230 340 30 40 1.0 11.7 10.7 11.7 10.7 -- -- A VO = 0V, VIN = VDD PW 10 s VO = 15V, VIN = 0V PW 10 s V A V IO = 0A IO = 0A VB = VS = 1200V VIN = 0V or VDD VIN = 0V or VDD VIN = 0V or VDD VIN = VDD VIN = 0V www.irf.com 3 IR2213(S) Functional Block Diagram VB VDD RQ S HIN HV LEVEL SHIFT UV DETECT PULSE FILTER R R S Q HO VDD /VCC LEVEL SHIFT PULSE GEN VS SD UV DETECT VCC VDD /VCC LEVEL SHIFT LIN RQ VSS S LO DELAY COM Lead Definitions Symbol Description VDD HIN SD LIN VSS VB HO VS VCC LO COM Logic supply Logic input for high side gate driver output (HO), in phase Logic input for shutdown Logic input for low side gate driver output (LO), in phase Logic ground High side floating supply High side gate drive output High side floating supply return Low side supply Low side gate drive output Low side return Lead Assignments 14 Lead PDIP 16 Lead SOIC (Wide Body) IR2213 Part Number 4 IR2213S www.irf.com IR2213(S) HV =10 to 1200V <50 V/ns Figure 1. Input/Output Timing Diagram Figure 2. Floating Supply Voltage Transient Test Circuit HIN LIN (0 to 1200V) 50% 50% ton tr 90% toff 90% tf HO LO Figure 3. Switching Time Test Circuit 10% 10% Figure 4. Switching Time Waveform Definition 50% HIN LIN 50% 50% SD tsd LO 90% MT HO 10% MT 90% HO LO LO Figure 5. Shutdown Waveform Definitions HO Figure 6. Delay Matching Waveform Definitions www.irf.com 5 IR2213(S) 100 100 80 Turn-On Rise Time (ns) Turn-On Rise Time (ns) 80 60 60 Max. 40 M ax. Typ. 40 Typ. 20 20 0 -50 -25 0 25 50 75 100 125 Temperature (C) 0 10 12 14 16 18 20 VBIAS Supply Voltage (V) Figure 10A. Turn-On Rise Time vs. Temperature 50 50 Figure 10B. Turn-On Rise Time vs. Voltage 40 Turn-Off Fall Time (ns) Turn-Off Fall Time (ns) 40 30 Max. 30 20 Typ. 20 Max. Typ. 10 10 0 -50 -25 0 25 50 75 100 125 Temperature (C) 0 10 12 14 16 18 20 VBIAS Supply Voltage (V) Figure 11A. Turn-Off Fall Time vs. Temperature 15.0 Figure 11B. Turn-Off Fall Time vs. Voltage 15 Logic " 1" Input Threshold (V) 12.0 Logic "1" Input Threshold (V) Min. 12 Max. 9 6 3 0 9.0 6.0 3.0 0.0 -50 -25 0 25 50 75 100 125 Temperature (C) 0 2 4 6 8 10 12 14 16 18 20 VDD Logic Supply Voltage (V) Figure 12A. Logic "1" Input Threshold vs. Temperature Figure 12B. Logic "1" Input Threshold vs. Voltage 6 www.irf.com IR2213(S) 15.0 15 12 Logic "0" Input Threshold (V) 12.0 Logic "0" Input Threshold (V) 9.0 9 Min. 6 3 0 6.0 Max. 3.0 0.0 -50 -25 0 25 50 75 100 125 Temperature (C) 0 2 4 6 8 10 12 14 16 18 20 VDD Logic Supply Voltage (V) Figure 13A. Logic "0" Input Threshold vs. Temperature Figure 13B. Logic "0" Input Threshold vs. Voltage 5.00 5.00 4.00 High Level Output Voltage (V) High Level Output Voltage (V) 4.00 3.00 3.00 2.00 Max. 2.00 M ax. 1.00 1.00 0.00 -50 -25 0 25 50 75 100 125 Temperature (C) 0.00 10 12 14 16 18 20 VBIAS Supply Voltage (V) Figure 14A. High Level Output vs. Temperature 1.00 1.00 Figure 14B. High Level Output vs. Voltage 0.80 Low Level Output Voltage (V) Low Level Output Voltage (V) Max. 0.80 0.60 0.60 0.40 0.40 0.20 0.20 M ax. 0.00 -50 -25 0 25 50 75 100 125 Temperature (C) 0.00 10 12 14 16 18 20 VBIAS Supply Voltage (V) Figure 15A. Low Level Output vs. Temperature Figure 15B. Low Level Output vs. Voltage www.irf.com 7 IR2213(S) 500 500 Offset Supply Leakage Current (A) Offset Supply Leakage Current (A) 400 400 300 300 200 200 100 Max. 100 Max. 0 -50 -25 0 25 50 75 100 125 Temperature (C) 0 0 200 400 600 800 1000 1200 VB Boost Voltage (V) Figure 16A. Offset Supply Current vs. Temperature Figure 16B. Offset Supply Current vs. Voltage 500 500 400 VBS Supply Current (A) VBS Supply Current (A) 400 300 Max. 300 200 Typ. 200 Max. 100 100 Typ. 0 -50 -25 0 25 50 75 100 125 Temperature (C) 0 10 12 14 16 18 20 VBS Floating Supply Voltage (V) Figure 17A. VBS Supply Current vs. Temperature Figure 17B. VBS Supply Current vs. Voltage 625 625 500 VCC Supply Current (A) VCC Supply Current (A) 500 375 Max. 375 250 Typ. 250 Max. 125 125 Typ. 0 -50 -25 0 25 50 75 100 125 Temperature (C) 0 10 12 14 16 18 20 VCC Fixed Supply Voltage (V) Figure 18A. VCC Supply Current vs. Temperature Figure 18B. VCC Supply Current vs. Voltage 8 www.irf.com IR2213(S) 100 60 50 VDD Supply Current (A) 80 VDD Supply Current (A) 40 30 20 10 max 60 40 Max. 20 Typ. typ. 0 0 -50 -25 0 25 50 75 100 125 Temperature (C) 0 2 4 6 8 10 12 14 16 18 20 VDD Logic Supply Voltage (V) Figure 19A. VDD Supply Current vs. Temperature Figure 19B. VDD Supply Current vs. VDD Voltage 100 Logic "1" Input Bias Current (A) 60 50 40 30 20 10 Typ. 80 Logic "1" Input Bias Current (A) 60 40 Max. max 20 0 -50 -25 0 25 50 75 100 125 Temperature (C) 0 0 2 typ. 4 6 8 10 12 14 16 18 20 VDD Logic Supply Voltage (V) Figure 20A. Logic "1" Input Current vs. Temperature Figure 20B. Logic "1" Input Current vs. VDD Voltage 5.00 Logic "0" Input Bias Current (A) 5 4 3 2 1 0 max 4.00 Logic "0" Input Bias Current (A) 3.00 2.00 1.00 Max. 0.00 -50 -25 0 25 50 75 100 125 Temperature (C) 0 2 4 6 8 10 12 14 16 18 20 VDD Logic Supply Voltage (V) Figure 21A. Logic "0" Input Current vs. Temperature Figure 21B. Logic "0" Input Current vs. VDD Voltage www.irf.com 9 IR2213(S) 0.0 20.0 Typ. -6.0 VSS Logic Supply Offset Voltage (V) -3.0 VS Offset Supply Voltage (V) 16.0 12.0 -9.0 8.0 Typ. -12.0 4.0 -15.0 10 12 14 16 18 20 VBS Floating Supply Voltage (V) 0.0 10 12 14 16 18 20 VCC Fixed Supply Voltage (V) Figure 36. Maximum VS Negative Offset vs. VBS Supply Voltage Figure 37. Maximum VSS Positive Offset vs. VCC Supply Voltage Case outlines 14-Lead PDIP 01-6010 01-3002 03 (MS-001AC) 10 www.irf.com IR2213(S) 16-Lead SOIC (wide body) 01 6015 01-3014 03 (MS-013AA) IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 Data and specifications subject to change without notice. 2/11/2002 www.irf.com 11 |
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