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Data Sheet XE1202
QAMP VDDD VDDF VDDP IAMP VDDA VDD
IAmp
QAmp SCAN
I RFA LNA RFB Q
AMP
BPF
AMP
Limiter DCLK FSK Demod. Bit Sync. DATAOUT
AMP
BPF
AMP
Limiter
Pattern Recognition LO Buff. Phase Shifter Prog. divider RSSI FEI
PATTERN MODE 0 MODE 1
Control Logic modulator /n Synthesizer POR Oscillator /n Clock Out I Ref
MODE 2 SI SO
RFOUT
PA
VCO
PFD
SCK EN
DATAIN
VSSD
VSSF
VSSF
VSSP
VSSP
CLKOUT
TSUPP
TKA
TKB
XTA
XTB
LFB
TVCO
VSSA
XE1202
433MHz / 868MHz / 915MHz Low-power, integrated UHF transceiver
GENERAL DESCRIPTION
The XE1202 is a single chip transceiver operating in the 433, 868 and 915MHz license free ISM (Industry Scientific and Medical) frequency bands. Its highly integrated architecture allows for minimum external components while maintaining design flexibility. All major RF communication parameters are programmable and most of them can be dynamically set. The XE1202 offers the unique advantage of narrow-band and wide-band communication, this without the need to modify the number or parameters of the external components. The XE1202 is optimized for low power consumption while offering high RF output power and channelized operation suited for both the European (ETSI-300-220) and the North American (FCC part 15) regulatory standards
KEY PRODUCT FEATURES
* * * * * * * * * * * Programmable RF output power: up to +15dBm High reception sensitivity: down to -113dBm Low power consumption: RX=14mA; TX = 48mA @15 dBm output power Supply voltage down to 2.7V Wide band operation: 400kHz channels for data rates of up to 76.8kbps, NRZ coding Narrow band operation: down to 25kHz channels for data rates of 4.8kbps, NRZ coding On-chip frequency synthesizer with steps of 500Hz Continuous phase 2-level FSK modulation Incoming data pattern recognition Built-in Bit-Synchronizer for incoming data and clock synchronization and recovery RSSI (Received Signal Strength Indicator) and FEI (Frequency Error Indicator)
APPLICATIONS
* * * * * * Narrow-band and wide-band security systems Voice and data over an RF link Process and building control Access control Home automation Home appliances interconnection
ORDERING INFORMATION
Part number XE1202I027 Temperature range -40C to +85 Package LQFP44
Coo l Solu tion s f or Wir eles s Con nec ti vit y
XEMICS SA * e-mail: info@xemics.com * web: www.xemics.com
VSSA
VSS
Data Sheet XE1202 Table of Contents General Description.................................................................................................................................................. 1 Applications .............................................................................................................................................................. 1 Key product features ................................................................................................................................................ 1 Ordering information................................................................................................................................................. 1 1 Functional Block Diagram .............................................................................................................................. 3 2 Pin description ................................................................................................................................................ 4 3 Electrical Characteristics ............................................................................................................................... 5 3.1 Absolute Maximum Operating Ranges.......................................................................................................... 5 3.2 Specifications................................................................................................................................................. 5 3.2.1 Operating Range .......................................................................................................................................... 5 3.2.2 Electrical Specifications ................................................................................................................................ 5 4 Description....................................................................................................................................................... 7 4.1 Detailed description ....................................................................................................................................... 8 4.1.1 Receiver........................................................................................................................................................ 8 4.1.2 High sensitivity vs. high linearity: A-mode, B-mode...................................................................................... 8 4.1.3 RSSI.............................................................................................................................................................. 8 4.1.4 Frequency Error Indicator - FEI .................................................................................................................... 9 4.1.5 Transmitter.................................................................................................................................................. 11 4.1.6 Pattern recognition...................................................................................................................................... 12 4.1.7 Clock Output for external processor ........................................................................................................... 12 5 Interface definition, Principles of operation ............................................................................................... 13 5.1 Serial Control Interface ................................................................................................................................ 13 5.2 Configuration and Status registers .............................................................................................................. 14 5.2.1 RTParam configuration register.................................................................................................................. 14 5.2.2 FSParam configuration register .................................................................................................................. 15 5.2.3 DataOut register ......................................................................................................................................... 16 5.2.4 ADParam configuration register ................................................................................................................. 17 5.2.5 Pattern register ........................................................................................................................................... 18 5.3 Operating Modes ......................................................................................................................................... 19 5.3.1 Standard power up sequence for the receiver and transmitter .................................................................. 19 5.3.2 Single step sequence for the receiver ........................................................................................................ 21 5.4 Transmitted Data Interface .......................................................................................................................... 21 5.5 Received Data Interface .............................................................................................................................. 21 5.6 Pattern Recognition Interface ...................................................................................................................... 21 5.7 Clock Output Interface ................................................................................................................................. 22 5.8 Default settings at power-up........................................................................................................................ 22 6 Application Information ................................................................................................................................ 23 6.1 Matching network of the receiver................................................................................................................. 23 6.2 Matching network of the transmitter ............................................................................................................ 23 6.3 VCO tank ..................................................................................................................................................... 24 6.4 Loop filter of the frequency synthesizer....................................................................................................... 24 6.5 Reference crystal for the frequency synthesizer ......................................................................................... 25 6.6 Decoupling capacitances............................................................................................................................. 25 7 Packaging information.................................................................................................................................. 26
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Data Sheet XE1202 The XE1202 single-chip solution is an integrated circuit intended for use as a low cost FSK transceiver to establish a frequency-agile, half-duplex, bi-directional RF link, with non-return to zero data coding. The device is available in an LQFP44 package and is designed to provide a fully functional multi-channel FSK transceiver. It is intended for applications in the 433- and 868MHz European band and the North American 902-928MHz ISM band. The single chip transceiver operates down to 2.7 V and provides low power consumption solutions for battery-operated and power sensitive applications. Thanks to the low external components count, the XE1202 is ideal for small size, lowcost UHF links. Its reference board design has no tunable components, which facilitates high volume cost sensitive production. The XE1202 can easily be interfaced to a controller such as the XEMICS' XE8000 Series of ultra low-power microcontrollers. The XE1202 serial control registers are programmed by the MCU and the MCU manages the communication protocol.
1 Functional Block Diagram
QAMP VDDD VDDF VDDP IAMP VDDA VDD
IAmp
QAmp SCAN
I RFA LNA RFB Q
AMP
BPF
AMP
Limiter DCLK FSK Demod. Bit Sync. DATAOUT
AMP
BPF
AMP
Limiter
Pattern Recognition LO Buff. Phase Shifter Prog. divider RSSI FEI
PATTERN MODE 0 MODE 1
Control Logic modulator /n Synthesizer POR Oscillator /n Clock Out I Ref
MODE 2 SI SO
RFOUT
PA
VCO
PFD
SCK EN
DATAIN
VSSD
VSSF
VSSF
VSSP
VSSP
CLKOUT
TSUPP
TKA
TKB
XTA
XTB
LFB
TVCO
VSSA
3
VSSA
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VSS
Data Sheet XE1202
2 Pin description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 NAME MODE(1) MODE(0) EN VSSF RFA RFB VSSP VSSP RFOUT VDDP TVCO VDD TKA TKB VSSF LFB VDDD VSSD TSUPP SCAN OPT TMOD[0] TMOD[1] VSSA XTA VSSA XTB VDDA QAMP IAMP TMOD[2] TMOD[3] TIBIAS VDD SO SI SCK CLKOUT VSS DCLK DATAOUT DATAIN PATTERN MODE(2) In In In In In In In Out In I/O I/O I/O DESCRIPTION Transmit/Receive/Stand-by/Sleep Mode Select Transmit/Receive/Stand-by/Sleep Mode Select Chip Enable HF Analog Ground RF Input RF Input Power Amplifier Ground Power Amplifier Ground RF Output Power Amplifier Supply Voltage Test Input (connected to VSS in normal operation) HF Analog Supply Voltage VCO Tank VCO Tank HF Analog Ground PLL Loop Filter HF Digital Supply Voltage HF Digital Ground Test Circuit Supply Voltage (connected to VSS in normal operation) Scan Test Input (connected to VSS in normal operation) (connected to VSS in normal operation) (connected to VSS in normal operation) (connected to VSS in normal operation) LF Analog Ground
Ref Xtal / Input of external clock
In
I/O I/O Out Out
LF Analog Ground Reference Xtal LF Analog Supply Voltage
Output of Q low-pass filter Output of I low-pass filter
Out In In Out Out Out In Out In
(connected to VSS in normal operation) (connected to VSS in normal operation) (connected to VSS in normal operation) LF Digital Supply Voltage Configuration Register Serial Output Configuration Register Serial Input Configuration Register Serial Clock
Output clock at reference frequency divided by 4, 8, 16 or 32
LF Digital Ground Recovered Received Data Clock Received Data Transmit Data
Output of the pattern recognition block
Transmit/Receive/Stand-by/Sleep Mode Select
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Data Sheet XE1202
3 Electrical Characteristics
3.1 Absolute Maximum Operating Ranges
Stresses above those values listed below may cause permanent device failure. Exposure to absolute maximum ratings for extended periods may affect device reliability. Symbol VDDmr Tmr Description Supply voltage Storage temperature Min. -0.5 -55 Max. 3.9 125 Unit V C
3.2
3.2.1
Specifications
Operating Range Symbol VDDop TRop CLop Description Supply voltage Temperature Load capacitance on digital ports Min. 2.7 -40 Max. 3.6 85 25 Unit V C pF
3.2.2 Electrical Specifications The table below gives the electrical specifications of the transceiver under the following conditions: Supply Voltage = 3.3 V, temperature = 25 C, 2-level FSK without pre-filtering, fc = 915 MHz, f = 5 kHz, Bit rate = 4.8 kb/s, BWSSB = 10 kHz, BER = 1 % (at the output of the bit synchronizer), matched impedances, environment as defined in section 6, unless otherwise specified. Symbol IDDSL IDDST IDDR IDDT RFS FDA Description Supply current in sleep mode Supply current in standby mode Supply current in receiver mode Supply current in transmitter mode RF sensitivity Frequency deviation 3.2.2.1 3.2.2.2 RFOP = 5 dBm RFOP = 15 dBm A-mode B-mode Quartz oscillator (39 MHz) running Conditions Min -13 funw = fLO + 50 kHz and fLO + 95 kHz A-mode B-mode Typ 0.2 0.85 14 33 48 -113 -102 5 10 20 40 100 -10 Max 1 1.10 16.5 40 59 -110 -99 Unit A mA mA mA mA dBm dBm kHz kHz kHz kHz kHz dBc
Programmable
CCR IIP3
Co-channel rejection Input intercept point (from LNA input to base-band filter output)
-43 -28
-40 -25
-
dBm dBm
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Data Sheet XE1202 Symbol ML BW Description Receiver input level Base band filter bandwidth Programmable Conditions Min 45 RFOP10 RFOP1 RFOP20 RFOP2 FR Synthesizer frequency range Programmable Each range with its own external components From quartz oscillator running From frequency synthesizer running From frequency synthesizer running "RTParam_WBB" = 1 From quartz oscillator running From frequency synthesizer running
RTParam_WBB=0
Typ 10 20 40 200 48 4.8 9.6 19.2 38.4 76.8 0 +5 +10 +15 200 100 3.5
Max -20 435 870 928 250 150 4.5
Unit dBm kHz kHz kHz kHz dBc kb/s kb/s kb/s kb/s kb/s dBm dBm dBm dBm MHz MHz MHz s s ms
ACR BR
Adjacent channel rejection Bit rate
funw = fLO + 65 kHz Pw=-107 dBm, A-mode Programmable
RFOP
RF output power
Programmable -3 +2 +7 +12 433 868 902 -
TS_BBR TS_TR TS_BB0
Receiver BB processing wake-up time (first step) Transmitter wake-up time Receiver RF Front-End wake-up time Frequency synthesizer wakeup time Receiver RF Front-End wake-up time Frequency synthesizer switching time RSSI wake-up time Quartz oscillator wake-up time FEI wake-up time (RTParam_Fsel = 1) or counting duration (RTParam_Fsel = 0)
TS_FS TS_BB2
-
200 500
250 600
s s
TS_FSW TS_RS TS_OS TS_FE
Between 2 channels at 1 MHz from each other From whole receiver running in mode 100 From receiver running RTParam_Fsel = 1 RTParam_Fsel = 0
100 -
150 1.5 2
s ms ms
-
39 500
20/BR 4/BR -
ms ms MHz Hz
XTAL FSTEP
Quartz oscillator frequency Frequency synthesizer step
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Data Sheet XE1202 Symbol VTHR Description Equivalent input thresholds of the RSSI Conditions A-mode,low range:VTHR1
VTHR2 VTHR3
Min
-
Typ
-105 -100 -95 -90 -85 -80
Max
-
Unit dBm
dBm dBm dBm dBm dBm
A-mode,high range:VTHR1
VTHR2 VTHR3
FERR SPR VIH VIL VOH VOL
Error threshold for the FEI Spurious emission in receiver mode Digital input level high Digital input level low Digital output level high Digital output level low
Pw=-100 dBm, A-mode RTParam_Fsel = 1
-
0.5 -55 -
-50 25 25
dBm % % % %
in % VDD in % VDD in % VDD in % VDD
75 75 -
4 Description
The XE1202 is a direct conversion (0-IF) half-duplex data transceiver. It includes a receiver, a transmitter, a frequency synthesizer and some service blocks. The circuit operates in 3 frequency ranges (433MHz, 868MHz, 915MHz) and uses 2-level FSK modulation. In a typical application, the XE1202 is programmed by a microcontroller through the 3-wire serial bus SI, SO, SCK to write to and read from the configuration registers. The circuit consists of 4 main functional blocks: The receiver converts the incoming 2-level FSK modulated signal into a synchronized bit stream. The receiver is composed of a low-noise amplifier, down-conversion mixers, baseband filters, baseband amplifiers, limiters, demodulator and the bit synchronizer. The bit synchronizer transforms the data output of the demodulator into a glitch-free bit stream DATAOUT and generates a synchronized clock DCLK to be used to easily sample the DATAOUT signal without loading an external processor with heavy signal processing. In addition, the receiver includes a Received Signal Strength Indicator function (RSSI), a Frequency Error Indicator function (FEI) that gives indication about the frequency error of the local oscillator, and pattern recognition function to detect programmable reference word in the incoming bit stream. The bandwidth of the base-band filters, the frequency deviation of the expected incoming FSK signal as well as the bitrate of this bit stream are programmable. The transmitter performs the modulation of the carrier by an input bit stream and the transmission of the modulated signal. The modulation is made directly through the frequency synthesizer. An on-chip power amplifier then amplifies the signal. The output power is programmable among 4 possible values. The frequency deviation and the bit rate for the transmit signal are the same as those programmed for the receiver section. The frequency synthesizer generates the local oscillator (LO) signal for the receiver section as well as the FSK modulated signal for the transmitter section. The core of the synthesizer is implemented with a PLL structure. The frequency is programmable with a step of 500 Hz in 3 frequency bands, 433-, 868-, and 915-MHz. This section includes a crystal oscillator whose signal is the reference for the PLL. This reference frequency is divided by 4, 8, 16, or 32 and is made available at the CLKOUT pin to serve as a clock signal for an external processor. The control block generates the control signals according to the setting in its set of configuration registers. The service block performs all the necessary functions for the circuit to work properly, including the internal voltage and current sources.
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Data Sheet XE1202
4.1
Detailed description
4.1.1 Receiver The outputs of the receiver are the two signals DATAOUT and DCLK. When the bit "RTParam_Bits" is "1" (see the Configuration register section below), the bit synchronizer is turned on, and the two output signals are respectively the output NRZ bit stream and the sampling clock. The function of the bit synchronizer is to remove the glitches from the bit stream DATAOUT and to provide the output clock DCLK. The value of DATAOUT is valid at the rising edge of DCLK. For proper behavior of the bit synchronizer, three conditions must be satisfied: - the received data must start with a preamble of 24 bits for synchronization; this preamble must be a sequence of "0" and "1" sent alternatively, - after that, the incoming bit stream must have at least one transition from "0" to "1" or from "1" to "0" every 8 bits, the accuracy of the bit rate must be better than 5 % (assuming the reference Xtal oscillator is exactly 39 MHz)
When "RTParam_Bits" is "0", the bit synchronizer is turned off, and the signal DATAOUT is the output of the demodulator. In this case DCLK is not used and its value is set to "low". The condition on the modulation index for proper behavior of the demodulator is: 2 f = 2, BR where f is the frequency deviation and BR the bit rate.
4.1.2 High sensitivity vs. high linearity: A-mode, B-mode The receiver can be operated in two different modes that provide the highest sensitivity or the highest linearity. This is programmable with the register "RTParam_Rmode" (see the Configuration register section below). A-mode: the receiver has the highest sensitivity (see RFS parameter) B-mode: the receiver has the highest linearity (see IIP3 parameter)
4.1.3 RSSI When activated, this function provides a Received Signal Strength Indication based on the signal at the output of the base-band filter. To activate this function, the bit "RTParam_RSSI" (see the Configuration register section below) must be set "1". When activated, the status is a 2-bits data stored in register "DataOut_RSSI", which can be read through the serial control interface. The meaning of this status information is given in the table below, where VRFFIL is the differential amplitude of the equivalent input RF signal when the receiver is operated in A-mode. The thresholds VTHRi are the thresholds at the output of the base-band filter divided by the gain between the input of the receiver and this output. DataOut_RSSI 00 01 10 11 Description VRFFIL VTHR1 VTHR1 < VRFFIL VTHR2 VTHR2 < VRFFIL VTHR3 VTHR3 < VRFFIL
Table 1 RSSI status description
Two ranges with three VTHRi are defined and selected with the flag "RTParam_RSSR". The time diagram of an RSSI measurement is given in the next figure. When the RSSI function has been activated the signal strength is periodically measured and the result is stored in the register "DataOut_RSSI" at each rising edge of the DATAIN. TS_RS is the wake-up time required after the function has been activated to get a valid result.
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Data Sheet XE1202
RTParam_RSSI
en
rssi_out
XX
VAL1
VAL2
VAL3
VAL4
XX
datain
DataOut_RSSI
XX
VAL2
VAL4
TS_RS
Figure 1 RSSI measurement timing diagram For applications where the time needed to get the first right result from the RSSI has to be as low as possible, this time can be minimized by waking up the RSSI during mode 010 instead of 100 which is the condition for the definition of TS_RS in page 6 (for definition of modes, see pages 19 and 20). 4.1.4 Frequency Error Indicator - FEI When activated, this function provides information about the frequency error of the local oscillator compared with the input carrier frequency. The condition on the modulation index for proper behavior of the FEI function is: 2 f = 2, BR where f is the frequency deviation and BR is the bit rate. There are 2 modes of operation for this function selected by the bit "RTParam_Fsel" (see the Configuration register section below). IMPORTANT NOTE To guarantee proper behavior of the FEI, the sum of frequency offset and the signal bandwidth (ssb) should be lower than the baseband filter bandwidth (single sided). That is foffset + SignalBW < Baseband_filterBW where foffset is the difference between the carrier frequency and the LO frequency, SignalBW is the signal bandwidth (single sided) equal to the sum of the bitrate divided by 2 and the frequency deviation (Bitrate/2 + Frequency Deviation), and Baseband_filterBW is the channel filter bandwidth defined by the RTParam_BW parameter (see the Configuration Registers section below). 4.1.4.1 "RTParam_Fsel" = 1 To activate the FEI function, the bit "RTParam_FEI" must be set to "1". When activated, the function provides a 2bits status stored in register "DataOut_FEI". The meaning of this output is given in the following table, where fLO is the internal local oscillator frequency, and fRF is the carrier frequency of the received signal. DataOut_FEI 00 01 10 11 Meaning fLO-fRF fERR (fLO-fRF) > fERR (fLO-fRF) < -fERR
Table 2 FEI status description
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Data Sheet XE1202 The threshold fERR = FERR * BR, where BR is the bit rate and FERR is a ratio given in the electrical specifications. As an example, for a bit rate of 4.8 kb/s and with FERR = 0.5, fERR is 2.4 kHz. This FEI function works properly only if the input signal is the preamble defined under the Receiver section above and if the frequency error to be detected is lower than 20 kHz. The time diagram of an FEI measurement is quite similar to the one of an RSSI measurement, and is given in the figure below. When the FEI is activated the frequency error is periodically measured and the result is stored in the register "DataOut_FEI" at each rising edge of DATAIN. TS_FE is the wake-up time required after the function has been activated to get a valid result.
RTParam_FEI
en
fei_out
XX
VAL1
VAL2
VAL3
VAL4
XX
datain
DataOut_FEI
XX
VAL2
VAL4
TS_FE
Figure 2 FEI measurement time diagram, RTParam_Fsel = 1
4.1.4.2 "RTParam_Fsel" = 0 To activate the FEI function, the bit "RTParam_FEI" must be set to "1". When activated by the rising edge of DATAIN, the function provides an 8-bits status stored in register "DataOut_FEI". The timing diagram of this FEI measurement is described in the in figure below. The FEI function is activated at the rising edge of the EN signal when the RTParam_FEI bit is set to "1". Then, an internal FEI counter is activated at the rising edge of DATAIN. After duration TS_FE (see Electrical Specifications), the counter is stopped and its content is stored in the register DataOut_FEI. The maximum delay between the rising edge of DATAIN and the first clock on the internal FEI counter is 1/(16*BR), where BR is the bit rate.
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Data Sheet XE1202
RTParam_FEI
en
Demodulated ffdemod_out data
BIT B0
BIT B0+1
BIT B0+2
BIT B0+3
BIT B0+4
datain
counter_out
0
N
DataOut_FEI
X
N
TS_FE
Figure 3 Time diagram of an FEI measurement when "RTParam_Fsel" = 0 (the number of transitions on "counter_out" is for illustration only)
4.1.5 Transmitter The output power of the power amplifier is programmable on four values with the register "RTParam_Tpow" (see the Configuration register section below), as shown in the table below, where RFOPi are given in Electrical Specifications section RTParam_Tpow 00 01 10 11 Output power RFOP10 RFOP1 RFOP20 RFOP2
The type of modulation of the LO frequency by the modulating bit stream is programmable through RTParam_Filter: - the input bit stream is directly applied to the frequency synthesizer without any pre-filtering (RTParam_Filter=0) - the input bit stream is pre-filtered before being applied to the frequency synthesizer; with this filtering, each edge of the bit stream is linearly smoothed with a staircase transition (RTParam_Filter=1) This is illustrated on the next page where DATAIN is the input bit stream to be transmitted.
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Data Sheet XE1202
tbit
datain
no filtering IN freq_synth
staircase filtering IN freq_synth
trise
Figure 4 Modulation without and with pre-filtering
The characteristic of the smoothing filter is the ratio trise/tbit. The value of this ratio is programmable with the register "RTParam_Stair", as shown in the following table. FSParam_Stair 0 1 trise/tbit 10 % 20 %
4.1.6 Pattern recognition XE1202 includes a pattern recognition function. When "ADParam_Pattern" (see the Configuration register section below) is set to "1" this feature is turned on, provided the bit synchronizer is turned on too (the pattern recognition feature doesn't work if the bit synchronizer is turned off). In this case, the incoming NRZ bit stream is compared with a pattern stored in the "Pattern" register. The length of this pattern can be 8, 16, 24, or 32 bits, as defined by "ADParam_Psize". When comparing the streams 0, 1, 2, or 3 errors, as defined by "ADParam_Psize" can be allowed to detect a match. The PATTERN output is driven by the output of this comparator. It is "high" when a match is detected, otherwise "low". When the feature is disabled, the PATTERN output is set to "low"
4.1.7 Clock Output for external processor When "RTParam_Clkout" is set high, a frequency divider by 4, 8, 16, or 32, depending on "ADParam_Clkfreq" (see the Configuration register section below), is embedded in XE1202 and provides the CLKOUT clock signal for an MCU or an external circuitry. The input frequency is the 39.0 MHz reference frequency, so the possible clocks available on CLKOUT are 1.22, 2.44, 4.87, or 9.75 MHz. When the XE1202 is in Sleep Mode (MODE[2:0] = 000), this clock is stopped. 12 D0211-105
Data Sheet XE1202
5 Interface definition, Principles of operation
5.1 Serial Control Interface
A 3-wire bi-directional bus (SCK, SI, SO) is used to program the XE1202 and read data from it. SCK and SI are input signals, for example generated by a microcontroller. SO is an output signal controlled by the XE1202. In write mode, at the falling edge of the SCK signal, the logic data on the SI line is written into an internal shift register. In read mode, at the rising edge of the SCK signal, the data on the SO line become valid and should be sampled at the next falling edge of SCK. The signal EN must be low during the whole write and read sequences. In write mode the actual content of the configuration register is updated at the rising edge of the EN signal. Before this, the new data is stored in temporary registers whose content does not affect the transceiver settings. The time diagram of a write sequence is given in the figure below. The sequence is initiated when a Start condition is detected, that is when the SI signal is set to "0" during a period of SCK. The next bit is a read/write (R/W) bit which should be "0" to indicate a write operation. The next 5 bits are the address of the control register A[4:0] to be accessed, MSB first. Then, the next 8 bits are the data to be written in the register. The sequence ends with 2 stop bits set to "1". The data on SI should change at the rising edges of SCK, and are sampled at the falling edge of SCK. After the 2 stop bits, the data transfer is terminated, even if the SI line stays at "1". After this the SI line should be at "1" for at least one clock cycle on SCK before a new write or read sequence can start. In doing this, users can write multiple registers in raw, there is no need to raise the EN signal in between. The duty cycle of SCK must be between 40 % and 60 % and the maximum frequency of this signal is 1 MHz. Over the operating supply and temperature range, set-up and hold time for SI on the falling edge of SCK are 200ns.
SCK SI SO EN
Figure 5 Write sequence into configuration register
START R/W
A(4)
A(1)
A(0)
D(7)
D(6)
D(3)
D(2)
D(1)
D(0)
STOP
STOP
The time diagram of a read sequence is given in figure below. The sequence is initiated when a Start condition is detected, that is when the SI signal is set to "0" during a period of SCK. The next bit is a read/write (R/W) bit which should be "1" to indicate a read operation. The next 5 bits are the address of the control register A[4:0] to be accessed, MSB first. Then the data from the register are transmitted on the SO pin. The data become valid at the rising edges of SCK and should be sampled at the falling edge of SCK. After this the data transfer is terminated. The SI line must stay high for at least one clock cycle on SCK to start a new write or read sequence. The maximum current drive on SO is 2mA @ 2.7V, the maximum load is CLop.
SCK
SI
START
R/W
A(4)
A(0)
SO EN
D(7)
D(6)
D(5)
D(4)
D(3)
D(2)
D(1)
D(0)
Figure 6 Read sequence into configuration register
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Data Sheet XE1202 When the serial interface is not used for read or write operations, both SCK and SI should be set to "1". Except in read mode, SO is set to "0".
5.2
Configuration and Status registers
XE1202 has a series of configuration registers programmable through the serial control interface described above. Their name, size, address and description are listed in the table below. The size of these registers is 1, 2, 3, or 4 bytes. Their byte address is 5 bit address, A[4:0]. In addition, there is one register, DataOut, from which users can read various transceiver status information. Name RTParam FSParam Size 2 x 8 bit 3 x 8 bit Byte Address 00000 00001 00010 00011 00100 00101 00110 00 111 01000 01001 01010 01011 Description Receiver and transmitter parameters registers Frequency parameters
DataOut ADParam Pattern
1 x 8 bit 2 x 8 bit 4 x 8 bit
Transceiver data register Additional parameters Reference pattern for the "pattern recognition" function
In addition, 16 bytes at addresses A[4:0] = 10000 to 11111 are reserved for test purpose Name Test Size 16 x 8 bit Byte Address 10000 to 11111 Description Test registers (reserved)
All the bits that are referred as "reserved" in this section should be set to "0". 5.2.1 RTParam configuration register Name RTParam_Rmode Bits 7 Byte Address 00000 Description Receiver modes: 0 -> A-mode (high sensitivity) 1 -> B-mode (high linearity) Bit synchronizer on/off: 0 -> off; 1 -> on RSSI on/off: 0 -> off; 1 -> on FEI on/off: 0 -> off; 1 -> on Bandwidth of the BB filter: 0 0 -> 10 kHz 0 1 -> 20 kHz 1 0 -> 40 kHz 1 1 -> 200 kHz
RTParam_Bits RTParam_RSSI RTParam_FEI RTParam_BW
6 5 4 3-2
00000 00000 00000 00000
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Data Sheet XE1202 Name RTParam_Tpow Bits 1-0 Byte Address 00000 Description Transmitter output power: 0 0 -> 0 dBm 0 1 -> 5 dBm 1 0 -> 10 dBm 1 1 -> 15 dBm Source for the reference frequency: 0 -> on-chip crystal oscillator 1 -> external signal Receiver wake-up type selection 0 -> "Boost" power up sequence 1 -> Standard power-up sequence Pre-filtering of bit stream in transmitter mode: 0 -> no filtering; 1 -> filtering Selection of the FEI block: 0 -> FEI uses FFD demodulator 1 -> FEI uses correlators Rise and fall time when RTParam_Filter = 1: 0 -> 10 % of bit duration 1 -> 20 % of bit duration Inhibition of the modulation in transmitter mode: 0 -> modulation; 1 -> no modulation Range of the RSSI: 0 -> low range; 1 -> high range Enable CLKOUT output: 0 -> no signal on pad CLKOUT 1 -> clock signal available on CLKOUT at 9.75 down to 1.22 MHz (39MHz divided by 4, 8, 16 or 32)
RTParam_Osc
7
00001
RTParam_WBB
6
00001
RTParam_Filter
5
00001
RTParam_Fsel
4
00001
RTParam_Stair
3
00001
RTParam_Modul
2
00001
RTParam_RSSR RTParam_Clkout
1 0
00001 00001
5.2.2
FSParam configuration register Name FSParam_Band Bits 7-6 Byte Address 00010 Description Frequency band: 0 0 -> not valid 0 1 -> 433 - 435 MHz 1 0 -> 868 - 870 MHz 1 1 -> 902 - 928 MHz Frequency deviation: 0 0 0 -> 5 kHz 0 0 1 -> 10 kHz 0 1 0 -> 20 kHz 0 1 1 -> 40 kHz 1 0 0 -> 100 kHz D0211-105
FSParam_Dev
5-3
00010
15
Data Sheet XE1202 Name FSParam_BR Bits 2-0 Byte Address 00010 Description Bit rate: 0 0 0 -> 4.8 kb/s 0 0 1 -> 9.6 kb/s 0 1 0 -> 19.2 kb/s 0 1 1 -> 38.4 kb/s 1 0 0 -> 76.8 kb/s others -> not valid LO frequency in 2's-complement representation: 00...0 -> fLO = middle of the range 0X...X -> fLO = higher than the middle of the range 1X...X -> fLO = lower than the middle of the range MSB = bit 7 of byte at pos. 00011 LSB = bit 0 of byte at pos. 00100
See example below
FSParam_Freq
7-0 7-0
00011 00100
Example of LO frequency setting in FSParam_Freq Byte Address 00011 Bit 7 Bit 0 Byte Address 00100 Bit 7 Bit 0 Resulting LO setting
Note: reference frequency = 39.0 MHz
00000000
00000000
F0, where F0 depends on the selected frequency band (see FSParam_Band ) F0 = 434.0 MHz for the 433-435 MHz band F0 = 869.0 MHz for the 868-870 MHz band F0 = 915.0 MHz for the 902-928 MHz band F0 + 500 Hz F0 + 2 * 500 Hz F0 - 500 Hz F0 - 2 * 500 Hz
00000000 00000000 11111111 11111111 5.2.3 DataOut register Name DataOut_RSSI Bits 7-6
00000001 00000010 11111111 11111110
Byte Address 00101
Description RSSI output: 0 0 -> lowest level 0 1 -> 2nd level 1 0 -> 3rd level 1 1 -> highest level FEI output: Output of the up/down counter in 2's-complement representation MSB = bit 7
DataOut_FEI When RTParam_Fsel = 0
7-0
00101
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Data Sheet XE1202 Name DataOut_FEI When RTParam_Fsel = 1 Bits 5-4 Byte Address 00101 Description FEI output: 0 0 -> frequency OK 1 0 -> frequency too low 1 1 -> frequency too high
5.2.4
ADParam configuration register Name ADParam_Pattern Bits 7 Byte Address 00110 Description Pattern recognition on/off: 0 -> off 1 -> on Size of the reference for pattern recognition: 0 0 -> 8 bits 0 1 -> 16 bits 1 0 -> 24 bits 1 1 -> 32 bits Number of tolerated errors for the pattern recognition: 0 0 -> 0 error 0 1 -> 1 error 1 0 -> 2 errors 1 1 -> 3 errors Frequency on CLKOUT: 0 0 -> 1.22 MHz (div. ratio: 32) 0 1 -> 2.44 MHz (div. ratio: 16) 1 0 -> 4.87 MHz (div. ratio: 8) 1 1 -> 9.75 MHz (div. ratio: 4) IQ amplifiers on/off: 0 -> off 1 -> on Reserved. Should be set to "0" Inversion of the output data of the receiver: 0 -> non-inverted data 1 -> inverted data Regulation of the bandwidth of the base-band filter on/off: 0 -> on 1 -> off Periodicity of regulation of the bandwidth of the base-band filter: 0 -> only at start-up of the receiver 1 -> each 1 minute as long as the receiver is on
ADParam_Psize
6-5
00110
ADParam_Ptol
4-3
00110
ADParam_Clkfreq
2-1
00110
ADParam_IQA
0
00110
ADParam_Res1 ADParam_Invert
7 6
00111 00111
ADParam_RegBW
5
00111
ADParam_Regfreq
4
00111
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Data Sheet XE1202 Name ADParam_Regcond Bits 3 Byte Address 00111 Description Regulation process of the bandwidth of the base-band filter according to the selected bandwidth: 0 -> regulation restarted each time the bandwidth is changed 1 -> no regulation started when bandwidth is changed Boosting process of the base-band filter according to the selected bandwidth: 0 -> boosting restarted each time the bandwidth is changed 1 -> no boosting started when bandwidth is changed Selection of the XOSC modes: 0 -> CL + C0 = 15 pF 1 -> CL + C0 = 11 pF, lower current consumption mode Reserved
ADParam_WBBcond
2
00111
ADParam_Xsel
1
00111
ADParam_Res2
0
00111
5.2.5 Pattern register In this register, users can store a reference pattern of 8, 16, 24, or 32 bits (see ADParam_Psize parameter). The first byte of this pattern is always stored in the byte at address A[4:0] = 01000. If used, the 2nd byte is stored at address A[4:0] = 01001, and so on. The MSB bit of the reference pattern is always the bit 7 of the address 01000 and the LSB bit is the bit 0 of the address 01000, 01001, 01010, or 01011 if the pattern length is 8, resp. 16, 24, or 32 bits. When compared to the demodulated bit stream, the last bit received is compared to the LSB bit in the Pattern register. The "oldest" bit received (the first of the last 8, 16, 24, or 32 received bits, depending on ADParam_Psize) is compared with the bit 7 of byte address 01000 (the MSB). Name Pattern Bits 7-0 Byte Address 01000 01001 01010 01011 Description 1st byte of the reference pattern 2nd byte 3rd byte 4th byte
Example of pattern recognition with a 32-bit pattern Byte Address 01000 Bit 7 Bit 0 10010011 101 10010011 Byte Address 01001 Bit 7 Bit 0 10101010 10101010 previous bits from demodulator Byte Address 01010 Bit 7 Bit 0 10010011 10010011 Byte Address 01011 Bit 7 Bit 0 10101010 10101010 last bit received
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Data Sheet XE1202 Example of pattern recognition with an 8-bit pattern Byte Address 01000 Bit 7 Bit 0 10010011 101 10010011 previous bits from demodulator last bit received Byte Address 01001 Bit 7 Bit 0 xxxxxxxx Byte Address 01010 Bit 7 Bit 0 xxxxxxxx Byte Address 01011 Bit 7 Bit 0 xxxxxxxx
5.3
Operating Modes
The XE1202 has 4 main operating modes as set by the MODE[2:0] inputs and illustrated in table below. To switch between modes, the new value of the inputs MODE[2:0] should be modified when the EN signal is low. The actual change will be applied to the transceiver upon the rising edge of the EN signal. Over the operating supply and temperature range, set-up and hold time for MODE[2:0] on the rising edge of EN are 200ns, while the negative pulse duration on EN is 2s minimum.
MODE[2:0] EN
Transceiver in Mode XXX Transceiver in Mode YXY XXX YXY
Name Sleep mode Standby mode Receiver mode Transmitter mode
MODE(2:0) 000 001 100 111
Description Reference Xtal oscillator running Ref Xtal oscillator, Frequency synthesizer, Receiver running Ref Xtal oscillator, Frequency synthesizer, Transmitter running
Table 3 XE1202 Main operating modes
5.3.1 Standard power up sequence for the receiver and transmitter 3 additional operating modes are defined and should be used when the transceiver is switched from the standby mode to the receiver or transmitter mode. These additional operating modes are illustrated in Table 4 below Name Receiver mode MODE(2:0) 010 011 Transmitter mode 110 Description Ref Xtal oscillator, Baseband running (first step) Ref Xtal oscillator, Frequency synthesizer, Baseband running (first step) Ref Xtal oscillator, Frequency synthesizer running
Table 4 XE1202 Additional operating modes
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Data Sheet XE1202
The standard power up sequence from sleep to receiver mode uses a "boost" procedure; this "boost" sequence is selected by setting the RTParam_WBB parameter to "0". The sequence is described in Figure 7 below Mode = 000 - Sleep Mode = 001 - Ref Xtal oscillator running Mode = 010 - Baseband - Ref Xtal oscillator running TS_BBR RTParam_WBB =0 Mode = 011 - Frequency synthesizer - Baseband - Ref Xtal oscillator running TS_FS Received data valid Mode = 100 - RF Front End - Frequency synthesizer - Baseband - Ref Xtal oscillator running TS_BB2 Mode=001 - Ref Xtal oscillator running
TS_OS
t
Figure 7 Standard "boosted" power up sequence from Stand By to Receiver Mode
The typical current consumption values during the standard power-up sequence from Stand-by to Receiver Mode is the following RTParam_WBB =0 14.0 mA 11.5 mA 3.0 mA 0.85 mA <1 uA Mode= 000 Mode= 001 TS_OS Mode=010 TS_BBR Mode =011 TS_FS Mode = 100 TS_BB2 t
Figure 8 Typical current consumption profile during a standard "boosted" power up sequence from Stand By to Receiver Mode
The standard power up sequence from sleep to transmit mode is described in Figure 9 below Transmission Mode = 000 - Sleep Mode = 001 - Ref Xtal oscillator running Mode = 110 - Frequency synthesizer - Ref Xtal oscillator running TS_FS Mode =111 - Power Amplifier - Frequency synthesizer - Ref Xtal oscillator running TS_TR Mode=001 - Ref Xtal oscillator running
TS_OS
t
Figure 9 Standard power up sequence from Stand by to Transmit Mode
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Data Sheet XE1202
5.3.2 Single step sequence for the receiver By programming RTParam_WBB to "1", the boost procedure is inhibited. In this case, the wake-up time is longer (TS_BB2 is
replaced by TS_BB0 whose value is given in the electrical specifications).
5.4
Transmitted Data Interface
When in transmit mode (MODE[2:0] = 111), the DATAIN signal is used as input for the on-chip modulator. DATAIN is not sampled, so the bit duration should match the bit rate setting of the receiver. Whenever XE1202 are used on both sides of the communication link, the bit rate should be one of those defined in the specifications table (BR). In this case the bit rate error should be less than 5% compared to the specified value.
DATAIN (NRZ)
BIT N 1/BR
BIT N+1
5.5
Received Data Interface
The outputs of the receiver are the two signals DATAOUT and DCLK. When the bit "RTParam_Bits" is "1", the bit synchronizer is turned on, and the two output signals are respectively the output NRZ bit stream and the sampling clock. The value of DATAOUT is valid at the rising edge of DCLK (see below).
DATAOUT (NRZ) DCLK
BIT N
BIT N+1
When "RTParam_Bits" is "0", the bit synchronizer is turned off, and the signal DATAOUT is the output of the demodulator. In this case DCLK is not used and its value is set to "low". The maximum current drive on DATAOUT and DCLK is 2mA @ 2.7V, the maximum load is Clop.
5.6
Pattern Recognition Interface
When this feature is turned on, the incoming NRZ bit stream is compared with a pattern stored in the "Pattern" register. The PATTERN output is driven by the output of this comparator and is synchronized by DCK. It is "high" when a match is detected, otherwise "low". Changes occur at the rising edge of DCK
DATAOUT (NRZ) DCLK PATTERN
BIT N-x=PATTERN[x] BIT N-1=PATTERN[1] BIT N=PATTERN[0]
When the feature is disabled, the PATTERN output is set to "low". The maximum current drive on PATTERN is 2mA @ 2.7V, the maximum load is Clop.
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Data Sheet XE1202
5.7
Clock Output Interface
CLKOUT is a clock signal at 1.22, 2.44, 4.87, or 9.75 MHz, depending on programming. When the XE1202 is in Sleep Mode (MODE[2:0] = 000) or when "RTParam_Clkout" is low, this clock is stopped.
5.8
Default settings at power-up
Upon power-up all , RTParam, FSParam, ADParam and Pattern registers are set to 00hex . At power-up, XE1202 is in Stand-by mode, which means that the Xtal oscillator is running; furthermore, the signal at 1.22 MHz (reference frequency divided by 32) is present on pin CLKOUT. However, internally, RTParam_Clkout is low, which means that, if nothing is changed in the configuration register, the signal on CLKOUT will disappear at the first rising edge of EN; furthermore, at this first rising edge of EN, the circuit will be put in the mode corresponding to the signals on pins MODE(2:0) at this moment. Thus, to keep the circuit in Standy-by mode and the clock signal present on CLKOUT, RTParam_Clkout has to be set high during the first communication through the 3-wire bus, and the MODE(0) has to be set high before the first rising edge of EN. It is strongly recommended to initialize the XE1202 registers right after power-up according to the application needs.
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Data Sheet XE1202
6 Application Information
6.1 Matching network of the receiver
The schematic of the matching network at the input of the receiver is given below
CR1
SOURCE
RFA LR1
EAGLE ASIC XE1202
CR3
RFB CR2 VSS
The components of the network have to satisfy the conditions given in the following table. Name CR1 CR2 CR3 (optional) LR1 Min. value 0.8 pF 0.8 pF 8 nH Typ. value Min. Q-factor @ selected frequency range 200 200 30 Tolerance 2% 2% 5%
6.2
Matching network of the transmitter
The schematic of the matching network at the output of the transmitter is given below.
VDD
XE1202
CR1 LR2
OUTPUT
LR1 RFOUT
CR2
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Data Sheet XE1202 The components of the network have to satisfy the following conditions: Name CR1 CR2 LR1 LR2 (optional) Min. value 0.8 pF 0.8 pF 8 nH Typ. value Min. Q-factor @ selected frequency range 200 200 30 Tolerance 2% 2% 5%
6.3
VCO tank
The tank of the VCO will be implemented with one inductor in parallel with one capacitor. The characteristics of these two components must be as follows: Name CV1 LV1 Min. value 0.8 pF 8 nH Typ. value Min. Q-factor @ selected frequency range 200 30 Tolerance 2% 5%
6.4
Loop filter of the frequency synthesizer
The loop filter of the frequency synthesizer is shown below.
LFB RL1 CL2 CL1
EAGLE ASIC XE1202
VSS
The components of the filter have to satisfy the following conditions: Name CL1 CL2 RL1 Min. value 0.8 pF 0.8 pF 1 k Typ. value Min. Q-factor @ selected frequency range 200 200 Tolerance 2% 2% 2%
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Data Sheet XE1202
6.5
Reference crystal for the frequency synthesizer
For narrow band applications, where users select the lowest frequency deviation and the narrowest baseband filter, the crystal for reference oscillator of the frequency synthesizer must have the following characteristics: Name Fs CL Rm Cm C0 fs(0) fs(T) fs(t) Description Nominal frequency Load capacitance for fs (on-chip) Motional resistance Motional capacitance Shunt capacitance Calibration tolerance at 25 C Stability over temperature range (-40 C to 85 C) Aging tolerance in first 5 years Min. value Typ. value 39.0 MHz (fundamental) 8 pF (*) Max. value 40 30 fF 7 pF (*) 10 ppm 10 ppm 5 ppm
Table 5 Crystal characteristics (*) The on-chip oscillator is implemented in two selectable versions: the first for CL = 8 pF and C0 = 7 pF, and the second for CL = 8 pF and C0 = 3 pF; the latter will allow a higher amplitude for the internal signal with a slightly lower consumption. The electrical specifications given in section 3.2.2 are valid provided the crystal satisfies the specifications given in table 5. For less demanding applications in term of signal bandwidth and/or temperature range, it is possible to use crystal with larger values for fs(0), fs(T), and/or fs(t). In this case foffset + BWssb should be lower than BWfilter, where foffset is the offset (error) on the carrier frequency (the sum of fs(0), fs(T), and/or fs(t)), BWssb is the single side-band bandwidth of the signal, and BWfilter is the single side-band bandwidth of the base-band filter. XE1202 can be used with reference crystal operating on its 3rd harmonic at 39.00 MHz. This has 2 consequences: a) the oscillator start-up time is higher than in fundamental mode; and b) an extra 1.5k to 16k ohm external resistor has to be placed in parallel to the crystal. In this case, the crystal should have Cload = 8 to 10pF, Rm < 60 ohm, C0 < 7pF.
6.6
Decoupling capacitances
A decoupling capacitance will be placed between each VDD pins and the ground VSS. These five capacitances must have the following characteristics: Name Cci Typ. value 100 nF Tolerance 10 %
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Data Sheet XE1202
7 Packaging information
XE1202 comes in 44-lead LQFP package
DATAOUT MODE(2) PATTERN DATAIN DCLK CLKOUT VDD VSS SCK SO
MODE(1) MODE(0) EN VSSF R FA R FB VSSP VSSP RFOUT VDDP TVCO
SI
VSS VSS VSS IAMP Q AMP VDDA XTB VSSA XTA VSSA VSS
TKA
TKB
LFB
TSUPP
VDDF
VSSF
VDDD
VSSD
VSS
XEMICS 2002 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. XEMICS PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF XEMICS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER'S OWN RISK. Should a customer purchase or use XEMICS products for any such unauthorized application, the customer shall indemnify and hold XEMICS and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise.
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SCAN
VSS
D0211-105

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