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SIEMENS Preliminary IC-SPECIFICATION TDA 6060XS, TDA 6060G
Multistandard Modulator / PLL
page
Contents 1 Functional Description, Application 2 Pin Definition and Function 3 Block Diagram 4 Circuit Description 5-10 Pinning, Package 11 Absolute Maximum Ratings 12 Operational Range 13 AC/DC Characteristics 14-18 Test Procedures 19 Equivalent I/O-Schematics 20-24 2C-Bus Timing 25 I Test Circuit Diagram 26 Application Board Circuit Diagram 27
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11.11.1998
V66047-S0894-A100-V3-76D4
page 1
SIEMENS Preliminary IC-SPECIFICATION TDA 6060XS, TDA 6060G
Functional Description, Application Multistandard Modulator / PLL
Functional Description
The TDA 6060XS device combines a digitally programmable phase locked loop (PLL), with a multistandard video modulator and a programmable sound FM and AM modulator. The PLL block with four hard-switched chip addresses forms a digitally programmable phase locked loop. With a 4 MHz quartz crystal, the PLL permits precise setting of the frequency of the modulator oscillator from 30 MHz to 950 MHz in increments of 250 kHz. The tuning process is controlled by a microprocessor via an I2C bus. The device has one output port, which can also be used as an A/D converter input. A flag is set when the loop is locked. The lock flag can be read by the processor via the I2C bus. The modulator block includes a clamped video input amplifier followed by a double balanced mixer as a RF modulator, a frequency and amplitude-stable balanced oscillator for the VHF, Hyper band and the UHF range (with different tank circuits), a digitally programmable sound FM / AM modulator, a second audio carrier input and a low-noise reference voltage source.
Features
* * * * * * * * * * * * * * * * * * Frequency and amplitude-stable balanced oscillator for the VHF, Hyper band and the UHF frequency range Clamped video input with peak white level detection for I2C bus controlled gain setting of the video amplifier Programmable sound carriers 4.5 MHz, 5.5 MHz, 6 MHz, 6.5 MHz Second sound carrier input Balanced RF output Low-noise reference voltage 1-chip system for C control (I2C bus) Fast I2C bus mode possible 4 programmable chip addresses Smallest possible lock-in time; no asynchronous divider stage Short pull-in time for quick channel switch-over and optimized loop stability One high-current switch output 5-level A/D converter Lock-in flag Power-down flag Few external components Package TSSOP 28 5 V supply voltage
Application
The TDA 6060XS is suitable for all modulator boxes The TDA 6060G has modified divider ratio for applications with +125kHz RF frequency offset (e.g. 38.875MHz, N=620+2) and reduced Sound Carrier Levels.
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11.11.1998
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SIEMENS Preliminary IC-SPECIFICATION TDA 6060XS, TDA 6060G
Pin Definitions and Functions
PLL Section PIN No. 5 9 10 11 12 13 14 15 16 17 Symbol CAS GNDD SDA SCL VVCCD Q Qx P2 / ADC CHGPMP VTUNE Chip address select Ground for digital block (PLL) Data input/output for the I2C bus Clock input for the I2C bus Positive supply voltage for digital block (PLL) 4 MHz low-impedance crystal oscillator input 4 MHz low-impedance crystal oscillator input; external oscillator input Port output / ADC input Charge pump output / loop filter Open collector output for pull up resistor / loop filter Function
Multistandard Modulator Section PIN No. 1 2 3 4 6 7 8 18 19 20 21 22 23 24 25 26 27 28 Symbol AudGnd AudinFM AudinAM SC2in Modout1 ModGnd Modout2 T1 O-B1 O-C2 O-C1 O-B2 GNDA Vidin SLF TFLF T2 VVCCA Audio ground Audio input for FM sound IF application Audio input for AM sound IF application Second sound carrier input Modulator output, balanced to pin 8 Modulator output ground Modulator output, balanced to pin 6 Test interface input 1 Oscillator amplifier, high-impedance base input, symmetrical to O-B2 Oscillator amplifier, high-impedance collector output, symmetrical to O-C1 Oscillator amplifier, high-impedance collector output, symmetrical to O-C2 Oscillator amplifier, high-impedance base input, symmetrical to O-B1 Ground for analog block Clamped video input Sound carrier PLL loop filter Tracking filter low pass filter Test interface input 2 Positive supply voltage for analog block Function
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11.11.1998
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SIEMENS Preliminary IC-SPECIFICATION TDA 6060XS, TDA 6060G
Block Diagram
CHGPMP 16
GNDA
O-C1
O-C2
O-B2
O-B1
28
Test Interface
27
26
25
24
23
22
21
20
19
18
P2 / ADC 15
I/O Ref.Divider
VVCCA
VTUNE 17
125kHz
TFLF
SLF
Vidin
T2
T1
Oscillator
PhaseDet.& ChgPmp
Tracking Filter AM Mod Sound Carrier Oscillator FM/AM
Isol. Amp
Isol. Amp
Progr. Divider
Mixer
Video
Test Pattern FM Amp AM Amp Sound carrier input Crystal Oscillator I2C-Bus Interface
1 AudinFM AudGnd
2 AudinAM
3 SC2in
4 CAS
5 Modout1
6 ModGnd
7 Modout2
8 GNDD
9 SDA
10 SCL
11 VVCCD
12 Q
13 Qx
14
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11.11.1998
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page 4
SIEMENS Preliminary IC-SPECIFICATION TDA 6060XS, TDA 6060G
Circuit Descripton
General Description: Modulator block The modulator section includes a gain adjustable video amplifier, a double balanced mixer working as a AM video modulator for positive or negative modulation, a balanced oscillator for VHF, Hyper band and UHF, a sound modulator suitable for FM and AM modulation, a programmable sound carrier oscillator and a reference voltage source. The audio signal is coupled to the gain settable audio pre-amplifier of the FM AF input (AudinFM) and to the AM input amplifier (AudinAM). The pre-emphasis is done with an external circuitry in front of the FM audio input. The FM audio amplifier allows a gain setting in four steps with the AU0 / 1 bits in the negative video modulation mode (PN = 0). The amplified audio signal is fed to the FM modulator. The modulated sound carrier is filtered by a tracked bandpass filter and added to the video signal. In the positve video modulation mode the the audio signal is directly fed to the AM sound modulator. The sound carriers are generated by a programmable on chip oscillator. The four possible frequencies are 4.5, 5.5, 6.0 and 6.5 MHz (2bit). To increase the speed of the sound PLL the loop filter current can be switched to 5I with the audio mode bits (table 4). A second FM or NICAM sound carrier may be added via the input SC2in to the internally generated carrier. The SC2in input is referenced to Audgnd and can be switched off by connecting SC2in to the supply voltage. The positve video signal is capacitively coupled to the video input pin (Vidin). An internal clamping circuit is referenced to the sync tip level. If the video signal exceeds the maximum level the peak white level is clipped. The clipping circuit acts also as a detector and sets a flag (FLV) for the I2C bus. The video input amplifier allows a gain setting in four steps. The polarity of the video signal can be switched for positve or negative modulation. The setting to positve modulation is combined with the AM modulation of the sound carrier. For the residual carrier adjustment a sawtooth test picture is used when the video modulator is in overmodulation mode.This mode is active by conneting test pin T1 to ground. The adjustments of the modulation depth and the picture to sound carrier ratio can be done in four steps. The RF oscillator works as gain controlled LC tuned astable multivibrator. The output of the oscillator is decoupled by two isolation amplifiers, one for the modulator mixer and one for the synthesizer PLL. The VCO can be switched off by setting both audio mode bits to 1 in positive modulation mode (table 4) The added sound carrier and video signals are mixed with the RF oscillator signal in the double balanced mixer and then fed to both RF outputs (Modout1 / Modout2) . PLL and I2C bus The oscillator signal for the RF modulator is internally DC-coupled as a differential signal at the programmable divider inputs. The signal subsequently passes through a programmable divider with ratio N = 256 through 32764 by 4 (TDA 6060G: 258 through 32766 by 4) and is then compared in a digital frequency / phase detector to a reference frequency fref = 62.5 kHz. This frequency is derived from a balanced, low-impedance 4 MHz crystal oscillator (pin Q, Qx) or from a external signal source divided by Q = 64. The phase detector has two outputs UP and DOWN that drive two current sources I+ and I- of a charge pump. If the negative edge of the divided VCO signal appears prior to the negative edge of the reference signal, the I+ current source pulses for the duration of the phase difference. In the reverse case the I- current source pulses. If the two signals are in phase, the charge pump output (CHGPMP) goes into the high-impedance state (PLL is locked). An active low-pass filter integrates the current pulses to generate the tuning voltage for the VCO (internal amplifier, external pullup resistor at TUNE and external RC circuitry). It should be noted, however, that the tuning voltage can alter over a long period in the high impedance state as a result of selfdischarge in the peripheral circuity. TUNE may be switched off by the control bit OS to allow external adjust-
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11.11.1998
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SIEMENS Preliminary IC-SPECIFICATION TDA 6060XS, TDA 6060G
Circuit Description
ments. The software-switched bidirectional port P2 is a general-purpose open-collector output and can also be used as an A/D converter input. In the internal or external 4 MHz reference oscillator mode a test pattern is generated in the reference divider. With the bit TP in the second control byte this test pattern is switched to the modulator input. Data are exchanged between the processor and the PLL via the I2C bus. The clock is generated by the processor (input SCL), while pin SDA functions as an input or output depending on the direction of the data (open collector, external pull-up resistor). Both inputs have hysteresis and a low-pass characteristic, which enhance the noise immunity of the I2C bus. The data from the processor pass through an I2C bus controller. Depending on their function the data are subsequently stored in registers. If the bus is free, both lines will be in the marking state (SDA, SCL are HIGH). Each telegram begins with the start condition and ends with the stop condition. Start condition: SDA goes LOW, while SCL remains HIGH. Stop condition: SDA goes HIGH while SCL remains HIGH. All further information transfer takes place during SCL = LOW, and the data is forwarded to the control logic on the positive clock edge. The table 1 "bit allocation" should be referred to the following description. All telegrams are transmitted byteby-byte, followed by a ninth clock pulse, during which the control logic returns the SDA line to LOW (acknowledge condition). The first byte is comprised of seven address bits. These are used by the processor to select the PLL from several peripheral components (chip select). The eighth bit (R/W) determines whether data are written into (R/W = 0) or read from (R/W = 1) the PLL. In the data portion of the telegram during a WRITE operation, the first bit of the first or third data byte determines whether a divider ratio or control information is to follow. In each case the second byte of the same data type has to follow the first byte. If the address byte indicates a READ operation, the PLL generates an acknowledge and then shifts out the status byte onto the SDA line. If the processor generates an acknowledge, a further status byte is output; otherwise the data line is released to allow the processor to generate a stop condition. The status word consists of two bits from the TTL input ports, three bits from the A/D converter, the lock flag and the poweron flag. Four different chip addresses can be set by appropriate connection of pin CAS (see table 2 "address selection"). When the supply voltage is applied, a power-on reset circuit prevents the PLL from setting the SDA line to LOW, which would block the bus. The power-on reset flag POR is set at power-on and when VVCCD goes below 3.2 V. It will be reset at the end of a READ operation. The lock detector resets the lock flag FL when the width of the charge pump current pulses is greater than the period of the crystal oscillator (i.e. 250 ns). Hence, when FL = 1, the maximum deviation of the input frequency from the programmed frequency is given by f = IP (KVCO / fQ) (C1+C2) / (C1C2) where IP is the charge pump current, KVCO the VCO gain, fQ the crystal oscillator frequency and C1, C2 the capacitances in the loop filter (see application circuit). As the charge pump pulses at 62.5 kHz (= fref), it takes a maximum of 16 s for FL to be reset after the loop has lost lock state. Once FL has been reset, it is set only if the charge pump pulse width is less than 250 ns for eight consecutive fref periods. Therefore it takes between 128 and 144 s for FL to be set after the loop regains the lock state.
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11.11.1998
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SIEMENS Preliminary IC-SPECIFICATION TDA 6060XS, TDA 6060G
Table 1: Bit Allocation Read/Write Data
MSB Write Data Address Byte Prog. Divider Byte1 Prog. Divider Byte 2 Control Byte1 Control Byte 2 Read Data Address Byte Status Byte 1 POR 1 FL 0 x 0 FLV 0 x MA1 A2 MA0 A1 1 A0 Ack Ack 1 0 n7 1 TP 1 n14 n6 PN VG1 0 n13 n5 AU1 VG0 0 n12 n4 AU0 MD1 0 n11 n3 x MD0 MA1 n10 n2 x P2 MA0 n9 SC1 OS PS1 0 n8 SC0 FS PS0 Ack Ack Ack Ack Ack bit6 bit5 bit4 bit3 bit2 bit1 LSB Ack
note: MSB is shifted first. x = don't care Divider ratio: TDA 6060XS: N = 16384 x n14 + 8192 x n13 + 4096 x n12 + 2048 x n11 + 1024 x n10 + 512 x n9 + 256 x n8 +128 x n7 + 64 x n6 + 32 x n5 + 16 x n4 + 8 x n3 + 4 x n2 + 0 + 0 TDA 6060G: N = 16384 x n14 + 8192 x n13 + 4096 x n12 + 2048 x n11 + 1024 x n10 + 512 x n9 + 256 x n8 +128 x n7 + 64 x n6 + 32 x n5 + 16 x n4 + 8 x n3 + 4 x n2 + 2 + 0 MA0/1: PN: 1 0 Address selection (table 2) negative modulation for video and FM for sound carriers (AudinFM active) positive modulation for video and AM modulation for sound carrier (AudinAM active)
AU 0/1: Audio mode bits and Sound / RF VCO off mode (table 4) SC0/1: Sound carrier bits (table 5) OS: FS: 1 0 disables VTUNE (for external VCO adjustment) normal PLL operation
When quartz oscillator is in slave mode: 1 external frequency is 62.5 kHz, for test and special applications (test pattern and PLL lock in flag FL not available, sound carrier frequencies incorrect) 0 external frequency is 4 MHz 1 0 test pattern generator on normal operation
TP:1 VG0/1:
Video gain setting (table 6) open-collector output is active open-collector output is inactive, ADC available
MD0/1: Modulation depth (table 7) Port P2: 1 0 PS0/1: POR: FL:
Picture / sound ratio setting (table 8) Power on reset, flag is set at power-on and reset at the end of READ operation PLL lock indicator, flag is set when loop is locked
FLV: Clipping detector, flag is set when clipping duration is longer than 1sec A0/1/2: A/D converter levels when P2 works as input (table 9)
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11.11.1998
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SIEMENS Preliminary IC-SPECIFICATION TDA 6060XS, TDA 6060G
Table 2: Address Selection
Voltage at CAS (0...0.1) * VVCCD open circuit (0.4...0.6) * VVCCD (0.9...1) * VVCCD MA1 0 0 1 1 MA0 0 1 0 1
Table 3: Audio Modes
Audio mode Normal audio operation AM 5 x I switch for sound PLL Sound carrier off RF VCO off (PN bit = 0) positive modulation Normal audio operation Audio level -1dB (PN bit = 1) negative modulation Audio level -2dB (PN bit = 1) negative modulation Audio level -3dB (PN bit = 1) negative modulation PN 0 0 0 0 1 1 1 1 AU1 0 1 0 1 0 1 0 1 AU0 0 0 1 1 0 0 1 1
Table 4: Sound Carrier Frequencies
SC Frequency 4.5 MHz 5.5 MHz 6.0 MHz 6.5 MHz SC1 0 0 1 1 SC0 0 1 0 1
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11.11.1998
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SIEMENS Preliminary IC-SPECIFICATION TDA 6060XS, TDA 6060G
Table 5: Video Gain Setting
Video Gain Normal operation -1 dB -2 dB -3 dB VG1 0 0 1 1 VG0 0 1 0 1
Table 6: Modulation Depth Adjustment
Modulation Depth Normal operation +5% -5% -10 % MD1 0 0 1 1 MD0 0 1 0 1
Table 7: Picture Carrier / Sound Carrier Adjustment
Picture Carrier to Sound Carrier Ratio Normal operation - 1 dB +1 dB +2 dB PS1 0 0 1 1 PS0 0 1 0 1
Table 8: A / D Converter Levels
Voltage at P2 / ADC (0.00...0.15) * VVCCD (0.15...0.30) * VVCCD (0.30...0.45) * VVCCD (0.45...0.60) * VVCCD (0.60...1.00) * VVCCD A2 0 0 0 0 1 A1 0 0 1 1 0 A0 0 1 0 1 0
Table 9: Test Pin Configuration
Picture Carrier to Sound Carrier Ratio f cy at P2 (P2 working as output; bit P2 = 1) fref ar P2 (P2 working as output; bit P2 = 1) RF modulator in overmodulation mode Normal operation T2 0 0 1 1 T1 0 1 0 1
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11.11.1998 V66047-S0894-A100-V3-76D4 page 10
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SIEMENS Preliminary IC-SPECIFICATION TDA 6060XS, TDA 6060G
Addressing
Ack.
1st Byte
Ack.
2nd Byte Ack.
3rd Byte
Ack. 4th Byte
Ack.
MA1
MA0
1/0
Note: SDA
SCL Telegram examples: Start-Addr-DR1-DR2-CW1-CW2-Stop Start-Addr-CW1-CW2-DR1-DR2-Stop Start-Addr-DR1-DR2-Stop Start-Addr-CW1-CW2-Stop Start-Addr-ST-Stop Start Addr DR1 DR2 CW1 CW2 Stop ST = start condition = address = divider ratio 1st byte = divider ratio 2nd byte = control word 1st byte = control word 2nd byte = stop condition = read status byte
8 s 64 s
8 s 4 s
Test picture
SIEMENS Preliminary IC-SPECIFICATION TDA 6060XS, TDA 6060G
Pinning,Package Plastic Package, P-TSSOP-28-1 (Plastic Thin Shrink Small Outline Package)
Pin Assignment
AudGnd AudinFM AudinAM SC2in CAS Modout1 ModGnd Modout2 GNDD SDA SCL VVCCD Q Qx VVCCA T2 TFLF SLF Vidin GNDA O-B2 O-C1 O-C2 O-B1 T1 VTUNE CHGPMP P2 / ADC
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11.11.1998
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SIEMENS Preliminary IC-SPECIFICATION TDA 6060XS, TDA 6060G
Absolute Maximum Ratings
The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC will result. Ambient temperature Tamb = 0 C...+80 C
# Parameter Symbol Limit Values Min PLL 1 2 3 4 5 6 7 8 9 10 Supply voltage Output CHGPMP Crystal oscillator pins Q, Qx Bus input/output SDA Bus input SCL Chip address switch CAS Output active filter VTUNE Bus output SDA Port output P2 Port output P2 VVCCD VCHGPMP VQ VSDA VSCL VCAUS VTUNE ISDAL IPL VP -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 0 0 -0.3 +6 +3.5 VVCCD +6 +6 VVCCD +35 5 20 +6 V V V V V V V mA mA V open collector open collector Max Units Remarks
Modulator 11 12 13 14 15 16 17 18 Difference of supply voltages Supply voltage Video Input Modulator outputs Modulator outputs FM Audio Input AM Audio Input Second sound carrier input VVCCDVVCCA VVCCA IVidin VModout1/2 VModout1/2 VAudinFM VAudinAM VSC2in -2 -0.3 -0.3 -0.3 +6 +6 +6 -0.3 -0.3 -0.3 +0.3 +6 3.5 6 V V V V mA V V V open collector open collector
General Items 19 20 21 22 Junction temperature Storage temperature Thermal resistance (junction to ambient) ESD protectiona TJ TS RthJA VESD -1 -40 +125 +125 130 +1 C C K/W kV HBM
a. according to MIL STD 883D, method 3015.7 and EOS/ESD assn. standard S5.1 - 1993
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11.11.1998
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page 12
SIEMENS Preliminary IC-SPECIFICATION TDA 6060XS, TDA 6060G
Operational Range
Within the operational range the IC operates as described in the circuit description. The AC/DC characteristic limits are not guaranteed. Ambient temperature Tamb = 0 C...+80 C
# Parameter Symbol Limit Values Min 1 2 3 4 5 6 7 8 Supply voltage Supply voltage Programmable divider factor Programmable divider factor Video input voltage range Audio input voltage (FM or AM) Oscillator frequency range Ambient temperature VVCCD VVCCA N N VVidin VAudin fO Tamb 30 0 +4.5 +4.5 256 258 0.3 Max +5.5 +5.5 32764 32766 1 1 950 +80 Vpp Vrms MHz C V V by 4, TDA 6060XS by 4, TDA 6060G nominal 500mVpp nominal 500mVrms, 40Hz-15kHz Units Remarks
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11.11.1998
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page 13
SIEMENS Preliminary IC-SPECIFICATION TDA 6060XS, TDA 6060G
AC/DC Characteristics
AC/DC characteristics involve the spread of values guaranteed within the specified supply voltage and ambient temperature range. Typical characteristics are the median of the production. Supply voltage VVCC = 5.0 V Ambient temperature Tamb = 25 C; Ch 21...Ch 69
# Parameter Symbol Min Limit Values Typ Max Units Test Conditions
Digital Part
1 PLL Crystal oscillator connections Q, QX 2 3 4 5 6 7 Crystal frequency Crystal resistance (1) Oscillation frequency Drive current (1) Input impedance (1) fQ RQ fQ IQ ZQ -600 20 3.2 10 3,99975 4,000 350 -750 -900 4.0 4.8 100 MHz Arms dB series resonance series resonance fQ = 4 MHz fQ = 4 MHz fQ = 4 MHz fQ = 4 MHz Supply current IVCCD 16 21 29 mA VVCCD = 5 V
4,00025 MHz
Margin from 1st (fundamen- aH tal) to 2nd and 3rd harmonics
(1)
Charge pump output CHGPMP (VVCCD = 5 V) 8 9 10 Output current Tristate current Output voltage ICPL ICPZ VCP 1.0 22 50 +1 2.5 75 A nA V VCP = 2 V OS = 1, VCP = 1.3V locked
Drive output VTUNE (open collector) 11 12 HIGH output current LOW output voltage ITH VTL 10 0.5 A V VTH = 33 V ITL = 1.5 mA
Port output P2 (open collector) 13 14 HIGH output current LOW output voltage IPOH VPOL 10 0.5 A V VPOH = 5V IPOL = 15 mA
ADC port input P2 15 16 HIGH input current LOW input current IADCH IADCL -10 10 A A
(1) Design note: no 100% final inspection.
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11.11.1998
V66047-S0894-A100-V3-76D4
page 14
SIEMENS Preliminary IC-SPECIFICATION TDA 6060XS, TDA 6060G
AC/DC Characteristics
AC/DC characteristics involve the spread of values guaranteed within the specified supply voltage and ambient temperature range. Typical characteristics are the median of the production. Supply voltage VVCC = 5.0 V Ambient temperature Tamb = 25 C; Ch 21...Ch 69
# Parameter Symbol Min Address selection input CAS 17 18 I2 C HIGH input current LOW input current Bus Bus inputs SCL, SDA 19 20 21 22 HIGH input voltage LOW input voltage HIGH input current LOW input current VIH VIL IIH IIL -20 3 5.5 1.5 10 V V A A A V VIH = VS VIL = 0 V ICASH ICASL -50 50 A A VCASH = 5 V VCASL = 0 V Limit Values Typ Max Unit Test Conditions
Bus output SDA (open collector) 23 24 HIGH output current LOW output voltage IOH VOL 10 0.4 VOH = 5.5 V IOL = 3 mA
Edge speed SCL,SDA 25 26 Rise time Fall time tr tf 300 300 ns ns
Clock timing SCL 27 28 29 Frequency HIGH pulse width LOW pulse width fSCL tH tL 0 0.6 1.3 400 kHz s s s s s s
Start condition 30 31 Set-up time Hold time tsusta thsta 0.6 0.6
Stop condition 32 33 Set up time Bus free tsusto tbuf 0.6 1.3
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V66047-S0894-A100-V3-76D4
page 15
SIEMENS Preliminary IC-SPECIFICATION TDA 6060XS, TDA 6060G
AC/DC Characteristics
AC/DC characteristics involve the spread of values guaranteed within the specified supply voltage and ambient temperature range. Typical characteristics are the median of the production. Supply voltage VVCC = 5.0 V Ambient temperature Tamb = 25 C; Ch 21...Ch 69
# Parameter Symbol Min Data transfer 34 35 36 37 38 Set-up time Hold time Input hysteresis SCL, SDA (1) Noise immunity SCL, SDA (1), (2) Capacitive load for each bus line tsudat thdat Vhys VN CL 0.1 0 200 5 400 s s mV Vpp pF fN = 2 MHz..14 MHz Limit Values Typ Max Units Test Conditions
(1) Design note: no 100% final inspection (2) Sinusoidal noise signal applied via a 33 pF coupling capacitor
Analog Part
39 Supply current IVCCA 33 43 57 mA incl. mixer outputs
Video modulator 40 41 42 43 44 Video input voltage Video gain steps Step width of gain setting Intermodulation ratio Harmonic wave ratio VVidin Gain Gain aIMA aH 0.8 60 60 0.5 -3 1 1.2 Vpp dB dB dB dB fSC - fCC fPC+2fCC; fPC+3fCC; fPC+4fCC 3 steps, 1 dB each
45 46 47 48
Modulation depth Modulation depth adj. range Video signal to noise ratio Ch21 or lower Video signal to noise ratio Ch69 Audio in Video (*test procedure1)
mD/N mD/P mD VS+N/N VS+N/N
80 80 -10 48 45
90 90
98 98 +5
% % % dB dB CCIR 17-line bar, line 22 HP =200kHz LP = 5MHz unweighted FM modulation; f = 27kHz; VVidin = 0 Vpp
51 48
49
aAV
54
60
dB
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11.11.1998
V66047-S0894-A100-V3-76D4
page 16
SIEMENS Preliminary IC-SPECIFICATION TDA 6060XS, TDA 6060G
AC/DC Characteristics
AC/DC characteristics involve the spread of values guaranteed within the specified supply voltage and ambient temperature range. Typical characteristics are the median of the production. Supply voltage VVCC = 5.0 V Ambient temperature Tamb = 25 C; Ch 21...Ch 69
# Parameter Symbol Min Video modulator 49 Audio in Video (*test procedure1) Differential gain Differential phase Video frequency response aAV 54 60 dB AM modulation; m = 65 %; VVidin = 0 Vpp VVidin = 0.5 Vpp VVidin = 0.5 Vpp f = 50 Hz...5 MHz Limit Values Typ Max Units Test Conditions
50 51 52
DG DP aV
3 1
5 5 1
% deg dB
FM modulator 53 54 FM audio input voltage* FM carrier frequency range FM deviation 55 56 57 58 59 60 SC = 6.5 MHz SC = 6.0 MHz SC = 5.5 MHz SC = 4.5 MHz FM modulation distortion FM signal to noise ratio FM FM FM FM THDFM S+N/N 50 28 24 24 17.5 35 30 30 22 0.3 56 42 36 36 26.5 1.5 kHz kHz kHz kHz % dB VAudin* rms = 0.5 V
f AF = 1kHz; f =50kHz; Video: colorbar Ch21,CCIR 468-3 quasi peak
VAudin* FMC 4.5
0.5 6.5
Vrms MHz
* At pre-emphasis network input
VAudin* rms = 0.5 V; fAF = 1 kHz
Second Sound Carrier input 61 62 63 Input DC voltage Input DC voltage Input AC voltage VSC2in VSC2in VSC2in -0.3 2 30 50 0 +0.3 VVCCA 80 V V mVrms Normal operation SC2in OFF FM, SC1: 5.5MHz, SC2=SC1
AM modulator 64 65 66 AM audio input voltage* AM carrier freqency AM modulation factor VAudin* AMC 0.5 6.5 55 60 65 Vrms MHz % VAudin* rms = 0.5 V * At voltage divider input
mAM
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11.11.1998
V66047-S0894-A100-V3-76D4
page 17
SIEMENS Preliminary IC-SPECIFICATION TDA 6060XS, TDA 6060G
AC/DC Characteristics
AC/DC characteristics involve the spread of values guaranteed within the specified supply voltage and ambient temperature range. Typical characteristics are the median of the production. Supply voltage VVCC = 5.0 V Ambient temperature Tamb = 25 C; Ch 21...Ch 69
# Parameter Symbol Min 67 68 AM modulation distortion AM signal to noise ratio THDAM S+N/N 47 50 Limit Values Typ Max 1.5 % dB Units Test Conditions VAudin* rms = 0.5 V fAF = 1 kHz; m = 60%; RMS; CCIR 468; video: colorbar
RF Modulator, referred to Application Board 69 70 71 72 73 74 75 76 77 Modulator output impedance RModout CModout RF output voltage VModout 77 20 0.5 80 -15 8 10 11 13 55 60 11 13 14 16 65 -10 14 16 17 19 k pF dBV dBc dB dB dB dB dB dB RL = 75 fModout = 470 to 860 MHz L; M; DK standard f=4.5MHz, 6.5MHz B/G; I standard f=5.5MHz, 6.0MHz L; M; DK standard f=4.5MHz, 6.5MHz B/G; I standard f=5.5MHz, 6.0MHz referenced to picture carrier
RF output harmonics (n = 2) aRF2 Picture Sound carrier ratio TDA 6060XS Picture Sound carrier ratio TDA 6060XS Picture Sound carrier ratio TDA 6060G Picture Sound carrier ratio TDA 6060G Sound carrier harmonics PC / SC ratio PC / SC ratio PC / SC ratio PC / SC ratio THD SC
Rejection of PLL refence fre- a fref quency
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11.11.1998
V66047-S0894-A100-V3-76D4
page 18
SIEMENS Preliminary IC-SPECIFICATION TDA 6060XS, TDA 6060G
Test Circuit 1 Measurement of Crystal Oscillator Frequency
VVCCD IVCCD Q 18 pF 4 MHz Qx 5V 5k
Test mode: tbf
TDA 6060
P2
fref
Counter
fQ = fref * 64 GNDD
Test Procedure 1: Crosstalk Audio in Video
aAV
VCO
-1 kHz + 1 kHz
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11.11.1998
V66047-S0894-A100-V3-76D4
page 19
SIEMENS Preliminary IC-SPECIFICATION TDA 6060XS, TDA 6060G
Equivalent I/O-Schematic
Equivalent I/O-Schematic of Quartz Oscillator
18 pF 4 MHz
pin 13
Q Qx
pin 14
Equivalent I/O-Schematic of Charge Pump
CHGPMP VTUNE pin 17 IT internal
VCP ICP pin 16
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11.11.1998
V66047-S0894-A100-V3-76D4
page 20
SIEMENS Preliminary IC-SPECIFICATION TDA 6060XS, TDA 6060G
Equivalent I/O-Schematic
Equivalent I/O-Schematic of Port Pin
pin 15 P2
IP
ADC input
Equivalent I/O-Schematic of CAS Pin
VCAS pin 5 CAS ICAS
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11.11.1998
V66047-S0894-A100-V3-76D4
page 21
SIEMENS Preliminary IC-SPECIFICATION TDA 6060XS, TDA 6060G
Equivalent I/O-Schematic
Equivalent I/O-Schematic of SDA/SCL Pins
SDA, SCL
pin 10/ 11
Ii
SDA only
Equivalent I/O-Schematic of Pins T1, AudinFM, AudinAM, SC2in
T1, SC2in, AudinFM, AudinAM
pin 2,3,4, 18
Ii
Equivalent I/O-Schematic of UHF- VHF-Oscillator Pins
pin 20 pin 19 T1 T2
pin 21
pin 22
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11.11.1998
V66047-S0894-A100-V3-76D4
page 22
SIEMENS Preliminary IC-SPECIFICATION TDA 6060XS, TDA 6060G
Equivalent I/O-Schematic of Modulator Output Pins
Modout1 pin 6
Modout2 pin 8
oscillator
Equivalent I/O-Schematic of Video Input
Vidin pin 24
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11.11.1998
V66047-S0894-A100-V3-76D4
page 23
SIEMENS Preliminary IC-SPECIFICATION TDA 6060XS, TDA 6060G
Equivalent I/O-Schematic of Filter Pins SLF, TFLF
TFL, SLF pin 25,26
Equivalent I/O-Schematic of Filter Pin T2
T2
pin 27
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11.11.1998
V66047-S0894-A100-V3-76D4
page 24
SIEMENS Preliminary IC-SPECIFICATION TDA 6060XS, TDA 6060G
I2C-Bus Timing
thdat
tsusto
tsudat
data transfer
stop
thst
tbuf
tr
90
10
tsusta
90
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11.11.1998
10
V66047-S0894-A100-V3-76D4
start
tbuf tr tf tsusta thsta tL tH tsudat thdat tsusto
tf
bus free time data/clock rise time data/clock fall time start set-up time start hold time LOW clock pulse width HIGH clock pulse width data transfer set-up time data transfer hold time stop set-up time clock
SDA
SCL
tL
tr
tH
tf
page 25
SIEMENS Preliminary IC-SPECIFICATION TDA 6060XS, TDA 6060G
Test Circuit Diagram
VCCA
Video in
+33V 4.7n P2/ADC
22k 22k 1k 1n 10p 4.7n 22k 22k BB535
75 47n 100k 100n VVCCA TFLF 10n T2 100n Vidin SLF 100n 1.2p GNDA O-C1 O-B2 1.2p O-C2 1.2p O-B1 1.2p 10n
2.2n
22n CHGPMP 16 P2 / ADC 15 14 Qx 4 MHz
28
27
26
25
24
23
22
21
20
19
18
TDA 6060XS, TDA 6060G
1 AudGnd
2 AudinFM
3 AudinAM
4 SC2in 4.7n
5 CAS
6 Modout1
7 ModGnd
8 Modout2
9 GNDD
10 SDA
11 SCL
VTUNE 17 12 VVCCD
T1
13 Q 18p
22n 75 75
100n
Audio Audio SC2 CAS in FM in AM in 2 : 1
VCCM
600
SDA SCL VCCD
RF, 50 Ohm
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11.11.1998
V66047-S0894-A100-V3-76D4
page 26
SIEMENS Preliminary IC-SPECIFICATION TDA 6060XS, TDA 6060G
Application Board
+5V
4.7n
Video in
+33V 4.7n
22k 22k 1k 1n 15p 4.7n 22k 22k BB535
75 4.7 2.7k
47n
100n VVCCA TFLF 100n T2 100n Vidin SLF
470n 1.2p GNDA O-C1 O-B2 1.2p O-C2 1.2p O-B1 1.2p 10n CHGPMP
22n P2 / ADC 15 14 Qx 4 MHz
28
27
26
25
24
23
22
21
20
19
18
VTUNE
T1
17
16
TDA 6060XS, TDA 6060G
1 AudGnd
2 AudinFM
3 AudinAM
4 SC2in 4.7n
5 CAS
6 Modout1
7 ModGnd
8 Modout2
9 GNDD
10 SDA
11 SCL
12 VVCCD
13 Q 18p
4.7 k
4.7n 4.7n
4.7 k
47k 4.7 k 47k 1n
270
4.7n 470n 4.7n
220
220
Audio SC2 CAS in in RF out
SDA SCL +5V
The reproduction, transmission or use of this document or its contents is not permitted without express written authority. Offenders will be liable for damages.All rights, including rights created by patent grant or registration of a utility model or design, are reserved.
11.11.1998
V66047-S0894-A100-V3-76D4
page 27

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