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Introduction
PerkinElmer's D Series image sensors are high-speed, self-scanned, chargecoupled photodiode (CCPD) arrays. The D Series Family, consisting of the Standard and Wide Aperture image sensors, allows the designer to select just the right device for a particular application. Typical applications include optical character recognition, document scanning, inspection, pattern recognition, noncontact measurement, and other applications requiring high quality, broad spectral response image acquisitions.
D Series
256, 512, 1024, 2048 Elements Photodiode Array
EVERYTHING IN A NEW LIGHT.
General Description
The D Series family of image sensors features the CCPD architecture which combines the best features of CCD and photodiode technology. The CCD readout structure allows high speed, low noise operation. The photodiode sensing elements provide superior light sensitivity, especially in the blue and near UV spectrum range. The Standard device is the nominal component of the D Series family. It operates at data rates up to 10 MHz, has 13 m x 13 m pixels, and features very high dynamic range. The Wide Aperture device is a wide-aperture version featuring 13 m x 26 m pixels for higher photo sensitivity.
Figure 1. D Series Linear Array and Pinnate Configuration
Key Features
* Antiblooming * Video data rates up to 10 MHz * High photo sensitivity * Wide dynamic range * 256, 512, 1024, and 2048 elements * 13 m x 13 m and 13 m x 26 m picture elements * Low power consumption * Wide spectral response (UV to near IR)
* (Pin 17 is N/C for RL0256D, VSub
2 VIn2 1 SB VSB VSub SBP VRD2 VID2 VLR VAB 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 T VRec 2 VIn1 1 * SBN VRD1 VID1 VDD GND
for all other D Series devices)
D Series Linear Family
1
2 V SB SB
1
RL (External to the Chip)
VIn2
2 CCD Shift Register
SB P V RD2
Even V
LR
Video R L
,VID
2
(External to the Chip)
VRec
N VSUB N-1
N-2 3
2 1
V
AB
V DD
R T
L
(External to the Chip) Odd Video ,VID
1
VIn1
2 CCD Shift Register
V RD1 SB N
1
2
2
RL (External to the Chip)
Figure 2. Simplified Schematic
Relative Aperture Response
100% 0
1
2
N-1
N
In addition, D Series Linear devices contain an antiblooming gate which can be used to either suppress blooming or to set the integration period independent of the line rate. That allows these devices to be used over the widest possible range of lighting conditions. Light incident on the sensing aperture generates a photocurrent which is integrated and stored as a charge on the capacitance of each of the photodiodes. If the charge accumulated on any diode exceeds a saturation value, the excess is shunted to VAB through the antiblooming gates, controlled by VLR, to control blooming effects (refer to Figure 2). The antiblooming gate is biased at a DC potential which is below that of the junction barrier and transfer gate oT "low" barrier. When the signal charge reaches the level set by the antiblooming gate, the excess will be sunk into VAB , thus preventing blooming. At the end of each integration period, the charges on all the diodes are simultaneously switched through transfer gates, oT, into one of two CCD analog shift registers for readout. The odd numbered diodes are switched into one register and the even diodes into the other. Immediately after this parallel transfer, a new integration period begins. Readout is accomplished by clocking the CCD shift registers so that the charge packets are delivered sequentially into two onchip charge-detection circuits. The registers deliver the charge packets to their outputs on alternate clock phases, allowing the inactive charge detector to be reset to a fixed level, VRD, while the opposite detector is active. The outputs of the two detectors may then be multiplexed off-chip if a single continuous video output is desired. Each video signal is developed across a 2-5K resistor load, RL.
a c 1
b
Distance
2
N-1
N
Figure 3. Sensor Geometry and Idealized Aperture Response
Functional Description
The sensing elements for the D Series Linear CCPDs are a row of diffused p-n junction photodiodes spaced on 13 m centers and interdigitated into a sensing aperture 13 m wide (26 m for Wide Aperture). The photodiode sensing elements provide very broad spectral response while the CCD readout registers and output buffer amplifiers allow very low-noise signal extraction. Figure 1 shows the pinout configuration and Figure 2 is a simplified schematic diagram. Figure 3 shows the aperture response function and sensor geometry. The dimensions shown in Figure 3 are as follows: the photodiode diffusion width a is 7 m, the center-to-center spacing b is 13 m and the aperture width c is 13 m or 26 m. Note that the entire 13 m (dimension b) produces photocurrent which divides between the two diffusions, with most of the charge going to the pixel near the site of the photon absorption.
D Series Linear Family
Operation
D Series devices require two complimentary shift register clocks, o1 and o2, a transfer gate pulse, oT, for normal operation. An additional transfer pulse, oSB, is required if a scan buffer output is desired. The clocks and their timing relationships are shown in Figure 4. The video output and scan buffer output, SBP + SBN, are also shown in Figure 4. The scan buffer output provides two marker bits; the first pulse coincides with the first video element, and the second with the last video element. The scan buffer output is obtained by differencing SBP and SBN through a differential amplifier. The circuit shown in Figure 6 will provide the required interface between the device's scan buffer output and its peripheral TTL circuit. Use of the scan buffer at higher speeds, greater than 5 MHz, is not recommended. It may be defeated by applying 0V to oSB. The transfer pulse should swing between 0 and +5V and must have a width greater than 0.2 sec. In order to transfer the charge from the photodiodes into the CCD register, the o1 clock must remain high during the blanking and transfer interval (see Figure 4). The odd and even video outputs are also shown in Figure 4. The odd and even output reset clocks, oRO and oRE, are derived from the same sources as o1 and o2 and are nominally synchronous with them. Figure 10 shows the schematic of a typical voltage drive circuit for the D Series. The high speed amplifier output circuit such as shown in Figure 5 is not required but is recommended to reduce the loading effects of external circuit capacitance. This will result in video rise and fall times of 50 ns or less.
Performance
Spectral response of the D Series devices covers the range from UV to the near IR. A ground and polished glass window is provided on the Standard devices. A quartz window is provided on Wide Aperture devices. Relative spectral re-sponse is shown as a function of wavelength in Figure 7. Since most applications for these devices (OCR, machine vision, etc.) use visible light, the responsivity and uniformity of response are specified using a light source with the spectral distribution shown by the dotted line in Figure 7. This spectral distribution is produced by filtering a 2870K tungsten source with a FishSchurman HA-11 heat absorbing 1 mm thick filter. Transfer characteristics showing the noise level and satura-tion output voltage can be seen in Figure 8. Since Reticon's line scanners operate in the charge-storage mode, the charge output of each diode (below saturation) is proportional to exposure; i.e., the irradiance or light intensity multiplied by the integration time or the time interval between successive transfer pulses. Thus, there is a trade-off between scanning speed and required light intensity. Light intensity in watts needed to saturate a pixel at a particular integration time can be obtained by dividing saturation exposure by integration time. Thus, that longer integration times may be used to detect lower light levels. However, this approach is ultimately limited by dark leakage current which is integrated along with the photocurrent.
1; RE 2; RO
300 ns min
T SB
50 ns min
200 ns min 50 ns min
Video 1
D1
D3
D5
D7
D9
1
3
N-1
D1
Dark Reference Video 2
D2 D4 D6 D8 D10 2 N D2
Dark Reference SBP + SBN
Figure 4. Timing Relationship of the Array's Clock Signals and Output
D Series Linear Family
+12V 100 1/2 .01 F VID 1 14 3K 3K VID 2 9 3K 3K MPS 6515 or Equivalent Buffered Video Output Even MPS 6515 or Equivalent Buffered Video Output Odd 100 1/2 .01 F
ODO Series Linear Photodiode Array
Figure 5. Recommended Output Circuit
101/2 10 1/2
0.1 F
+12V
+12V +5V
2.2K
2.2K
0.1F 1
101/2 0.1 F
SBN SBP
Q1
MPS 6519
Q2
MP1 6519
LM 3 361 10
4
14
3 6
0.1 F
TTL Output 101/2 -12V
5.1K
5.1K
1K
R55 1K
1K
Figure 6. Recommended Buffer Output Circuit
1.0
1.0
Quartz Window Response
Array Spectral Response
Relative Response
0.8
0.6
Test Glass Window Response Light Source 0.01
0.4
0.2
Relative Noise
0 200 300 400 500 600 700 800 900 1000 1100 1200
Output (Volts)
0.1
2.7 V/J/cm 2
0.001
Wavelength (nm)
0.001
0.01
0.1 2
0.47 1.0
Exposure (Joules/cm )
Figure 7. Relative Spectral Response as a Function of Wavelength
Figure 8. Typical Transfer Characteristics
D Series Linear Family
Drive Circuit
The circuit shown in Figure 10 will interface the TTL level control circuit to D Series CCPD devices. It will ensure that the o1 and o2 clock transitions cross at or above the midpoint; i.e., 50% clock crossing or higher. The supply voltages to the o1 and o2 clock drivers, devices 3 and 4, are as follows: VSS = 0V or ground and VDD = +12V. The clock drivers, devices 1A and 2A, will provide voltage swings consistent with those given in the specification table. The supply voltages to device 1A are VDD = +5V, pin 6, and VSS = 0V. The supply voltages to device 2A are VDD = +12V, pin 6, and VSS = +5V. (Note: Both supply pins are positive to keep the minimum swing to +5V.)
1 2 Video #1 (Odd) Tf
Max 100% VDD Typ 80% VDD Min 50% VDD Cross Over Tr Dark Level @ 6.6V Reset Level Reset Level Video
@ 7.0V
Video #2 (Even)
Dark Level 0 Tf 30 ns 0 Tr 15 ns
Video
Figure 9. Clock Crossing and Video Output Relationship
+5V
TTL T Clock TTL SB Clock
5.1K
0.1 F 0.1 F
7404
T
Device 1A 1/2 DS0026
7404
-
+12V
10 F
+ Device 2A
SB
1/2 DS0026
5.1K 0.01 F 1K 0.01 F 1K
0.01 F
7408
To 1 Odd
Device 3A 1/2 DS0026
7404 CLK Q 7474 D Q
100 1/2
10 pF
7404
7408
To 1 Even
MH0026
7408 7404 7404
1K 0.01 F 1K
To 2 Even
Device 4A and B, DS0026
100 1/2
10 pF
7408
To 2 Odd
Device 3B 1/2 DS0026
Figure 10. Drive Circuit for D Series Linear Devices
D Series Linear Family
Table 1. Array Bias and Clock Level Requirements
Symbol VRD VDD VIN VAB VLR Parameter Reset drain bias Output drain bias Input bias Antiblooming drain Antiblooming gate Disabled Antiblooming active Line reset active Substrate bias CCD transport clock High Low Transfer clock High Low Transfer clock scan buffer High Low Receiving gate DC input scanning Min +11 +11 +11 +7 -1 +1 +2.5 -2 +11 -1 +4 -1 +11 +4 -1 +11 Typ +12 +12 +12 +8 0 +1.7 +3.5 -1 +12 0 +5 0 +12 +5 0 +12 Max +13 +13 +13 +9 +1 +2.5 +4.5 0 +13 +1 +6 +1 +13 +6 +1 +13 Units V V V V V V V V V V V V V V V V
VSub o1, o2
oT
oSB
VRec VSB
"Min and Max values shown represent the allowable tolerance to maintain normal operation and are not absolute min and max values".
Table 2. Absolute Maximum Ratings
(Above Which Useful Life May Be Impaired) Storage temperature Operating temperature Voltage on any pin with respect to substrate -25C to 85C -25C to 55C -0.3V to 22V
Table 3. Linear D Series Array Capacitance Values
1
Pin 1, 20 3, 18 4 7, 16 9, 14 10 22
Notes:
Sym o2 o1 oSB SBP, SBN VID2 , VID1 VLR oT
RL2048D 386 367 25 5 5 14 103
Typical Capacitance (pF) RL1024D RL0512D RL0256D 193 111 55 185 106 53 13 8 6 4 4 3 4 4 3 14 14 14 61 40 20
1 Measured with respect to device substrate (pin 6) with a DC bias voltage of +12V
D Series Linear Family
Table 4 . Array Performance Characteristics
Conditions: (unless otherwise specified) Ta = 25C, fdata = 10 MHz, tint = 10 ms, RL (at video output) = 3 K, VLR = 1.6V, Light Source = 2870K + Fish Schurman HA-11, 1 mm filter. All other operating voltages are nominal, as specified in Array Electrical Characteristics. First and last pixels of each video output are ignored.
Symbol DRP-P DRrms ENE ESat R PRNU 0256 0512 1024 2048 Vda Vdm VSat P NP-P VDCR VDCD ZOut VBal fdata
Parameter Dynamic range 1 Dynamic range 1 P-to-P noise equivalent exposure Wide Aperture Saturation exposure Wide Aperture Responsivity Wide Aperture Photoresponse nonuniformity 4, 6
2 2 2 2
Min
.30 .15 2.0 4.0 0.8 7
Typ 2600:1 13000:1 .18 .09 .47 .24 2.7 5.4 3 3 3 5 .03 .06 1.2 126 0.5 7.0 6.7 2 80 10 -
Max
Units
.63 .32 3.3 6.6 8 8 10 12 .25 .5 1.5 160 -
nj/cm2 nj/cm2 j/cm2 j/cm2 V/j/cm2 V/j/cm2 % % % % % % V mW mV V V k mV mV/C MHz
Average dark signal 3, 8 Maximum dark signal 4, 8 Saturation output voltage Power dissipation 5 Peak-to-peak noise Output DC reset level 5 Output DC dark level 5 Output impedance 6 Video output balance Output DC drift 10 Maximum guaranteed video data rate Standard and Wide Aperture
10
Notes: 1 Dynamic range is defined as V / N , RMS noise is approximately N / 5. Sat P-P P-P 2 Measured at an exposure level of approximately V / 2. PRNU is defined as 100*[(V -V ) / V ] where V Sat max min avg max is output of highest pixel (toward VSat). Vmin is output of lowest pixel (towards dark) and Vavg is the numerical average of all the pixels in the video line. 3 Measured at ambient temperatures T = 25C, t = 2.5 ms. Defined as 100* (V / V ) where V is the numerical average of the output of all pixels in dark and V is a int a Sat a Sat the numerical average of all pixels in saturation. 4 Measured at ambient temperature T = 25C, t = 2.5 ms. Defined as 100* (V / V ) where V is the pixel with the maximum output of all pixels in dark and V is the a int m Sat m Sat numerical average of all of pixels in saturation. 5 Measured with device in the dark. 6 Measured with output current of 2 mA. 7f data is defined as 2 times fclock where fclock is the frequency of the o1 or o2 clock. The minimum frequency is limited by increases in dark signal. 8 Dark signal approximately doubles for each 7-10C increase in temperature. 9 Defined as the difference in DC dark level output (D ) between the two video outputs. DC 10 Defined as the thermal drift in the reset level (R ). DC
D Series Linear Family
A
Pixel 1
.038" .010" from Top of Window
.390 .010
Sensing Area
to Top of Image Sensor Die
13 m
Pin No. 1
Quartz or Glass
B
.038 .010
.185 Typ 0.100 0.008 10 Equal Spaces @ .100 = 1.00
0.020
C
0.002
0.020 0.002
0.020 0.002 0.400 0.010 (At Standoff)
A Device RL0256D RL0512D RL1024D RL2048D inches .131 .262 .524 1.048 mm 3.328 6.656 13.312 26.624
B inches 1.0800.011 1.0800.011 1.0800.011 1.6000.016
C inches 0.0900.009 0.0800.008 0.0800.008 0.0800.008
Figure 11. Package Dimensions
Ordering Information
Standard RL0256DAG-111 RL0512DAG-111 RL1024DAG-111 RL2048DAG-111 Wide Aperture RL0256DKQ-111 RL0512DKQ-111 RL1024DKQ-111 RL2048DKQ-111
The quartz window supplied standard on Wide Aperture devices is available as an option for all D Series devices. For options, consult PerkinElmer Optoelectronics.
For more information e-mail us at opto@perkinelmer.com or visit our web site at www.perkinelmer.com/opto PerkinElmer Optoelectronics 2175 Mission College Blvd. Santa Clara, CA 95054 Toll Free: (800) 775-OPTO Phone: (408) 565-0830 Fax: (408) 565-0703
All values are nominal; specifications subject to change without notice. (c)2000 PerkinElmer, Inc. All rights reserved. 0700
is a registered trademark of PerkinElmer, Inc.

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