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| HV57708 32 MHz, 64-Channel Serial To Parallel Converter With Push-Pull Outputs Ordering Information Package Options Device 80 Lead Quad Ceramic Gullwing HV57708DG 80 Lead Quad Plastic Gullwing (MIL-STD-883 Processed*) HV57708PG 80 Lead Quad Ceramic Gullwing (MIL-STD-883 Processed*) RBHV57708DG Die HV57708X HV57708 * For Hi-Rel process flows, refer to page 5-3 of the Databook. Features Processed with HVCMOS(R) technology 5V CMOS logic Output voltages up to 80V Low power level shifting 32MHz equivalent data rate Latched data outputs Forward and reverse shifting options (DIR pin) Diode to VPP allows efficient power recovery Outputs may be hot switched Hi-Rel processing available General Description The HV577 is a low-voltage serial to high-voltage parallel converter with push-pull outputs. This device has been designed for use as a driver for electroluminescent displays. It can also be used in any application requiring multiple output high-voltage current sourcing and sinking capability such as driving plasma panels, vacuum fluorescent displays, or large matrix LCD displays. The device has 4 parallel 16-bit shift registers, permitting data rates 4X the speed of one ( they are clocked together). There are also 64 latches and control logic to perform the polarity select and blanking of the outputs. HVout1 is connected to the first stage of the first shift register through the polarity and blanking logic. Data is shifted through the shift registers on the logic low to high transition of the clock. The DIR pin causes CCW shifting when connected to GND, and CW shifting when connected to VDD. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register (HVOUT64). Operation of the shift register is not affected by the LE (latch enable), BL (blanking), or the POL (polarity) inputs. Transfer of data from the shift registers to the latches occurs when the LE (latch enable) input is high. The data in the latches is stored when LE is low. Absolute Maximum Ratings Supply voltage, VDD1 Output voltage, VPP1 Logic input levels1 Ground current 2 Continuous total power dissipation 3 Operating temperature range Storage temperature range Lead temperature 1.6mm (1/16 inch) from case for 10 seconds Plastic Ceramic -0.5V to +7.5V -0.5V to +90V -0.3V to VDD +0.3V 1.5A 1200mW 1900mW Plastic Ceramic -40 to 85C -55C to 125C -65C to +150C 260C Notes: 1. All voltages are referenced to GND. 2. Limited by the total power dissipated in the package. 3. For operation above 25C ambient derate linearly to maximum operating temperature at 20mW/C for plastic and at 19mW/C for ceramic. 02/96/022 For detailed circuit and application information, please refer to application note AN-H3. Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website. 1 HV57708 Electrical Characteristics (over recommended operating conditions unless noted, T =-40C to +85C) A DC Characteristics Symbol IDD IPP IDDQ VOH VOL IIH IIL VOC Parameter VDD supply current High voltage supply current Min Max 15 100 100 Quiescent VDD supply current High-level output HVOUT Data out Low-level output HVOUT Data out High-level logic input current Low-level logic input current High voltage clamp diode 65 VDD - 0.5 7 0.5 1 -1 1 100 Units mA A A A V V V V A A V Conditions VDD = VDD max fCLK = 8MHz Outputs high Outputs low All VIN = VDD IO= -15mA, VPP = 80V IO= -100A IO = 12mA, VPP = 80V IO= 100A VIH = VDD VIL = 0V IOC = 1mA AC Characteristics (TA = 85C max. Logic signal inputs and Data inputs have tr, tf 5ns [10% and 90% points]) Symbol fCLK tWL,tWH tSU tH tON, tOFF tDHL tDLH tDLE* tWLE Parameter Clock frequency Clock width high or low Data set-up time before clock rises Data hold time after clock rises Time from latch enable to HVOUT Delay time clock to data high to low Delay time clock to data low to high Delay time clock to LE low to high Width of LE pulse 25 25 62 10 15 500 70 70 Min Max 8 Units MHz ns ns ns ns ns ns ns ns CL = 15pF CL = 15pF CL = 15pF Conditions Per Register tSLE LE set-up time before clock rises 0 ns * tDLE is not required but is recommended to produce stable HV outputs and thus minimize power dissipation and current spikes (allows internal SR output to stabilize). Recommended Operating Conditions Symbol VDD VPP VIH VIL fCLK TA Logic supply voltage Output voltage High-level input voltage Low-level input voltage Clock frequency per register Operating free-air temperature Plastic Ceramic Note: Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 4. Apply VPP. 5. The VPP should not drop below VDD or float during operation. Power-down sequence should be the reverse of the above. Parameter Min 4.5 8 VDD -0.5V 0 Max 5.5 80 Units V V V 0.5 8 V MHz C -40 -55 +85 +125 2 HV57708 Input and Output Equivalent Circuits VDD VDD VPP Input Data Out HVOUT GND Logic Inputs GND Logic Data Output GND High Voltage Outputs Switching Waveforms VIH Data Input 50% tSU Clock 50% tWL 50% tWH 50% VOL Data Out tDLH 50% tDHL VOH VOL Data Valid tH 90% 50% 50% VIL tf tr VIH 10% 10% 90% 50% VIL VOH Latch Enable tDLE 50% tWLE 50% tSLE VIH VOL HVOUT w/ S/R LOW tOFF HVOUT w/ S/R HIGH 90% 10% VOH VOL 10% tON 90% VOH VOL 3 HV57708 Functional Block Diagram DO1 DO2 DI 4 DI 3 DO3 DI 2 DO4 DI 1 V DD LE BL POL VPP DIR SR1 HV OUT 1 5 9 * * * HV OUT61 SR2 HV OUT 2 6 10 * * * HV OUT62 CLK HV OUT 3 7 11 * * * HV OUT63 SR3 SR4 HV OUT 4 8 12 * * * HV OUT64 DO4 DO3 DI 1 DI 2 DO2 DI 3 DO1 DI 4 GND Note: Each SR (shift register) provides 16 outputs. SR1 supplies every fourth output starting with 1; SR2 supplies every fourth output with 2, etc. Function Table Inputs Function All O/P High All O/P Low O/P Normal O/P Inverted Data Falls Through (Latches Transparent) Data Stored/ Latches Loaded Data X X X X L H L H X X DI/O1-4A DI/O1-4A I/O Relation DI/O1-4B DI/O1-4B Note: Outputs BL L L H H H H H H H H H H H H POL L H H L H H L L H L H H H H DIR X X X X X X X X X X H H L L L H L H * * Qn Qn +1 Qn Qn +1 Qn Qn -1 Qn Qn -1 Shift Reg HV Outputs H L No inversion Inversion L H H L Stored Data Inversion of Stored Data New H or L Previous H or L Previous H or L New H or L DI/O1 - 4B DI/O1 - 4B DI/O1 - 4A DI/O1 - 4A Data Out CLK X X X X X X LE X X X X H H H H L L H L L H * = dependent on previous stage's state. See Pin configuration for DIN and DOUT pin designation for CW and CCW shift. 4 HV57708 Pin Configurations HV577 80-pin Gullwing Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Function HVOUT 24/41 HVOUT 23/42 HVOUT 22/43 HVOUT 21/44 HVOUT 20/45 HVOUT 19/46 HVOUT 18/47 HVOUT 17/48 HVOUT 16/49 HVOUT 15/50 HVOUT 14/51 HVOUT 13/52 HVOUT 12/53 HVOUT 11/54 HVOUT 10/55 HVOUT 9/56 HVOUT 8/57 HVOUT 7/58 HVOUT 6/59 HVOUT 5/60 HVOUT 4/61 HVOUT 3/62 HVOUT 2/63 HVOUT 1/64 DIN 1/DOUT 4(A) DIN 2/DOUT 3(A) DIN 3/DOUT 2(A) DIN 4/DOUT 1(A) LE CLK BL VDD DIR GND POL DOUT 4/DIN 1(B) DOUT 3/DIN 2(B) DOUT 2/DIN 3(B) DOUT 1/DIN 4(B) VPP Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Function HVOUT 64/1 HVOUT 63/2 HVOUT 62/3 HVOUT 61/4 HVOUT 60/5 HVOUT 59/6 HVOUT 58/7 HVOUT 57/8 HVOUT 56/9 HVOUT 55/10 HVOUT 54/11 HVOUT 53/12 HVOUT 52/13 HVOUT 51/14 HVOUT 50/15 HVOUT 49/16 HVOUT 48/17 HVOUT 47/18 HVOUT 46/19 HVOUT 45/20 HVOUT 44/21 HVOUT 43/22 HVOUT 42/23 HVOUT 41/24 HVOUT 40/25 HVOUT 39/26 HVOUT 38/27 HVOUT 37/28 HVOUT 36/29 HVOUT 35/30 HVOUT 34/31 HVOUT 33/32 HVOUT 32/33 HVOUT 31/34 HVOUT 30/35 HVOUT 29/36 HVOUT 28/37 HVOUT 27/38 HVOUT 26/39 HVOUT 25/40 Package Outline 64 65 41 40 Index 80 1 top view 80-pin Gullwing Package 24 25 HVOUT32 * DIR = H; CW (HVOUT1 HVOUT64) DIR = L; CCW (HVOUT64 HVOUT1) DIR = H DIR = L HOUT33 * * 1 * 2 * 3 * 4 HVOUT2 HVOUT1 Pin 25 26 27 28 36 37 38 39 SR4 1 SR3 2 SR2 3 SR1 4 * * * * HOUT63 HOUT64 Note: Pin designation for DIR = H/L. Example: For DIR = H, pin 41 is HVOUT 64. For DIR = L, pin 41 is HVOUT 1. For CW/CCW Shift see function table QN QN+1. 02/06//02 (c)2002 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited. 5 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 * FAX: (408) 222-4895 www.supertex.com |
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