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(R)
STV9211
150 MHz PIXEL VIDEO CONTROLLER FOR MONITORS IN DC-COUPLING MODE
FEATURES
q 150 q 2.7 qI
MHz Pixel Rate
ns Rise and Fall Time Bus Controlled q Support DC Coupling Application only q Brightness Selection (after or before Drive) q Grey Scale Tracking Versus Brightness q InfraBlack Range Selection 1.3 or 1.8V (i.e: 26 or 36V in kit with STV95xx amplifier) q InfraBlack Offset Selection 0.4 to 2.2V (i.e: 115 to 80V in kit with STV95xx amplifiers) q OSD Mixing q Beam Current Attenuation (ABL) q Pedestral Clamping on Output Stage q Possibility of Light or Dark Grey OSD Background q OSD Contrast Control q Input Black Level Clamping with Built-in Clamping Pulse q 5 V to 8 V Power Supply q Perfectly matched with the STV95xx ST Amplifier Family q Preamplifier Control (bandwidth and stand-by) q Amplifier Control (bandwidth and stand-by), only applicable to amplifiers with CTL pin or STDBY pins.
2C
DIP20 (Plastic Package) ORDER CODE:
The RGB incoming signals are amplified and shaped to drive in DC coupling the video amplifier without intermediate follower stages. One of the main advantages of ST devices is their ability to sink and source currents. These driving capabilities combined with an original output stage structure suppress any static current on the output pins and therefore reduce dramatically the power dissipation of the device. Extensive integration combined with high performance and advanced features make the STV9211 one of the best choice for any CRT monitor. Perfectly matched with the ST video amplifiers STV95xx, they offer a complete solution for high performance and cost-optimized Video Board Application.
DESCRIPTION
The STV9211 is an I2C Bus controlled RGB preamplifier designed for Monitor applications, able to mix the RGB signals coming from any OSD device. The usual Contrast, Brightness, Drive and Cut-Off (InfraBlack) Controls are provided. In addition, it includes the following features: - High resolution cut-off (InfraBlack) adjustment, - OSD contrast, - Bandwidth and stand-by control, - Brightness before/after Drive Selection.
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STV9211
Table of contents
Chapter 1
1.1 1.2
Pin connection, pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Pin connection ................... .................................................. ........................... ...................... 6 Pin description ................... .................................................. ........................... ...................... 6
Chapter 2
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 2.16 2.17 2.18 2.19
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
RGB input, clamping function ..................... ........................... ............................................... 8 Fast blanking input ...................................... ........................................ ................................. 9 Blanking input .................... .................................................. ........................... ...................... 9 Contrast adjustment (8 bits) .................... ............................................................ ...............10 Brightness/Drive selection (1 bit) .............. ........................... .............................................. 11 Drive adjustment (3 x 8 bits) ................. ............................................................. ................ 11 Brightness adjustment (8 bits) ................. ........................... ................................................ 12 Cut-off adjustment, Infra-black level (Vib) (3x8 bits) ..................... .............. ....................... 13 ABL Control .................. .................................................................................................... ..15 OSD ........................... ........................................ ............................................................ .... 15 Output stage ............... .............. .......................................................................................... 17 Preamplifier bandwidth adjustment (4 bits) ................ ........................................................ 18 Amplifier bandwidth adjustment (7 bits) .............................................................. ............... 18 CRT cathode, DC-coupling mode (Figure 14) ......................... ........................................... 19 Preamplifier stand-by mode ........................ .............. ......................................................... 19 Amplifier stand-by mode .............. .......................................................................... ............ 19 Serial interface ............... .......................................................................... .......................... 20 Power-on reset ....................... ....................................................................................... ..... 20 Specific application conditions .................... ........................... ............................................ 21
Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7
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Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 I2C electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
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STV9211 Chapter 8 Chapter 9 Chapter 10
10.1 10.2 10.3 10.4
I2C interface timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 I2C register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 STV9211 + STV9556/55/53 applications hints . . . . . . . . . . . . . . . . . . . . . . . . . .30
InfraBlack adjustment procedure (Cut-off) ......................... .............. .................................. 30 Preamplifier bandwidth register ......................... ............................................................. .... 32 Preamplifier output network ................ ............................................................................... 32 White balance adjustment ....................... ................................................. .......................... 32
Chapter 11 Chapter 12 Chapter 13
Internal schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Demonstration boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
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STV9211
Revision follow-up
Target specification
December 2000 January 2001 January 2001 version 1.0 version 1.1 version 1.2 document created reformatted with ST new corporate template General update - replacement of some figures , - correction and addition of registers First ADCS release April 2001 version 1.3 General update - replacement of some figures , - correction of text, - addition of sections June 2001 version 1.4 General update and addition of: - chapter 10: Application hints, - chapter 11: Internal, schematics, - chapter 12: application boards
Product preview
October 2001 version 2.0 General update: - replacement of some figures, - addition of sections : cut-off adjustment..., - addition of figures (I2C, Cut-off adjustment) - TDA95xx salestype replaced with STV95xx
Preliminary data
December 2001 version 3.0 General update - figures replaced - Cut-off replaced with Infra-Black
Datasheet
January 2002 version 4.0 section 1.2: pin description modified for IN1, IN2, IN3, OSD1, OSD2, OSD3 and OUT1, OUT2, OUT3: replaced with video input, OSD input, Video output (channel 1, red), (channel 2, green), (channel 3, blue) respectively Block diagram replaced section 2.3 Blanking input added Section 2.8 - Cut-off adjustment: Tables 1 and 2 gathered into table 1 Section 2.12 - preamplifier bandwidth adjustment (4 bits) instead of 3 bits previously Chapter 10 - Application hints tables 9 and 10 replaced with table 1 Cross reference to AN1445 replaced with AN1510
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Pin connection, pin description
1
1.1
PIN CONNECTION, PIN DESCRIPTION
Pin connection
Figure 1: STV9211 pin connection
IN1 ABL IN2
AMPCTL
IN3 GNDA
VCCA
OSD1 OSD2 OSD3
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
BLK HS OUT1 VCCP OUT2 GNDP OUT3 SDA SCL FBLK
1.2
1 2 3 4
Pin description
Pin number symbol
IN1 ABL IN2 AMPCTL
description
Video input (channel 1, red) ABL input Video input (channel 2, green) Amplifier control (bandwidth and stand-by). Only applicable with amplifiers with the CTL or STDBY pins. To be connected to ground if not used. Video input (channel 3, blue) Analog ground Analog supply (5V) OSD input (channel 1, red) OSD input (channel 2, green) OSD input (channel 3, blue) Fast blanking SCL SDA Video output (channel 3, blue) Power ground Video output (channel 2, green) Output stage supply (5 V to 8 V) Video output (channel 1, red) Horizontal synchro or BPCP pulse Blanking input
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
IN3 GNDA VCCA OSD1 OSD2 OSD3 FBLK SCL SDA OUT3 GNDP OUT2 VCCP OUT1 HS BLK
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FBLK VCCA VCCP 17 3V (DC) PreAmplifier Stand-by R13-bit7 (I C) Amplifier IC OUT1 Drive 8-bit + Stage GND R13-bit6 15 GNDP BLK * Range: 1.3 & 1.8V * Offset (3-bit) * Adjustment (8-bit) InfraBlack Adjustment (**) (Cut-off) CTL or STDBY EHT 18
Output
HS 11 7 HS OCL Generator (*) BLK
BLK
19
20
BPCP (*)
IC
Red Channel
TDA95xx
+ +
IN1
1
Contrast 8-bit
Pin connection, pin description
STMicroelectroni cs Confidential
Brightness 8-bit
Vref
Figure 2: Block diagram
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IN2
3
Green Channel Blue Channel
16
OUT2
IN3
5
14
OUT3
ABL
I C Bus Decoder
2
Amplifier control 4 IC * Stand-by: On/Off * Bandwidth (3-bit) AMPCTL OSD Contrast 4-bit OSD Contrast 4-bit 10 OSD3 OSD Contrast 4-bit 9 OSD2
TDA9211
12 SCL OSD1 8 6 GND
13
SDA
(*) See RGB input section for complete BPCP and OCL description
(**) See Cut-off adjustment section for complete Cut-off register description
STV9211
STV9211
Functional description
2
2.1
FUNCTIONAL DESCRIPTION
RGB input, clamping function
The three RGB inputs have to be supplied with a video signal (maximum peak-to-peak value = 1V) through coupling capacitors (100 nF typ.). The RGB inputs include a clamping function using the input serial capacitor as "memory capacitor". To avoid the discharge of this capacitor during the line (due to leakage current), the input voltage is referenced to the ground. This clamping function is gated by the BPCP pulse (Black Porch Clamping Pulse) which is internally generated (see Figure 4). The Register 8 allows to choose the way to generate this BPCP (see Figure 3 and Figure 4). - Synchronization: - Polarity: HS or BLK signal (Register 8, bit0) Positive or negative (Automatic detection) when synchronized by HS Positive or negative ( programmed via Register 9, bit 0) when synchronized by BLK - see Note 1 - Edge: - Width: - Direct BPCP: Trailing or Leading (Register 8, bit1) From 0.33s to 1.33s (Register 8, bit2 and bit3) If the application provides the BPCP, one can program the direct connection between Pin 19 and the internal BPCP (Register 8, bit4)
Note 1: When BPCP is synchronized by BLK, the leading edge of the BLK must be selected to get a proper synchronization.
Figure 3: BPCP selection of synchronization edge Synchronization source Edge selection BPCP generation
Trailing (R8, bit 1=0) HS (R8, bit 0=0) Leading (R8, bit 1=1)
HS (Pin 19) Internal BPCP
HS (Pin 19) Internal BPCP BLK (Pin 20) Internal BPCP
BLK (R8, bit 0=1)
Leading (R8, bit 1=0)
HS (R8, bit 4=1)
HS (Pin 19) _ Internal BPCP =HS
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Functional description
Figure 4: BPCP and OCL generation
STV9211
HS Edge Selection BPCP Source Selection R8-bit1 R8-bit4 Source Selection Width Selection R8-bit0 R8-bit2 & bit3 BPCP Internal
HS 1 External
Automatic Polarity
Edge Selection
Pulse Generation
BLK 20 External
Polarity Selection
Pulse Generation
OCL Internal
BLK Polarity Selection: R9-bit0
OCL source Selection: R8-bit7
2.2
Fast blanking input
The fast blanking pin (FBLK) is TTL compatible. The blanking pulse can be:
q q
positive or negative line or Composite-type (but not Frame-type).
2.3
Blanking input
The blanking pin (BLK) is TTL compatible. A 5 V logical pulse generally supplies the BLK pin and defines the Infra-black level (see Signal waveform, Figure 12). It is also possible to apply the H-Flyback signal directly to the BLK pin by using a simple circuitry, as shown in Figure 5.
Figure 5: Blanking pin (BLK) directly controlled by the H-flyback signal
40 to 100V 5V Typical H-Flyback signal
2.7k H-Flyback R (*) 20 BLK D GND 0 to -10V 5V GND Signal at BLK pin (Pin 20)
(*) R value is chosen so that the signal at BLK pin is not inferior to 0V
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Functional description
2.4
Contrast adjustment (8 bits)
The contrast is adjusted simultaneously on, the 3 RGB channels via three internal amplifiers delivering a 48dB attenuation range (see Register 1, I2C table 1 and Figure 6). .
Figure 6: Contrast adjustment
BLK
ax =m T p CR = Ty CRT
Output
CRT = min
Black level InfraBlack level
Channel
Register min / max Adjustment name / address attenuation Contrast
Number step / resolution
CRT / 01
0 / - 48 dB
256 (8 bit) / 0,19 dB
3 channels Simultaneously
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Functional description
STV9211
2.5
Brightness/Drive selection (1 bit)
The brightness position is selectable by I2C (Register 13, bit6. See I2C table 4). There are 2 cases: bit6=0 The brightness is located before the Drive (as for the TDA9210). The advantage is to keep the "White balance" tracking when changing the brightness level. bit6=1 The brightness is located after the Drive. The advantage is to perform the "White balance" tracking faster (typically one adjustment less than in the previous case)
2.6
Drive adjustment (3 x 8 bits)
In order to perform the "White balance" adjustment, the gain of the three RGB signals are adjustable separately via the three Drive amplifiers (Registers 3, 4 and 5, I2C table 1). The very large range of the Drives (48 dB) allows different standards or custom color temperatures. It can also be used to adjust the output voltages at the optimum amplitude to drive the CRT drivers, keeping the whole contrast control for the end-user only.
Figure 7: Drive adjustment
BLK
Case #1: Brightness before Drive Register 13, b6=0
Output
ax =m V DR p = Ty RV D
DRV = min
Black levels InfraBlack level
Case #2: Brightness after Drive Register 13, b6=1
V DR
ax =m
= DRV
Typ
Black level InfraBlack level
Channel
Output
DRV = min
Register min / max Adjustment name / address Attenuation Number step / resolution Drive
DRV / 03, 04, 05
0 / - 48 dB
256 (8 bit) / 0,19 dB
each channel Independantly
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Functional description
2.7
Brightness adjustment (8 bits)
Brightness adjustment is controlled by Register 2 (I2C table 1). It consists of adding the same DC voltage (BRT) to the three RGB signals. This DC voltage can be adjusted between 0 and 2V, outside the blanking pulse with 8mV adjustment steps (see Figure 8). Inside the blanking pulse the DC output level is forced to the "Infra Black" level (Vib).
Figure 8: Brightness adjustment
BLK
BRT max 2V BRT min Insertion pulse: VIP (*) 0.4V Vib GND Black levels InfraBlack level
(*) The Insertion pulse VIP is present only in "Brightness before Drive" mode
Adjustment Brightness Register name / address min / max Value Number step / resolution Channel
BRT / 02
0/2V
256 (8 bit) / 8mV
3 channels simultaneously
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Functional description
STV9211
2.8
Cut-off adjustment, Infra-black level (Vib) (3x8 bits)
The Infra-black level (Vib) is the output voltage during the blanking time (BLK). This level is sampled after each line (sample - and - hold block) during an internal pulse (OCL) which is generated during the blanking pulse (see Figure 4). The STV9211 allows to adjust independantly the cut-off levels of the 3 video outputs with a high resolution. This is done via 3 registers (IBR, IBO and IBL) programming respectively:
q q q
the range: 1.3 or 1.8V (i.e: 26 or 36V in kit with the STV95xx amplifiers) the offset (to keep the video signal inside thelinear area) the level. Infra-black range register (IBR: Register 14, bit 0. See I C table 6) This register must be selected first, either to 1.3V to get a 26V Cut-off adjustment range with the STV95xx amplifier or to 1.8V to get a 36V range (see Figure 9 )
Infra-black offset register (IBO: Register 14, bit 1, 2 & 3. See I C table 6) This register select the Vib offset. It allows to keep the video signal inside the linearity area of the amplifier. The value of this register depends on the amplifier high voltage supply (Vdd). In kit with the STV95xx amplifier family, we recommend the following programming:
Table 1: Setting of the infra-black offset register (IBO) Case 1: Vdd (5%) Brightness before Drive Binary 112 to 115V 107 to 111V 102 to 106V 97 to 101V 92 to 96V 88 to 91 87 and below 001 010 011 100 101 110 111 Decimal 1 2 3 4 5 6 7 Case 2: Brightness after Drive Binary 011 100 101 110 111 111 111 Decimal 3 4 5 6 7 7 7
Example: For Vdd=101V +/-5% and Brightness before Drive, IBO must be set to 100. Infra-black level register (IBL: Register 10, 11, 12. See I C table 1) These three 8 bit- registers adjust independantly the infra-black level of the 3 outputs with a high resolution (typically 100mV at 26V range or 140mV at 36V range).
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Functional description
Figure 9: Infra-black level adjustment
BLK
IBL max IBL min Vibmin GND
Case #1: IBR=1 Vib
IB0= 111
Black level Infra-black level Vibmax
Case #2: IBR=0 Vib
1 =11 IB0 10 =0 IB0 001 = IB0=000 B0 I
2,20
010 IB0= 01 0 IB0= 00 0 B0= I
2,20
1.8V
0.92 0.66 0.40 0
1.3V
0.92 0.66 0.40 IBL 0
255
255
IBL
Adjustment InfraBlack Range InfraBlack Offset
Register name & address IBR / 14 IBO / 14
Selection
min / max value 1.3 or 1.8 V 0.4 to 2.2 V (@ IBL=0) 0.40 to 1.70V
Number step / resolution 2 selections 16 (3 bit) / 0.26V
Channel 3 channels Simultaneously 3 channels Simultaneously
Examples #1 IBR=1 IB0=000
256 (8 bit) / 5 mV each channel Independantly
InfraBlack Level
IBL / 10, 11, 12
Examples #2 IBR=0 IB0=010
0.92 to 2.72 V
256 (8 bit) / 7mV
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Functional description
STV9211
2.9
ABL Control
The STV9211 includes an ABL (automatic beam limitation) input to attenuate the RGB Video signals depending on the beam intensity. The operating range is 2 V (from 3 V to 1 V). A typical 15 dB maximum attenuation is applied to the output signal whatever the contrast adjustment is. (See Figure 10). When not used, the ABL input (Pin 2) must be connected to a 5 V supply voltage.
Figure 10: ABL attenuation range
Attenuation (dB) 0 -2 -4 -6 -8 -10 -12 -14 -16 1 2 0
VABL (V) 3 4 5
2.10
OSD
Principle
The STV9211 allows to mix the OSD signals into the RGB main picture. The four pins dedicated to this function are the following:
q
Three TTL RGB inputs (Pins 8, 9, 10) connected to the three outputs of the corresponding OSD processor. One TTL fast blanking input (Pin 11) also connected to the FBLK output of the OSD processor.
q
When a high level is present on the FBLK, the IC acts as follows:
q
The three main picture RGB input signals (IN1, IN2, IN3) are internally switched to an internal clamp reference voltage. The three output signals (OUT1, OUT2, OUT3) are set to the voltage corresponding to the three OSD input logic states (0 or 1). (See Figure 2: Block diagram).
q
Output level
If the OSD input is set to 0, the output is set to the black level (see Figure 11). If the OSD input is at high level, the output voltage is set to: black-level + VOSD, where VOSD is the I2C bus-controlled voltage, adjustable between 0 V to 4.9 V by 306 mV steps via Register 7 (4 bits). The same variation is applied simultaneously to the three channels providing the OSD contrast.
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Functional description
The STV9211 allows the display of grey OSD by programming the following conditions:
q q
OSD1 = 1, OSD2 = 0 and OSD3 = 1, Register 9, bit 5 or 6 = 1.
If Register 9, bit 5 =1: a light grey OSD is displayed. If Register 9, bit 6 = 1: a dark grey OSD is displayed. If Register 9, bit 5=0 and bit 6=0: a standard OSD is displayed.
Figure 11: OSD
Video IN BLK
OSD signals
FBLK OSD In 4.9V OSD max
OSD typ VOSD Video OUT OSD min black level infra-black level GND
Adjustment
Register name / address
min / max Value 0 / 4.9 V (*)
Number step / resolution
Channel 3 channels simultaneously
OSD Contrast
OSD / 09
16 (4 bit) / 306mV
(*) 4.9V is the max OSD level at Drive max (DRV=254)
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Functional description
STV9211
2.11
Output stage
The overall waveforms of the output signal are shown in Figure 12. The three output stages are large bandwidth output amplifiers able to deliver up to 4.4 VPP for 0.7 VPP video signal. When a high level is applied on the BLK input (Pin 20), the three outputs are forced to "Infra Black" level (Vib) thanks to a sample and hold circuit (described below). The black level is the output voltage outside the blanking pulse when no video input signal is available (see Figure 12 ).
Figure 12: Signal waveforms
Typical Input signals Typical Internal signals OSD signals
BLK HS (Pin 19)
BPCP OCL
Video IN
FBLK OSD IN
Video OUT
black-level Infra-black level
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Functional description
2.12
Preamplifier bandwidth adjustment (4 bits)
An advanced feature: preamplifier bandwidth adjustment (BW: Register 13, see I2C table 5), is implemented on the STV9211. The programming of this BW register is very important to get good video performances. It must not be set its maximum value. With the following values, the optimum performances are obtained.
Preamplifier bandwidth register: BW tR/tF Binary
5.5 1 ns 7.5 1ns 9.5 1ns 10 ns and below 1000 0101 0010 0000
Decimal
8 5 2 0
For applications where rise/fall time <5.5ns, this feature offers several advantages:
q
Slew-rate: depending on the external capacitive load and on the peak-to-peak output voltage, this adjustment avoids getting any slew-rate phenomenon. Electromagnetic radiation (EMI): slowing down the signal of rise/fall time will decrease the EMI without significantly deteriorating the rise/fall time of the CRT driver. Video signal response: using this adjustment will allow to optimize the high frequency transient phenomenons. Picture boost mode: when displaying still pictures or moving video, having high video swing can be of greater interest than rise/fall time. The preamplifier bandwidth adjustment can be used to avoid any slew-rate phenomenon at the CRT driver output.
q
q
q
2.13
Amplifier bandwidth adjustment (7 bits)
The STV9211 can adjust the bandwidth of any ST video amplifier having a dedicated control pin (CTL). The adjustment is done by I2C via Register 6 (see I2C table 2). If not used, the AMPCTL pin must be connected to ground.
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Functional description
STV9211
2.14
CRT cathode, DC-coupling mode (Figure 13)
The STV9211 can be used in DC coupling mode only. The cut-off (InfraBlack) adjustment is done by the preamplifier. The infra-black level (Vib) is adjusted independently for each channel via the Registers 10, 11 and 12 (see the complete description in Section 2.10 ).
Figure 13: DC-coupling mode
STV9211
OUT
Amplifier STV95xx
+
InfraBlack Adjustment (Cut-off) * Range: 1.3 & 1.8V * Offset: 3-bit * Adjustment: 8-bit
2.15
Preamplifier stand-by mode
The STV9211 is set in stand-by mode either by I2C or by decreasing the VCCP supply voltage.
q q
I2C: the STV9211 is in stand-by mode when Register 13, bit 7=1 VCCP: the STV9211 is in stand-by mode when VCCP<3 V
In stand-by mode, the analog blocks are internally switched-off while the logic parts (I2C bus and power-on reset) are still supplied. The power consumption is below 20mW.
2.16
Amplifier stand-by mode
The STV9211 can set in stand-by mode any ST video amplifier with the CTL control pin. When Register 9, bit 7=1, the AMPCTL pin is switched to low level (<0.3V). The amplifier is set in stand-by mode when CTL<0.3V. If not used, the AMPCTL pin must be connected to ground.
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Functional description
2.17
Serial interface
The 2-wire serial interface is an I2C interface. The slave address of the STV9211 is DC hex.
A6 1 A5 1 A4 0 A3 1 A2 1 A1 1 A0 0 W 0
The host MCU can write into the STV9211 Registers. Read mode is not available. In order to write data into the STV9211, after the "start" message, the MCU must send the following data (see Figure 14):
q q q
the I2C address slave byte with a low level for the R/W bit, the byte to the internal Register address where the MCU wants to write data, the data.
All bytes are sent with MSB bit first. The transfer of written data is ended with a "stop" message. When transmitting several data, the Register addresses and data can be written with no need to repeat the start and slave addresses.
Figure 14: I2C write operation
SCL SDA Start I2C Slave Address W A7 ACK A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK Stop
Register Address
Data Byte
2.18
Power-on reset
A power-on reset function is implemented on the STV9211 so that the I2C registers have a determined status after power-on. The Power-on reset threshold for a rising supply on VCCA (Pin 7) is 3.8 V (typ.) and 3.2V when the VCC decreases.
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Functional description
STV9211
2.19
Specific application conditions
q
Functioning with VCCP below 8 V
To simplify the application, it is possible to supply the power VCCP with 5 V (instead of 8 V nominal) at the expense of output swing voltage.The CRT Heater voltage (6.2V Typ.) is used very often to supply VCCP..
q
Functioning without blanking pulse
If no blanking pulse is applied to the STV9211, it is necessary to ensure the OCL pulse generation (which sets the infra-black level) by setting the Register 8, bit7=1 (OCL = BPCP). To ensure the device correct behavior in the worst possible conditions, the brightness Register must be set to 0.
q
Soft blanking
It is possible to blank the video signal by setting the Register 9, bit1=1 and Register 8, bit 6=1. In this mode the output voltage is set to Vib (see Figure 15). This mode is used for example when changing the timing resolution of the video, in order to suppress the video during this transient period.
Figure 15: Soft blanking
Case #1: Normal operation Register 9, bit1=0 Case #2: Soft Blanking mode Register 9, bit1=1
Black level
Infra-black
Feature
Register name & address Register 9, bit1 (*)
Channel 3 channels simultaneously
Soft Blanking
(*) Register 8, bit6 must be set to 1 too
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Absolute maximum ratings
3
ABSOLUTE MAXIMUM RATINGS
Symbol
VCCA VCCP Vin VI VESD Tstg Toper
Parameter
Supply Voltage on Analog VCC Supply Voltage on Power VCC Voltage at any Input Pins (except Video inputs) and Input/Output Pins Voltage at Video Inputs ESD susceptibility Human Body Model (100pF discharge through 1.5k) Storage Temperature Operating Junction Temperature
Pin
7 20 1, 3, 5 All -
Value
5.5 8.8 5.5 1.4 2 +150
Units
V V V V kV C C
4
THERMAL DATA
Symbol
Rth(j-a) Tj
Parameter
Max. Junction-ambient Thermal Resistance Typ. Junction Temperature at Tamb = 25C
Value
69 80
Units
C/W C
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DC electrical characteristics
STV9211
5
DC ELECTRICAL CHARACTERISTICS
Tamb = 25C, VCCA = 5V, V CCP = 8V, unless otherwise specified.
Symbol Parameter
Analog Supply Voltage Power Supply Voltage Power Supply Voltage stand-by threshold Analog Supply Current Power Supply Current Total Supply Current in stand-by mode Pin 7 Pin 17 Pin 17 VCCA = 5V VCCP = 8V Pin 17 and pin 7 -
Test conditions
Min.
4.5 4.5 2.5
Typ.
5 8 3.0 70 55 0.7
Max.
5.5 8.8 3.5
Units
V V V mA mA
SUPPLY VCCA VCCP VCCPS I CCA I CCP IS
5 1 VCCP -0.5V 0.8 1
mA V V V V A k
INPUTS, OUTPUTS Video Input Voltage Amplitude VI Vo VIL VIH I IN RHS AMPCTL1 AMPCTL2 Output Voltage Range Low Level Input Voltage High Level Input Voltage Input Current Input Resistor Amplifier standby threshold Amplifier operating range OSD, FBLK, BLK, HS 2.4 OSD, FBLK, BLK HS Pin 4 @ Register 9, bit 7 = 1 and I4sink = 200A Pin 4@Register 9,bit 7 = 0 and I4sink = 200A Register 6, bit 4 to bit 7=0000 Register 6, bit 4 to bit 7=1111 -1 0.5 Note 1
40 80 300
mV
0.7 4.5
V V
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AC electrical characteristics
6
AC ELECTRICAL CHARACTERISTICS
Tamb = 25C, VCCA = 5V, VCCP= 8V, Vi = 0.7 VPP , CLOAD = 5pF
RS = 100, serial between output pin and CLOAD, unless otherwise specified.
Symbol Parameter Test conditions Min. Typ.
16 4.4 2.2 48 48
0.1
Max.
Units
dB V V dB dB dB V V V mV
VIDEO OUTPUT SIGNAL (pins 14, 16, 18) - CONTRAST AND DRIVE G Maximum gain Max Contrast and Drive (CRT = DRV = 254 dec) VOM Maximum video output voltage Max Contrast and Drive (Note 1) (CRT = DRV = 254 dec) VON Nominal video output voltage Contrast and Drive at POR (CRT = DRV = 180 dec) CAR Contrast attenuation range From max. Contrast (CRT=254 dec) to min. Contrast (CRT = 1 dec) From Max. Drive (DRV = 254 dec) to min. Drive (DRV = 1 dec) GM Gain matching (Note 3) Contrast and Drive at POR VIDEO OUTPUT SIGNAL (pins 14, 16, 18) - BRIGHTNESS BRTmax Maximum brightness level Max. Brightness (BRT = 255 dec) and Max. Drive (DRV = 254 dec) BRT min Minimum brightness level Min. Brightness (BRT = 0 dec) and Max. Drive (DRV = 254 dec) VIP Insertion pulse (Note 4) BRTM Brightness matching (Note 3) Brightness and Drive at POR VIDEO OUTPUT SIGNAL - OSD Max. Drive (DRV = 254 dec) VOSDmax Maximum OSD output level Max. OSD (OSD = 15 dec) VOSD min Minimum OSD output level Min. OSD (OSD = 0 dec) VIDEO OUTPUT SIGNAL - INFRA BLACK LEVEL (Figure 9) IBR=0 and IBL=0 Vib0 max Maximum infrablack level Max. Vib (IBL = 255 dec) Vib0 min Minimum infrablack level Min. Vib (IBL = 0 dec) IBR=1 and IBL=0 Vib1 max Maximum infrablack level Max. Vib (IBL = 255 dec) Vib1 min. Minimum infrablack level Min. Vib (IBL = 0 dec) Vib step 0 Infrablack level step IBR=0 (Note 5) Vib step 1 Infrablack level step IBR=1 (Note 5) ABL (Pin 2) GABLmin ABL mini attenuation VABL 3.2 V GABL max ABL maxi attenuation V =1V DAR Drive attenuation range
ABL
2 0 0.4
10
4.9 0
V V
2.2 0.4 1.7 0.4 7 5 0 15 3 0 -2 2.7 5 130 70 130 60 35
V V V V mV mV dB dB V A A ns MHz MHz MHz dB dB
VABL IABL high IABLl ow
ABL threshold voltage High ABL input current Low ABL input current
For output attenuation VABL = 3.2V VABL = 1V
VIDEO OUTPUT SIGNAL - DYNAMIC PERFORMANCES (Figure 10) tR, tF Rise Time, Fall Time (Note 6) VOUT = 2 VPP (BW = 15 dec) VOUT = 2 VPP (BW = 0 dec) BW BW Large Signal Bandwidth Bandwidth Adjustment Range VOUT = 2 VPP VOUT = 2 VPP Minimum bandwidth (BW = 0 dec) Maximum bandwidth (BW =15 dec) VOUT = 2 VPP@ f = 10 MHz @ f = 50 MHz
CT
Crosstalk between Video Outputs
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AC electrical characteristics
STV9211
Notes about electrical characteristics
Note: 1 The video on the preamplifier output must remain above 0.5V even for high frequency signals. 2 Assuming that the video output signal remains inside the linear area of the preamplifier output (between 0.5V and VCCP - 0.5V) 3 Matching measured between the different outputs 4 The VIP insertion pulse is present only in "brightness before drive" mode (see Figure 8) 5 In kit with the STV95xx amplifier, this 7/5 mV step resolution offers a 100/140mV resolution at the amplifier output 6 tR, tF are calculated values, assuming an ideal input signal with rise/fall time = 0ns
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I2C electrical characteristics
7
I2C ELECTRICAL CHARACTERISTICS
Tamb = 25C, VCCA = 5V, VCCP= 8V, Vi = 0.7 VPP, CLOAD = 5pF
Symbol
VIL VIH IIN fSCL(Max.) VOL
Parameter
Low Level Input Voltage High Level Input Voltage Input Current (Pins SDA, SCL) SCL Maximum Clock Frequency Low Level Output Voltage
Test conditions
On Pins SDA, SCL
Min.
3
Typ.
Max.
1.5
Units
V V A kHz V
0.4 V < VIN < 4.5 V SDA Pin when ACK Sink Current = 6mA
-10 0.25
+10 200 0.6
8
I2C INTERFACE TIMING REQUIREMENTS
Symbol Parameter
Time the bus must be free between two accesses Hold Time for Start Condition Set-up Time for Stop Condition The Low Period of Clock The High Period of Clock Hold Time Data Set-up Time Data Rise and Fall Time of both SDA and SCL
Min.
Typ.
Max.
1300 600 600 1300 600 300 250 20
Units
ns ns ns ns ns ns ns ns
tBUF tHDS tSUP tLOW tHIGH tHDAT tSUDAT tR, tF
Figure 16: I2C timing diagram
t BUF SDA t HDS SCL t HIGH
t HDAT
t SUDAT
t SUP
t LOW
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I2C register description
STV9211
9
I2C REGISTER DESCRIPTION
Table 2: Register sub-addressed - I2C table 1 Sub-address Hex
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E
Dec
01 02 03 04 05 06 07 08 09 10 11 12 13 14
Register Names
Contrast (CRT) - Note 1 Brightness (BRT) Drive 1 (DRV) - Note 1 Drive 2 (DRV) - Note 1 Drive 3 (DRV) - Note 1 Amplifier control OSD Contrast (OSD) BPCP & OCL Miscellaneous Out 1- Infra-black level: IBL1 Out 2- Infra-black level: IBL2 Out 3- Infra-black level: IBL3 Preamplifier Bandwidth Adjustment (BW) - Note 2 InfraBlack range and offset selection 8-bit 8-bit 8-bit 8-bit 8-bit DAC DAC DAC DAC DAC
POR Value Hex
B4 B4 B4 B4 B4 99 09 04 1C B4 B4 B4 07
Max. Value Hex
FE FF FE FE FE 0F
Dec
180 180 180 180 180 153 09 04 28 180 180 180 07
Dec
254 255 254 254 254 15
refer to I 2C table 2 4-bit DAC Refer to I2C table 3 Refer to I2C table 4 8-bit DAC 8-bit DAC 8-bit DAC 4-bit DAC I2C table 5 Refer to I2C table 6
FF FF FF 0F
255 255 255 15
.
Table 3: Amplifier bandwidth adjustment register (R6) - I2C table 2 b7
0 1 1
b6
0 0 1
b5
0 0 1
b4
0 1 1
b3
0 0 0
b2
0 0 0
b1
0 0 0
b0
0 0 0 Min. amplifier bandwidth Typ. amplifier bandwidth Max. amplifier bandwidth
Function
POR value
x
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Table 4: BPCP & OCL register (R8) - I2C table 3 b7 b6 b5 b4
0 0 0 0 0 0 0 0 1 0 1 0 1 0 1
I2C register description
b3
b2
b1
0 1 0 1
b0
0 0 1 1
Function
Internal BPCP triggered by HS (trailing edge) Internal BPCP triggered by HS (leading edge) Internal BPCP synchronized by BLK (leading edge) Internal BPCP synchronized by BLK (trailing edge) Internal BPCP Width = 0.33 s Internal BPCP Width = 0.66 s Internal BPCP Width = 1 s Internal BPCP Width = 1.33 s Internal BPCP = BPCP input Normal Operation Reserved (Force BPCP to 1 in test) Normal Operation Reserved (Force OCL to 1 in test) Internal OCL pulse triggered by BLK Internal OCL pulse = Internal BPCP
POR value
x x
0 0 1 1
0 1 0 1
x
x x x
Table 5: Miscellaneous register (R9) - I2C table 4 b7 b6 b5 b4 b3 b2 b1 b0
0 1 0 1 0 1 0 0 0 1 0 1 0 1 0 0
Function
Positive Blanking Polarity Negative Blanking Polarity Soft Blanking = OFF Soft Blanking = ON (Note 3) Reserved (Test mode, very low bandwidth) Normal operation Light Grey on OSD Outputs = OFF Light Grey on OSD Outputs = ON Dark Grey on OSD Outputs = OFF Dark Grey on OSD Outputs = ON Amplifier stand-by = OFF Amplifier stand-by = ON
POR value
x x
x x x x
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I2C register description
Table 6: Preamplifier bandwidth adjustment (R13) - I2C table 5 b7 b6 b5 b4 b3
1 0 0 0 0 1 0 1 0 1 0 1 0
STV9211
b2
1 1 0
b1
1 1 0
b0
1 1 0
Function
130 MHz (Note 2) 100 MHz (Note 2) 70 MHz(Note 2) Normal operation Reserved (test mode - BW DAC output connected to BLK input) Reserved (test mode - BW DAC complementary output connected to BLK input) Brightness before drive Brightness after drive Preamplifier stand-by = OFF Preamplifier stand-by = ON
POR value
x x
x x
Table 7: Cut-off range and offset selection (R14) - I2C table 6 - see Figure 9 b7
-
b6
-
b5
-
b4
-
b3
0 1 1
b2
0 0 1
b1
0 0 1
b0
0 1 Infra-black Infra-black Infra-black Infra-black Infra-black
Function
range (IBR) = 1.8V range (IBR) = 1.3V offset (IB0)- Min. value = 0.4V @ IBL =0 offset (IB0)- Typ. value = 1.3V @ IBL = 0 offset (IB0)- Max. value = 2.2V@ IBL = 0
POR value
x x
Notes about I2C register description
Note: 1 For contrast & drive adjustment, code 00 (dec) and 255 (dec) are not allowed. 2 This register has to be set with the following values:
Preamplifier bandwidth register: BW tR/tF Binary
5.5 1 ns 7.5 1ns 9.5 1ns 10 ns and below 1000 0101 0010 0000
Decimal
8 5 2 0
3 to set the device in soft blanking mode, it is necessary to program also Register 8, bit 6 = 1
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STV9211 + STV9556/55/53 applications hints
10
10.1
STV9211 + STV9556/55/53 APPLICATIONS HINTS
InfraBlack adjustment procedure (Cut-off)
The STV9211 allows to adjust independantly the InfraBlack levels of the 3 video outputs with a high resolution. This ajustment is done via the 3 infra-black level registers (IBL1, IBL2 and IBL3). In order to have the optimum resolution, it is necessary, first, to set the video signal inside the linear area of the amplifier, by programing the infra-black range register IBR (26 or 36V) and the infrablack offset register IBO.
Step 1 Setting of the infra-black range register IBR (Register 14, bit 0. See I C table 6). This register must be selected, either to 1.3V to get a 26V Cut-off adjustment range with the STV95xx amplifier or to 1.8V to get a 36V range (see Figure 17) Step 2 Setting of the Infra-black offset register IBO (Register 14, bit 1, 2 & 3. See I C table 6). This register selects the Vib Offset. It allows to keep the video signal inside the linearity area of the amplifier. The register value depends on the amplifier high voltage supply (Vdd). In kit with the STV95xx amplifier family, we recommend the following programming:
Table 8: Setting of the infra-black offset register (IBO) Case 1: Vdd (5%) Brightness before Drive Binary 112 to 115V 107 to 111V 102 to 106V 97 to 101V 92 to 96V 88 to 91 87 and below 001 010 011 100 101 110 111 Decimal 1 2 3 4 5 6 7 Case 2: Brightness after Drive Binary 011 100 101 110 111 111 111 Decimal 3 4 5 6 7 7 7
Example: For Vdd=101V +/-5% and Brightness before Drive, IBO must be set to 100.
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STV9211 + STV9556/55/53 applications hints
Step 3
STV9211
Adjustment of the InfraBlack level register IBL (Register 10, 11, 12. See I C table 1). These three 8 bit- registers adjust separately the infra-black level of the 3 outputs with a high resolution (100mV at 26V range or 140mV at 36V range).
Figure 17: STV9211 and STV95xx - Cut-off adjustment
PreAmplifier
OUT IN
Amplifier STV95xx
* G=20 * Vref=5.6V
STV9211
VDD Vib-A Black Vib-P GND InfraBlack InfraBlack Black
Vib-P (@IBO=000)
Vib-A (@IBO=000)
InfraBlack Range: IBR
IBR 0 1 DVib-P 1.8V 1.3V DVib-A 36V 26V
2,20 1.70
I BR =0
110V 1.8V 84V 1.3V IBL 0 255 0 74V
IBR=
1
26V
IBR =0
36V
0.40
IBR=
1
IBL 255
InfraBlack Offset: IBO
IBO 000 001 010 --111 Vib-P 0.40V 0.66V 0.92V --2.22V Vib-A 110V 2,22 105V 100V --75V 0.92 0.66 0.40 0 Vib-P (@IBR=1) Vib-A (@IBR=1) 110V 105V 100V 1.3V IBL 255 0 255 75V
111 IB0= 010 IB0= 1 =00 IB0 000 IB0=
IB0=0 00 IB0=0 01 IB0=0 10 IB0=1 11
IBL 26V
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STV9211 + STV9556/55/53 applications hints
10.2
Preamplifier bandwidth register
The preamplifier bandwidth must not be set to maximum. To get the optimum video performances and reduce the EMI, we recommend to use the values from Section 2.12.
10.3
Preamplifier output network
The choice of the network between the STV9211video outputs and the STV95XX amplifier is important. We recommend to use the network described in the application note AN1510.
10.4
White balance adjustment
The white balance adjustment on a DC-coupling video system and an AC-coupling video system differs. Please, use our application note referenced AN1490 for the complete description of the white balance procedure.
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Internal schematics
STV9211
11
INTERNAL SCHEMATICS
Figure 18:
VCCA 30k V CCA 1k IN (Pins 1-3-5) HIGH IMPEDANCE ABL 2
Figure 19:
GNDA GNDA
Figure 20: Pin 4
V CCA VCCA 1k AMPCTL 4
Figure 21:
7 (8V) LOGIC PART
GNDA
GNDA
6
Figure 22:
Figure 23:
VCCA OSD-FBLK-HS-BLK Pins 8-9-10 11-19-20 GNDA GNDL GNDA GNDL HSYNC 19
Figure 24:
30k SCL 12 4pF GNDA (8V) GNDL GNDP 30k SCA 13 4pF GNDA GNDL
Figure 25:
VCCP
15
GNDA
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Internal schematics
Figure 26:
VCCP 17 OUT Pins 14-16-18
(20V)
GNDA
GNDP
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Demonstration boards
STV9211
12
DEMONSTRATION BOARDS
Figure 27: STV9211 + STV9556/55/53 + STV9936S/P demonstration board schematic
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HS C1 110V R29 39 5V BLK ABL 8V 12V R4 2.7 100pF R11 2.7 U1 C26 R25 100 100pF
R1 100
C10 C18 4.7F/160V
110V 7
5V
10nF/250V C8 C7 100nF
3
D1 R2 15 C3 IN1 BLK 20 100nF 1 5V
Blue
1N4148
47F/25V D2 FDH400
11 110/0.25W R6 RK F2 200V R R15 F4 200V GK G B CRT small neck L1 R7
D3 Vcc Vdd Out1 D4 1N4148 C4 100nF 3 IN2
C23
J1 2 ABL C31 1.5nF R9 1 In1 51 OUT1 18 HS/CLP 19
R3 75
1N4148
Green D5 1N4148 C33 1.5nF C9 100nF 4 AMPCTL VCCP 17
10pF
1 2 3 4 5 6 R8 15
R5 75
5V
D10 110V 0.33H 110/0.25W FDH400 D7
D6 R12 15 5 IN3
C24
video C6 100nF OUT2 16 2 In2 110/0.25W 110V 0.33H 110/0.25W D12 FDH400 Out2 10
Red
1N4148
R13 51
U2 STV9556
R14
D8 C22 100nF 6
R10 75
1N4148
GNDA
GNDP
C5 100nF 15
10pF C36 1.5nF
FDH400 L2
R16 2.7 7
VCCA D9
C25 10pF
OUT3 SDA
4 In3 110/0.25W Out3 9 13 R22 L3 R40 100 R21 2.7k 12 5V R19 2.7k
14
R17 51
U3
8
FDH400 D13 FDH400
SDA 9 R45 15k SCL 5 6 8 10 OSD3 FBLK
R38 100
1
SDA
AVSS
16
R46 5.6k C35 10nF
OSD1 OSD2
R47 100 11
R23
BK F1 200V
0.33H 110/0.25W
SCL
GNDA
GNDS
H2
G1
G2 9 5 7
SCL
RP
10 H1
1
Heater C14 100nF
GND
VS
R35 100
3
VS
VCO
14
Vco R44 5.6k C34 10nF
C13 100pF
J10 110V J7 GND 5V
STV9211
L4 1H 3.3V SDA 1 2 3 4 I2C R28 0 C21 10nF/250V optional
HFLY R41 100 C2 C37 100F/25V 100nF
4 HFLY
AVDD 13
AVdd
R43 1M
4.7nF/2kV
C19 F3 1.5
Figure 28: STV9211 - STV9556 - STV9936S/P application schematic
ADCS 7244743
GNDP
3.3V
L5 1H
5
DVDD
FBLK
12
C28 100nF
C12 100pF
6 R36 330 R32 330
DVSS BOUT
11
G1
R27 150/0.25W
D11 1N4004
C20 4.7nF/1kV
R31 30/0.5W
C32
7
TEST GOUT
10
100F/25V
8 OVDD ROUT 9 R33 330
12V 8V 110V J16 C16 47F/25V C15 BLK
3.3V R37 51
HS1 5V 1 2 3 RadAB20
STV9936 R34 330 J17 G1 HEATER VS HS HFLY
J8 G2
1 2 3 4 5 6 7 8 47F/25V Power C27 47F/25V
3V0
STMicroelectronics Monitor BusinessUnit - Video application CMG - Imagingand Display Division(IDD) 12, rue Jules Horowitz- B.P. 217 38019 Grenoblecedex - FRANCE
7 6 5 4 3 2 1
ABL
ZD1
C27 47F/25V
Sync
EVALCRT52/STV955xdemoboard(AB25)
Version1.4
WednesdayOctober3, 2001
12 GND
SCL
R39 100
2
15
Rp
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Demonstration boards
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Package mechanical data
STV9211
13
PACKAGE MECHANICAL DATA
Figure 29: 20 pins - plastic dip
R1 N
e4
N
K1 I K2 A a1 b R1 B e Z e3 D 20 1 R2 Dimensions A a1 B b b1 C D E e e3 e4 F I L N R1 R2 K K1 K2 Z Min. 3.25 1.39 0.381 0.20 5.20 24.9 7.8 2.29 22.60 7.36 6.22 3.42 3.17 Millimetres Typ. 3.30 0.508 0.457 0.254 5.33 25.15 8.5 2.54 22.86 7.62 6.35 3.68 3.30 7d 0.152 0.762 1.524 0.762 0.762 1.27 Max. 3.35 1.65 0.533 0.30 5.46 25.4 9.1 2.79 23.11 7.87 6.50 3.93 3.42 Min. 0.128 0.055 0.015 0.008 0.205 0.980 0.307 0.090 0.890 0.290 0.245 0.135 0.125 11 10 1.34 L
Tie Bar Center
Inches Typ. 0.130 0.020 0.018 0.010 0.210 0.990 0.335 0.100 0.900 0.300 0.250 0.145 0.130 7d 0.006 0.030 0.060 0.030 0.030 0.050
N K C F E Max. 0.132 0.065 0.021 0.012 0.215 1.000 0.358 0.110 0.910 0.310 0.255 0.155 0.135 0.053 b1
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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