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(R)
ISL6161
Data Sheet January 2003 FN9104
PRELIMINARY
Dual Power Distribution Controller
The ISL6161 is a HOT SWAP dual supply power distribution controller that can be used in PCI-Express applications. Two external N-Channel MOSFETs are driven to distribute and control power while providing load fault isolation. At turn-on, the gate of each external N-Channel MOSFET is charged with a 10A current source. Capacitors on each gate (see the Typical Application Diagram), create a programmable ramp (soft turn-on) to control inrush currents. A built in charge pump supplies the gate drive for the 12V supply N-Channel MOSFET switch. Over current protection is facilitated by two external current sense resistors and FETs. When the current through either resistor exceeds the user programmed value the controller enters the current regulation mode. The time-out capacitor, CTIM, starts charging as the controller enters the time out period. Once CTIM charges to a 2V threshold, both the NChannel MOSFETs are latched off. In the event of a hard and fast fault of at least three times the programmed current limit level, the N-Channel MOSFET gates are pulled low immediately before entering the time out period. The controller is reset by a rising edge on the ENABLE pin. The ISL6161 constantly monitors both output voltages and reports either one being low on the PGOOD output as a low. The 12V PGOOD Vth is 10.8V and the 3.3V Vth is 2.8V nominally.
Features
* HOT SWAP Dual Power Distribution and Control for +12V and +3.3V * Provides Fault Isolation * Programmable Current Regulation Level * Programmable Time Out * Charge Pump Allows the Use of N-Channel MOSFETs * Power Good and Over Current Latch Indicators * Adjustable Turn-On Ramp * Protection During Turn-On * Two Levels of Current Limit Detection Provide Fast Response to Varying Fault Conditions * 1s Response Time to Dead Short * 3s Response Time to 200% Current Overshoot
Applications
* PCI-Express Applications * Power Distribution and Control * Hot Plug, Hot Swap Components
Ordering Information
PART NUMBER ISL6161CB TEMP. RANGE (oC) -0 to 70 PACKAGE 14 Ld SOIC PKG. NO. M14.15
Pinout
ISL6161 (SOIC) TOP VIEW
Typical Application Diagram
CPUMP RSENSE 12VS 12VG VDD NC 1 2 3 4 5 6 7 14 12VISEN 13 RILIM 12 GND 11 CPUMP 10 CTIM 9 8 PGOOD 3VISEN 3.3V CGATE OPTIONAL VDD RFILTER CFILTER CGATE 12V RGATE ISL6161 12VS 12VG VDD ENABLE INPUT RGATE 12VISEN RILIM GND CPUMP CTIM 3.3V RILIM RLOAD
ENABLE 3VG 3VS
CTIM ENABLE PGOOD 3VG 3VS 3ISEN RSENSE
RLOAD
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Hot PlugTM is a trademark of Core International, Inc.
Simplified Schematic
RSENSE 12VIN
TO LOAD
12VS
OC
CLIM + -
R 100A 2R
12V
12ISEN
10A
2
12VG FALLING EDGE DELAY 18V CGATE 20 OPTIONAL VDD RFILTER CFILTER NC RISING EDGE RESET VDD R QN R Q S 20 CGATE 10A 3VG ENABLE 12V ENABLE FALLING EDGE DELAY 3VS 5VIN
RILIM + 3X RILIM 18V POR GND QPUMP
ENABLE
ENABLE
ISL6161
12V 10A
CPUMP CPUMP
TO VDD
12V CTIM 3X + CLIM + PGOOD OC R OPTIONAL 3ISEN ISL6161 2R + 2V CTIM + PGOOD OC LATCH
RSENSE
TO LOAD
ISL6161 Pin Descriptions
PIN # 1 SYMBOL 12VS FUNCTION 12V Source DESCRIPTION Connect to source of associated external N-Channel MOSFET switch to sense output voltage. Connect to the gate of associated N-Channel MOSFET switch. A capacitor from this node to ground sets the turn-on ramp. At turn-on this capacitor will be charged to 17.4V by a 10A current source. A small resistor (10 - 200) should be placed in series with the gate capacitor to ground to prevent current oscillations. Connect to 12V supply. This can be either connected directly to the +12V rail supplying the load voltage or to a dedicated VDD +12V supply. If the former is chosen special attention to VDD decoupling must be paid.
2
12VG
12V Gate
3
VDD
Chip Supply
4 5
NC ENABLE
Not Connected Enable / Reset ENABLE is used to turn-on and reset the chip. Both outputs turn-on when this pin is driven low. After a current limit time out, the chip is reset by the rising edge of a reset signal applied to the ENABLE pin. This input has 100A pull up capability which is compatible with 3V and 5V open drain and standard logic. Connect to the gate of the external 3V N-Channel MOSFET. A capacitor from this node to ground sets the turn-on ramp. At turn-on this capacitor will be charged to 11.4V by a 10A current source. A small resistor (10 - 200) should be placed in series with the gate capacitor to ground to prevent current oscillations. Connect to the source side of 3V external N-Channel MOSFET switch to sense output voltage. Connect to the load side of the 3V sense resistor to measure the voltage drop across this resistor between 3VS and 3VISEN pins. Indicates that all output voltages are within specification. PGOOD is driven by an open drain N-Channel MOSFET. It is pulled low when any output is not within specification. Connect a capacitor from this pin to ground. This capacitor controls the time between the onset of current limit and chip shutdown (current limit time-out). The duration of current limit time-out (in seconds) = 200k x CTIM (Farads). Connect a 0.1F capacitor between this pin and VDD (pin3). Provides charge storage for 12VG drive
6
3VG
3V Gate
7
3VS
3 Source
8
3VISEN
3V Current Sense
9
PGOOD
Power Good indicator
10
CTIM
Current Limit Timing Capacitor
11
CPUMP GND RILIM
Charge Pump Capacitor Chip Ground Current Limit Set Resistor
12 13
A resistor connected between this pin and ground determines the current level at which current limit is activated. This current is determined by the ratio of the RILIM resistor to the sense resistor (RSENSE). The current at current limit onset is equal to 10A x (RILIM/ RSENSE). The ISL6161 is limited to a 10k min. value (OC Vth = 100mV) resistor whereas the ISL6161 can accommodate a 5k resistor for a lower OC Vth (50mV). Connect to the load side of sense resistor to measure the voltage drop across this resistor.
14
12VISEN
12V Current Sense
3
ISL6161
Absolute Maximum Ratings TA = 25oC
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +16V 12VG, CPUMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 21V 12VISEN, 12VS . . . . . . . . . . . . . . . . . . . . . . . . . . -5V to VDD + 0.3V 3VISEN, 3VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5V to 7.5V PGOOD, RILIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7.5V ENABLE, CTIM, 3VG . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV (Class 2)
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only)
Operating Conditions
VDD Supply Voltage Range . . . . . . . . . . . . . . . . . . . +10.5V to +13.2 Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications
PARAMETER 12V CONTROL SECTION Current Limit Threshold Voltage (Voltage Across Sense Resistor)
VDD = 12V, CVG = 0.01F, CTIM = 0.1F, RSENSE = 0.1, CBULK = 220F, ESR = 0.5, TA = TJ = 0oC to 70oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
VIL12V VIL12V 3XViL12V 3XVIL12V 20%iLrt 10%iLrt 1%iLrt RTSHORT tON12V ION12V 3XdisI 12VVUV V12VG
RILIM =10k RILIM = 5k RILIM =10k RILIM = 5k 200% Current Overload, RILIM = 10k, RSHORT = 6.0 200% Current Overload, RILIM = 10k, RSHORT = 6.0 200% Current Overload, RILIM = 10k, RSHORT = 6.0 C12VG = 0.01F C12VG = 0.01F C12VG = 0.01F 12VG = 18V
92 47 250 100 8 0.5 10.5
100 53 300 165 2 4 10 500 12 10 0.75 10.8 17.3
108 59 350 210 1000 12 11.0 17.9
mV mV mV mV s s s ns ms A A V V
3X Current Limit Threshold Voltage (Voltage Across Sense Resistor) 20% Current Limit Response Time (Current within 20% of Regulated Value) 10% Current Limit Response Time (Current within 10% of Regulated Value) 1% Current Limit Response Time (Current within 1% of Regulated Value) Response Time To Dead Short Gate Turn-On Time Gate Turn-On Current 3X Gate Discharge Current 12V Under Voltage Threshold Charge Pumped 12VG Voltage 3.3V CONTROL SECTION Current Limit Threshold Voltage (Voltage Across Sense Resistor) 3X Current Limit Threshold Voltage (Voltage Across Sense Resistor) 20% Current Limit Response Time (Current within 20% of regulated value) 10% Current Limit Response Time (Current within 10% of Regulated Value) 1% Current Limit Response Time (Current within 1% of Regulated Value) Response Time To Dead Short
CPUMP = 0.1F
16.8
VIL3V 3XVIL3V
RILIM =10k RILIM = 5k RILIM =10k RILIM = 5k I 200% Current Overload, RILIM = 10k, RSHORT = 2.5 200% Current Overload, RILIM = 10k, RSHORT = 2.5 200% Current Overload, RILIM = 10k, RSHORT = 2.5
92 47 250 100 -
100 53 300 155 2 4 10 500
108 59 350 210 -
mV mV mV mV s
s s 800 ns
RTSHORT
CVG = 0.01F
4
ISL6161
Electrical Specifications
PARAMETER Gate Turn-On Time Gate Turn-On Current 3X Gate Discharge Current 3.3V Under Voltage Threshold 3.3VG High Voltage VDD = 12V, CVG = 0.01F, CTIM = 0.1F, RSENSE = 0.1, CBULK = 220F, ESR = 0.5, TA = TJ = 0oC to 70oC, Unless Otherwise Specified (Continued) SYMBOL tON3V ION3V 3XdisI 3.3VVUV 3VG TEST CONDITIONS CVG = 0.01F CVG = 0.01F CVG = 0.01F, ENABLE = Low MIN 8 0.5 2.7 11.2 TYP 5 10 0.75 2.85 11.9 MAX 12 3.0 UNITS ms A A V V
SUPPLY CURRENT AND IO SPECIFICATIONS VDD Supply Current VDD POR Rising Threshold VDD POR Falling Threshold Current Limit Time-Out ENABLE Pull-up Voltage ENABLE Rising Threshold ENABLE Hysteresis ENABLE Pull-Up Current Current Limit Time-Out Threshold (CTIM) CTIM Charging Current CTIM Discharge Current CTIM Pull-Up Current RILIM Pin Current Source Output Charge Pump Output Current Charge Pump Output Voltage Charge Pump Output Voltage - Loaded Charge Pump POR Rising Threshold Charge Pump POR Falling Threshold TILIM PWRN_V PWR_Vth PWR_hys PWRN_I CTIM_Vth CTIM_I CTIM_disI CTIM_disI RILIM_Io Qpmp_Io Qpmp_Vo Qpmp_VIo Qpmp+Vth Qpmp-Vth CPUMP = 0.1F, CPUMP = 16V No load Load current = 100A VCTIM = 8V CTIM = 0.1F ENABLE pin open IVDD 4 9.5 9.3 16 1.8 1.1 0.1 60 1.8 8 1.7 3.5 90 320 17.2 16.2 15.6 15.2 8 10.0 9.8 20 2.4 1.5 0.2 80 2 10 2.6 5 100 560 17.4 16.7 16 15.7 10 10.7 10.3 24 3.2 2 0.3 100 2.2 12 3.5 6.5 110 800 16.5 16.2 mA V V ms V V V A V A mA mA A A V V V V
ISL6161 Description and Operation
The ISL6161 is a multi featured +12V and +3.3V dual power supply distribution controller, features include programmable current limiting regulation and time to latch off. With the ENABLE internal pull-up the ISL6161 is well suited for implementation on either side of the connector where a motherboard prebiased condition or a load board staggered connection is present. In either case the ISL6161 turns on in a soft start mode protecting the supply rail from sudden current loading. At turn-on, the gate capacitor of each external N-Channel MOSFET is charged with a 10A current source. These capacitors create a programmable ramp (soft turn-on). A charge pump supplies the gate drive for the 12V supply control FET switch driving that gate to 17V. The load currents pass through two external current sense resistors. When the voltage across either resistor exceeds the user programmed Over Current (OC) voltage threshold value, 5
(see Table 1) the controller enters current regulation. The OC Vth is set by the external resistor value on RILIM pin. At this time the time-out capacitor, CTIM, starts charging with a 10A current source and the controller enters the time out period. The length of the time out period is set by the single external capacitor (see Table 2) placed from the CTIM pin (pin 10) to ground and is characterized by a lowered gate drive voltage to the appropriate external N-Channel MOSFET. Once CTIM charges to 2V, an internal comparator is tripped resulting in both N-Channel MOSFETs being latched off.
TABLE 1. RILIM RESISTOR 10k 7.5k 4.99k NOTE: Nominal OC Vth = Rilim x 10A. NOMINAL OC VTH 100mV 75mV 50mV
ISL6161
TABLE 2. CTIM CAPACITOR 0.022F 0.047F 0.1F NOMINAL TIME OUT PERIOD 4.4ms 9.4ms 20ms
With the high levels of inrush current e.g., highly capacitive loads and motor start up currents, choosing the current limiting level is crucial to provide both protection and still allow for this inrush current without latching off. Consider this in addition to the time out delay when choosing MOSFETs for your design. Physical layout of Rsense resistors is critical to avoid the possibility of false over current occurrences. Ideally trace routing between the Rsense resistors and the ISL6161 is direct and as short as possible with zero current in the sense lines.
NOTE: Nominal time-out period in seconds = CTIM x 200k.
The ISL6161 responds to a load short (defined as a current level 3X the OC set point) immediately, driving the relevant N-Channel MOSFET gate to 0V in less than 1s. The gate voltage is then slowly ramped up turning on the N-Channel MOSFET to the programmed current limit level, this is the start of the time out period. The programmed current level is held until either the OC event passes or the time out period expires. If the former is the case then the N-Channel MOSFET is fully enhanced and the CTIM charging current is diverted away from the capacitor. If the time out period expires prior to OC resolution then both gates are quickly pulled to 0V turning off both N-Channel MOSFETs simultaneously. Upon any OC or UV condition the PGOOD signal will pull low when tied high through a resistor to the logic supply. This pin is a fault indicator but not the OC latch off indicator. For an OC latch off indication, monitor CTIM, pin 10. This pin will rise rapidly to 12V once the time out period expires. See block diagram for OC latch off circuit suggestion. The ISL6161 is reset by a rising edge on the ENABLE pin and is turned on by the ENABLE pin being driven low.
CORRECT
INCORRECT
TO ISEN AND RISET
CURRENT SENSE RESISTOR
FIGURE 1. SENSE RESISTOR PCB LAYOUT
ISL6161 Application Considerations
Current loop stabilization is facilitated through a small value resistor in series with the gate timing capacitor. As the ISL6161 drives a highly inductive current load, instability characterized by the gate voltage repeatedly ramping up and down may appear. A simple method to enhance stability is provided by the substitution of a larger value gate resistor. Typically this situation can be avoided by eliminating long point to point wiring to the load. During the Time Out delay period with the ISL6161 in current limit mode, the VGS of the external N-Channel MOSFETs is reduced driving the N-Channel MOSFET switch into a high rDS(ON) state. Thus avoid extended time out periods as the external N-Channel MOSFETs may be damaged or destroyed due to excessive internal power dissipation. Refer to the MOSFET manufacturers data sheet for SOA information.
Open load detection can be accomplished by monitoring the ISEN pins. Although gated off the external FET IDSS will cause the ISEN pin to float above ground to some voltage when there is no attached load. If this is not desired 5k resistors from the xISEN pins to ground will prevent the outputs from floating when the external switch FETs are disabled and the outputs are open. For PCI-Express applications the ISL6161 and the ISL6118 provide the fundamental hotswap function for the +12V & +3.3V main rails and the +3.3V aux respectively as shown in Figure 13.
6
ISL6161 Typical Performance Curves
8.4 8.2 SUPPLY CURRENT (mA) 105
8.0 7.8 7.6 7.4 7.2 -40 CURRENT (A) -30 -20 -10 0 10 20 30 40 50 60 70 80
104
103
102 -40
-30
-20
-10
0
10
20
30
40
50
60
70
80
TEMPERATURE (oC)
TEMPERATURE (oC)
FIGURE 2. SUPPLY CURRENT
FIGURE 3. RILIM SOURCE CURRENT
10.7 2.04 CTIM OC VOLTAGE THRESHOLD (V) -30 -20 -10 0 10 20 30 40 50 60 70 80 CTIM CURRENT SOURCE (A)
10.6
2.02
2.00
10.5
1.98
10.4
1.96
10.3 -40
TEMPERATURE (oC)
1.94 -40
-30 -20 -10
0
10
20
30
40
50
60
70
80
TEMPERATURE (oC)
FIGURE 4. CTIM CURRENT SOURCE
FIGURE 5. CTIM OC VOLTAGE THRESHOLD
10.92
2.875
3.3V UV THRESHOLD (V)
12V UV THRESHOLD (V)
2.8725
10.902
2.870
10.886
2.8675
10.87 -40
-20
0
20
40
60
80
2.865 -40
-20
0
20
40
60
80
TEMPERATURE (oC)
TEMPERATURE (oC)
FIGURE 6. 12V UV THRESHOLD
FIGURE 7. 3.3V UV THRESHOLD
7
ISL6161 Typical Performance Curves
17.36
(Continued)
11.935 11.930
17.6
17.34 12V GATE DRIVE (V) VOLTAGE (V) 12V VG 17.32 11.925 11.920 11.915 3.3VG 17.28 11.905 17.26 -40 -20 0 20 40 60 TEMPERATURE (oC) 11.900 80 11.910 3.3V GATE DRIVE (V)
17.4 CHARGE PUMP VOLTAGE NO LOAD 17.2
17.30
17.0 CHARGE PUMP VOLTAGE 100A LOAD
16.8
16.6 -40
-20
0 20 40 TEMPERATURE (oC)
60
80
FIGURE 8. 12V, 3V GATE DRIVE
FIGURE 9. PUMP VOLTAGE
54.5 VOLTAGE THRESHOLD (mV) VOLTAGE THRESHOLD (mV)
102.5
54.0
12 OC Vth
102.0
12 OC VTth
53.5
101.5
3.3 OC Vth 53.0
101.0
3.3 OC Vth
52.5 -40
-20
0
20
40
60
80
100.5 -40
-20
0
20
40
60
80
TEMPERATURE (oC)
TEMPERATURE (oC)
FIGURE 10. OC VOLTAGE THRESHOLD WITH RLIM = 5k
FIGURE 11. OC VOLTAGE THRESHOLD WITH RLIM = 10k
10.2 VDD LOW TO HIGH POWER ON RESET (V)
10.0
9.8
VDD HIGH TO LOW
9.6 -40
-30 -20 -10
0
10
20
30
40
50
60
70
80
TEMPERATURE (oC)
FIGURE 12. POWER ON RESET VOLTAGE THRESHOLD
8
PCI-EXPRESS Implementation of ISL6161 and ISL6118
INTERSIL ISL6161 12V, 3.3V POWER CONTROLLER INTERSIL ISL6161 12V, 3.3V POWER CONTROLLER SLOT 1 PWREN# SLOT 2 PWREN# SLOT 1 PWRGD SLOT 2 PWRGD
3.3V GATE SWITCH
+12V GATE SWITCH
3.3V GATE SWITCH
3.3V 3.3V
+12V GATE SWITCH
+12V
+12V
3.3V
3.3V
INTERSIL ISL6118 3.3VSB DUAL 3.3VAUX POWER CONTROLLER
FIGURE 13.
3.3VAUX
3.3VAUX
9
12V +12V
CONTROLLER
ISL6161
SLOT 1 PRSNT
SLOT 2 PRSNT
PCI-EXPRESS SLOT 1
PCI-EXPRESS SLOT 2
SLOT 2 PWREN# SLOT 1 PWREN# SLOT 2 PWRFLT# SLOT 1 PWRFLT#
ISL6161 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M14.15 (JEDEC MS-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 8.55 3.80 MAX 1.75 0.25 0.51 0.25 8.75 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0532 0.0040 0.013 0.0075 0.3367 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.3444 0.1574
A1 B C D E

A1 0.10(0.004) C
e
B 0.25(0.010) M C AM BS
e H h L N
0.050 BSC 0.2284 0.0099 0.016 14 0o 8o 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 14 0o 6.20 0.50 1.27
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 10

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