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S E M I C O N D U C T O R, I N C .
Figure 1. Block Diagram
FBIN
11
GA1086
S1
10
CLK
9
S0
8
NC
7
NC
6
GND
5
S2
12
VDD 13 Q/2 14 GND 15 FBOUT 16 Q1
17
Control Logic
Phase Detector VCO
4 VDD 3 2
Q9 Q8
11-Output Clock Buffer
Features
* Operates from 30 MHz to 67MHz * Pin-to-pin output skew of 250 ps (max) * Period-to-period jitter: 75 ps (typ) * Near-zero propagation delay: -350 ps 500 ps or -350 ps 1000 ps * 10 symmetric, TTL-compatible outputs with 30 mA drive and rise and fall times of 1.4 ns(max)
SYSTEM TIMING PRODUCTS
Divide Logic MUX Precision Output Buffers
1 GND 28 27
Q7 Q6
VDD 18
26 VDD
19
20
21
22
23
24
25
GND
Q2
Q3
VDD
Q4
Q5
GND
TriQuint's GA1086 operates from 30 MHz to 67 MHz. This TTL-level clock buffer chip supports the tight timing requirements of high-performance microprocessors, with near zero input-to-output delay and very low pin-topin skew. The device offers 10 usable outputs synchronized in phase and frequency to a periodic clock input signal. One of the ten outputs is a onehalf clock output (CLK / 2). With split termination, the GA1086 can be used to drive up to nineteen 15 pF loads, as shown in Figure 10. The tight control over phase and frequency of the output clocks is achieved with a 400 MHz internal Phase-Locked Loop (PLL). By feeding back one of the output clocks to FBIN, the on-chip PLL continuously maintains synchronization between the input clock (CLK) and all ten outputs. Any drift or gradual variation in the system clock is matched and tracked at the ten outputs. The GA1086 output buffers are symmetric, each sourcing and sinking up to 30 mA of drive current. For diagnostic purposes, the device has a test mode which is used to test the device and associated logic by single-stepping through the control logic. The GA1086 is fabricated using TriQuint's One-UpTM gallium arsenide technology to achieve precise timing control and to guarantee 100% TTL compatibility. The output frequency makes this device ideal for clock generation and distribution in a wide range of high-performance microprocessor-based systems. Many other CISC- and RISC-based systems will also benefit from its tight control of skew and delay.
* 28-pin J-lead surface-mount package * Special test mode * Meets or exceeds PentiumTM processor timing requirements * Typical applications include low-skew clock distribution for: * RISC- or CISC-based systems * Multi-processor systems * High-speed backplanes
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1
GA1086
Functional Description
The GA1086 generates 10 outputs (Q1 - Q9 and FBOUT) which have the same frequency and zero phase delay relative to the reference clock input. In addition, there is one output (Q/2) that has 1/2 the frequency of the reference clock. The GA1086 maintains frequency and zero phase delay using a Phase Detector to compare the output clock with the reference clock input. Phase deviations between the output clock and reference clock are continuously corrected by the PLL. Figure 1 shows a block diagram of the PLL, which consists of a Phase Detector, Voltage Controlled Oscillator (VCO), Divide Logic, Mux and Control Logic. The Phase Detector monitors the phase difference between FBIN which is connected to FBOUT, and the reference clock (CLK). The Phase Detector adjusts the VCO such that FBIN aligns with CLK. The VCO has an operating range of 360 MHz to 402 MHz. The output clocks (Qn, FBOUT, and Q/2) are generated by dividing the VCO output. The desired operating frequency determines the proper divide mode. There are 4 divide modes; /12, /10, /8 and /6. In each mode, the GA1086 operates across the frequency range listed in the Divide Mode Selection Table. The operating frequency is equivalent to the VCO frequency divided by the mode number. Table 1 shows the input clock frequency (CLK), output clock frequency (Qn), 1/2 output clock frequency (Q/2),
control bit settings, divide mode and VCO range. FBOUT is fed back to FBIN and has the same frequency as the Qn outputs. The GA1086 has a test mode that allows for single stepping of the clock input for testing purposes. With S2 HIGH, S1 LOW and S0 HIGH, the signal at the CLK input goes directly to the outputs, bypassing the PLL circuitry. The maximum rise and fall time at the output pins is 1.4 ns. All outputs of the GA1086 are TTL-compatible with 30 mA symmetric drive and a minimum VOH of 2.4 V. The GA1086-MC500 and GA1086-MC1000 are identical except for the propagation delay specification (see AC Characteristics table).
Breaking the Feedback Loop
There is no requirement that the external feedback connection be a direct hardwire from an output pin to the FBIN pin. As long as the signal at FBIN is derived directly from the FBOUT pin and maintains its frequency, additional delays can be accommodated. The internal phase-locked loop will adjust the output clocks on the GA1086 to ensure zero phase delay between the FBIN and CLK signals.
Note: the signal at FBIN must be continuous, i.e. not a gated or conditional signal.
Table 1. Divide Mode Selection Table
CLK
30 - 33 MHz 36 - 40 MHz 45 - 50 MHz 60 - 67 MHz TSTCLK
Qn
30 - 33 MHz 36 - 40 MHz 45 - 50 MHz 60 - 67 MHz TSTCLK
Q/2
15 - 16.5 MHz 18 - 20 MHz 22.5 - 25 MHz 30 - 33.5 MHz TSTCLK/2
S2
1 1 1 0 1
Control S1
1 1 0 1 0
S0
1 0 0 1 1
Divide Mode
/12 /10 /8 /6 --
2
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GA1086
Power-Up/Reset Synchronization
The GA1086 utilizes on-chip phase-locked loop (PLL) technology to maintain synchronization between inputs and outputs. Whenever the device is powered up, or the system clock (CLK) is reset, the phase-locked loop requires a synchronization time (tSYNC) before lock is achieved. The maximum time required for synchronization is 500 ms.
obtained by summing the various skews. The skew between the outputs of the GA1086 (1) which drive the GA1086 (2) and the GA1086 (n) is summed with the propagation delay of the GA1086 (2 or n), the skew between the outputs of the GA1086 (2), and the skew between the outputs of the GA1086 (n). This results in a total skew of 1.75 ns (250 ps + 1000 ps + 250 ps + 250 ps).
2) Board-to-Board Synchronization Many computing systems today consist of multiple boards designed to run synchronously. The skew associated with routing clocks across a backplane presents a major hurdle to maximizing system performance.
Typical Applications
The GA1086 is designed to satisfy a wide range of system clocking requirements. Following are two of the most common clocking bottlenecks which can be solved using the GA1086. 1) Low-Skew Clock Distribution / Clock Trees The most basic bottleneck to clocking high-performance systems is generating multiple copies of a system clock, while maintaining low skew throughout the system.
* The edge placement feature of TriQuint's configurable custom clock generator (GA1110E) operating at 33 MHz, coupled with the tightly controlled input/output delay of the GA1086, ensures all boards in the system are running synchronously.
SYSTEM TIMING PRODUCTS
* The GA1086 guarantees low skew among all clocks in the system by controlling both the input-tooutput delay and the skew among all outputs. In Figure 2, the worst-case skew from Output 1 to Output n, with reference to the system clock, is Figure 2. Low-Skew Clock Distribution
Figure 3. Board-to-Board Synchronization
HOST TARGETS
SYS CLK
GA1110E
GA1000
t -t -2t
GA1086
SYSTEM CLOCK
Q1 GA1086 (1) Q/2 * * *
Q1 GA1086 (2) Q9 * * *
OUTPUT 1
GA1086 (n)
* * * OUTPUT n
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3
GA1086
Multi-Processor Systems
The GA1086 can be effectively used to distribute clocks in RISC- or CISC-processor-based systems. Its 10 outputs support both single- and multi-processor systems. Following are three representative configurations which show how the 10 outputs can be used to synchronize the operation of CPU cache and memory banks operating at different speeds. Figure 4 depicts a 2-CPU system in which the processors and associated peripherals are operating at 66 MHz. Each of the nine outputs operating at 66 MHz are fully utilized to drive the appropriate CPU, cache, and memory control logic. The 33 MHz output is used to synchronize the operation of the slower memory bank to the rest of the system.
Figure 4. Clocking a Dual-CPU System
R CPU 1 CACHE R Q1 Q2 Q3 Q4 R R R MEMORY CONTROL LOGIC (66 MHZ)
FBIN SYSTEM CLOCK CLK
FBOUT
GA1086
R Q5 R Q6 Q7 R R R Q9 R Q/2 SLOW MEMORY CONTROL LOGIC (33 MHZ) CPU 2 CACHE
LOW HIGH HIGH
S2 S1 S0
Q8
4
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GA1086
Multi-Processor Systems (cont.)
Figure 5 shows a 4-processor system with various 33 MHz memory banks synchronized to the 66 MHz CPUs. The GA1110E, a custom device whose six outputs can be individually configured, (see GA1110E data sheet), is used as the clock source for the GA1086 devices. This configuration gives the user 18 copies of the 66 MHz clock and 7 copies of the 33 MHz clock. By using the configurability of the GA1110E, the user can also specify and control the placement of the edges of the outputs of the GA1110E.
Figure 5. Generating Multiple Outputs
R
FBIN
FBOUT Q1
FBIN
FBOUT
33 MHz
1
33MHzMHz 66
6 pF
GA1000
Q1 Q2 Q3 Q4 Q5 -t - 2t - 3t
GA1110E
GA1086 MC500
CLK Q9 Q/2 R
9 @ 66 MHz
3
4 @ 33 MHz
2
33 MHz
33 MHz
CLK
Note: The GA1000 is a custom device whose outputs can be customized to the user's requirement. The figure above is one possible configuration.
Max Pin-to-Pin Skew from: 1 1 1 2 2 3 3 4 to 2 = 1.2 ns* to 3 = 1.75 ns to 4 = 1.5 ns to 3 = 2.7 ns* to 5 = 3.2 ns* to 4 = 1.75 ns to 5 = 2.7 ns* to 5 = 1.2 ns*
FBIN
FBOUT Q1
4
6 pF
GA1086 MC500
CLK Q9 Q/2
9 @ 66 MHz
5
33 MHz
* Assumes maximum skew between Q9 and Q/2 is 1.2 ns. See AC specifications.
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SYSTEM TIMING PRODUCTS
GA1086
Single-Processor Systems
Figure 6 is an example of a single-CPU system. The nine 66MHz outputs of the GA1086 are used to drive the CPU and its related cache, the state machine, memory banks, and other general-purpose logic.
The table in Figure 5 also specifies the maximum pinto-pin skew of various sets of outputs from the three clocking devices. Please note that the GA1086s are series-terminated and that the feedback trace lengths for the two devices should be equal.
Figure 6. Clocking a Single-CPU System
R CPU CACHE FBIN SYSTEM CLOCK CLK FBOUT R Q1 Q2 Q3 Q4 R R R STATE MACHINE
GA1086
R Q5 R Q6 R Q7 R Q8 R Q9 R Q/2 LOGIC BLOCK 1
LOW HIGH HIGH
S2 S1 S0
MEMORY CONTROL
LOGIC BLOCK 2
6
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GA1086
Parallel Termination of Outputs
The GA1086 can be terminated either in parallel or in series. If power dissipation is not of primary concern, then parallel termination can be the most effective mode of termination for the GA1086. An example of this termination is shown in Figure 7, along with the waveforms at an output pin and at the load. Note that the Thevenin equivalent using two resistors and +5 V supply can replace the 65 ohms to 1.5 V. Unused outputs must be terminated.
Figure 7. Parallel Termination
R OUT A VOUT
B ZO t AB R IN
RT
Series Termination of Outputs
The alternative to parallel termination is series termination. For applications where overshoots and undershoots of the clock signal are a concern, it is best to use balanced termination as shown in Figure 8. This could, however, slow the rise time of the pulses arriving at the destination.
SYSTEM TIMING PRODUCTS
Figure 8. Balanced Termination
65 FBIN FBOUT 52
13
Q t0 52 Q t0 1.4 ns (max) 65 Q t1 30 pF Q t1 1.8 ns (typ)
CLK
13 Q
GA1086
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7
GA1086
If rise times are critical and if overshoots and undershoots can be tolerated, then unbalanced termination may be used. Reflections due to unbalanced termination can cause ringing at the load. The transmission line lengths, therefore, must be long enough to cause the ringing to occur only after the waveform has completely switched to either the LOW or the HIGH state, (the round trip). The propagation time of the output signals should be greater than the switching time for LOW to HIGH or HIGH to LOW.
To double the number of loads (devices) driven by the GA1086, split termination may be used. Examples of three types of series termination and the resulting waveforms, measured between 0.8 V and 2.0 V, are shown in Figures 9 and 10 for one of the outputs. Unused outputs must be terminated.
Figure 9. Unbalanced Termination
65 FBIN FBOUT 37 Q t0 1.4 ns (max) 37 Q t0 65
13
CLK
13 Q
Q t1 30 pF
Q t1 1.5 ns (typ)
GA1086
Figure 10. Split Unbalanced Termination
65 FBIN FBOUT 13 65 12 15 pF Q t0 1.4 ns (max) 65 13 Q Q t0 65 Q t2 15 pF Q t2 1.5 ns (typ)
Note: Rise time at Qt1 is measured between 0.8 V and 2.0 V.
Q t1 15 pF Q t1 1.5 ns (typ)
12
CLK
GA1086
8
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GA1086
Absolute Maximum Ratings
Storage temperature Ambient temperature with power applied Supply voltage to ground potential DC input voltage DC input current
Caution: Damage to the device may occur if an output is shorted to ground or VDD.
-65 C to +150 C -55 C to +100 C -0.5 V to +7.0 V -0.5 V to +(VDD + 0.5) -30 mA to +5 mA
DC Characteristics (Supply voltage: +5 V + 5% Ambient temp: 0 C to +70 C) 1
Limits 2 Typ
3.6 0.2 2.0 0.8 -166 0 2 -0.62 -400 25 1000 115 IIN = -18 mA -1.2 0.5
Symbol
VOH VOL VIH3 VIL3 IIL IIH II IDD4 VI
Description
Output HIGH voltage Output LOW voltage Input HIGH level Input LOW level Input LOW current Input HIGH current Input HIGH current Power supply current Input clamp voltage
Test Conditions
VDD = Min IOH= -30 mA VIN= VIH or VIL VDD = Min IOL = 30 mA VIN= VIH or VIL Guaranteed input logical HIGH voltage for all inputs Guaranteed input logical LOW voltage for all inputs VDD = Max VDD = Max VDD = Max VDD = Max VDD = Min VIN = 0.40 V VIN = 2.7 V VIN = 5.5 V
Min
2.4
Max
Unit
V V V
A A A 160 mA V
Capacitance 1,5
Symbol
CIN
Description
Test Conditions
Input capacitance
Min
VIN = 2.0 V at f = 1 MHz
Typ
Max
6
Unit
pF
Notes: 1. These values apply to both the GA1086-MC500 and GA1086-MC1000. 2. Typical limits are at VDD = 5.0 V and TA = 25 C. 3. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 4. IDD is measured with outputs LOW and unloaded. 5. These parameters are not 100% tested, but are periodically sampled.
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9
SYSTEM TIMING PRODUCTS
V
GA1086
AC Specifications (Supply voltage: +5 V + 5%, Ambient temp: 0 C to +70 C)
Figure 11. Switching Waveforms Buffer Configuration (FBIN = FBOUT)
Input Clocks
FIN tCP tCPW tIR CLK frequency CLK period CLK pulse width Input rise time
(0.8 V - 2.0 V)
Min
30 14.9 3.0 --
Typ
-- -- -- --
Max
67 33 -- 2.0
Unit
MHz ns ns ns
FBIN REFCLK
tCPW
tCPW
t PD1,2
t JR
Q0 - Q10 (INDIVIDUALLY)
t PERIOD t JP
Output Clocks
tOR tOF tPD11 tPD21,2
Min
Typ
-- -- -350 -350 -- -- -- 0.6 100 1.0 200 75
Max
1.4 1.4 +150 +650 +125 +125 +125 1.2 250 -- 500 --
Unit
ns ns ps ps ps ps ps ns ps ns s ps
R2 +5 V R1 Z FBIN Q0 Q1 Q2 * * * * Q10 Y 50 X +5 V R1 R2 * * * * +5 V R1 R2 +5 V R1 R2 Notes: R1 = 160 R2 = 71 Y+Z=X
Output rise time (0.8 V - 2.0 V) 0.15 Output fall time (0.8 V - 2.0 V) 0.15
CLK I to FBIN I (MC500) CLK I to FBIN I (MC1000)
-850 -1350 -125 -125 -125 -- -- -- -- --
tSKEW12,3 Q1-Q9 and FBOUT (0.8V) tSKEW12,3 Q1-Q9 and FBOUT (1.5V) tSKEW12,3 Q1-Q9 and FBOUT (2.0V) tSKEW22,3 Q/2 Output skew tW 4 tCYC 5 tSYNC 6 tJIT 7 Output window Duty-cycle variation Synchronization time Period-to-period jitter
Figure 12. AC Test Circuit
+5 V R1 R2 Z CLK
Notes: 1. The PLL maintains alignment of CLK and FBIN at all times. This specification applies to the rising edge only because the input duty cycle can vary while the output duty cycle is typically 50/50. The delay tPD is measured at the 1.5 V level between CLK and FBIN. 2. tPD and tSKEW are tested with an input clock having a rise time of 0.5 ns (0.8 V to 2.0 V). 3. The output skew is measured from the middle of the output window, tW. The maximum skew is guaranteed across all voltages and temperatures. 4. tW specifies the width of the window in which outputs Q1-Q9 switch. 5. This specification represents the deviation from 50/50 on the outputs; it is sampled periodically but is not guaranteed. 6. tSYNC is the time required for the PLL to synchronize; this assumes the presence of a CLK signal and a connection from one of the outputs to FBIN. 7. Jitter is specified as a peak-to-peak value.
10
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GA1086
28-Pin MQuad J-Leaded Package Mechanical Specification (All dimensions are in inches)
.172 .005 .490 .005 .045 X 45 .445 .005 .132 .005 .040 MIN
PIN 1 8 0.125 VENT PLUG 15 .015 X 45 22
.490 .005 .445 .005 .445 .028 .005 .018
.410 .015
.050 TYP. .060
.050 TYP. NON-ACCUM.
.104 .005
28-Pin MQuad Pin Description
SYSTEM TIMING PRODUCTS
Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Pin Name
GND Q8 Q9 VDD GND N/C N/C S0 CLK S1 FBIN S2 VDD Q/2
Description
Ground Output Clock 8 Output Clock 9 +5 V Ground No Connect No Connect Select 0 Reference Clock Select 1 Feedback In Select 2 +5 V Half-Clock Out
I/O
- O O - - - - I I I I I - O
Pin #
15 16 17 18 19 20 21 22 23 24 25 26 27 28
Pin Name
GND FBOUT Q1 VDD GND Q2 Q3 VDD Q4 Q5 GND VDD Q6 Q7
Description
Ground Feedback Clock Output Clock 1 +5 V Ground Output Clock 2 Output Clock 3 +5 V Output Clock 4 Output Clock 5 Ground +5 V Output Clock 6 Output Clock 7
I/O
- O O - - O O - O O - - O O
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11
GA1086
Layout Guidelines
Multiple ground and power pins on the GA1086 reduce ground bounce. Good layout techniques, however, are necessary to guarantee proper operation and to meet the specifications across the full operating range. TriQuint recommends bypassing each of the VDD supply pins to the nearest ground pin, as close to the chip as possible. Figure 13 shows the recommended power layout for the GA1086. The bypass capacitors should be located on the same side of the board as the GA1086. The VDD traces connect to an inner-layer VDD plane. All of the ground pins (GND) are connected to a small ground plane on the surface beneath the chip. Multiple
through-holes connect this small surface plane to an inner-layer ground plane. The capacitors (C1-C5) are 0.1 mF. TriQuint's test board uses X7R temperaturestable capacitors in 1206 SMD cases.
Figure 13. Top Layer Layout of Power Pins (Approx. 3.3x)
V DD C4
Pin 1
V DD C3
Ground Plane
V DD C2
Ordering Information
To order, please specify as shown below:
Pin 15
C5
C1 V DD
GA1086-MC n...n
500 1000
11-Output Clock Buffer
Propagation delay skew: -350 ps 500 ps -350 ps 1000 ps
V DD
Additional Information
For latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint: Web: www.triquint.com Email: sales@tqs.com Tel: (503) 615-9000 Fax: (503) 615-8900
Temperature range: 0 C to 70 C (Commercial) Package: MQuad
For technical questions and additional information on specific applications: Email: applications@tqs.com
The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or omissions. TriQuint assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems. Copyright (c) 1997 TriQuint Semiconductor, Inc. All rights reserved. Revision 1.1.A November 1997
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