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RFG75N05E Data Sheet July 1999 File Number 2275.5 75A, 50V, 0.008 Ohm, N-Channel Power MOSFET These are N-Channel enhancement mode silicon gate power field effect transistors. They are advanced power MOSFETs designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA09821. Features * 75A, 50V * rDS(ON) = 0.008 * Electrostatic Discharge Rated * UIS Rating Curve (Single Pulse) * 175oC Operating Temperature * Temperature Compensated PSPICE(R) Model Provided Symbol D Ordering Information PART NUMBER RFG75N05E PACKAGE TO-247 BRAND RFG75N05E G S NOTE: When ordering, include the entire part number. Packaging JEDEC STYLE TO-247 SOURCE DRAIN GATE DRAIN (BOTTOM SIDE METAL) 4-481 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. PSPICE(R) is a registered trademark of MicroSim Corporation. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 RFG75N05E Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFG75N05E 50 50 75 200 20 240 1.6 2 Refer to UIS SOA Curves -55 to 175 300 260 UNITS V V A A V W W/oC kV Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current (Current Limited by Package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrostatic Discharge Rating, MIL-STD-883, Category B(2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESD Single Pulse Avalanche Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg oC oC oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications PARAMETER TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS VGS = 0V, ID = 250A (Figure 9) VGS = VDS, ID = 250A (Figure 8) VDS = Rated BVDSS, VGS = 0V VDS = 0.8 x Rated BVDSS, VGS = 0V, TC = 150oC VGS = 20V VGS = 10V, ID = 75A (Figure 7) VDD = 25V, ID 37.5A, RL = 0.67, RG = 1.67, VGS = 10V, (Figure 11) MIN 50 2.0 VGS = 0, 20V VGS = 0, 10V VGS = 0, 2V VDD = 40V, ID = 75A, RL = 0.53 IG(REF) = 3.44mA (Figure 11) TYP 17 75 70 17 MAX 4.0 1 25 100 0.008 125 125 400 220 15 0.625 80 UNITS V V A A nA ns ns ns ns ns ns nC nC nC oC/W oC/W Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Drain to Source on Resistance (Note 2) Turn On Time Turn On Delay Time Rise Time Turn Off Delay Time Fall Time Turn Off Time Total Gate Charge (Gate to Source + Gate to Drain) Gate Charge at 10V Threshold Gate Charge Junction to Case Junction to Ambient IGSS rDS(ON) t(ON) td(ON) tr td(OFF) tf t(OFF) Qg(TOT) Qg(10) Qg(TH) RJC RJA Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage Diode Reverse Recovery Time NOTES: 2. Pulse test: pulse width 300s, duty cycle 2%. 3. Repetitive pulse: pulse width is limited by maximum junction temperature. 4. Refer to Intersil Application Notes AN9321 and AN9322. See Figure 4. SYMBOL VSD trr ISD = 75A ISD = 75A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.5 125 UNITS V ns 4-482 RFG75N05E Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 TC , CASE TEMPERATURE (oC) 150 175 Unless Otherwise Specified 80 70 ID, DRAIN CURRENT (A) 60 50 40 30 20 10 0 25 50 75 100 125 150 175 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 100 ID MAX CONTINUOUS 1000 IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) Idm 100 10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) DC TC = 25oC TJ = MAX RATED SINGLE PULSE STARTING TJ = 25oC STARTING TJ = 150oC If R = 0 tAV = (L)(IAS)/(1.3 RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3 RATED BVDSS - VDD) +1] 10 0.01 0.10 1 tAV, TIME IN AVALANCHE (ms) 1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 102 10 FIGURE 3. FORWARD BIAS SAFE OPERATING AREA FIGURE 4. UNCLAMPED INDUCTIVE SWITCHING SOA (SINGLE PULSE UIS SOA) IDS(ON), DRAIN TO SOURCE CURRENT (A) 200 VGS = 10V VGS = 7.0V VGS = 6.0V 200 ID, DRAIN CURRENT (A) 160 TC = 25oC 120 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 5.0V 160 VDD > ID x rDS(ON) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX -55oC 25oC 175oC 120 80 80 40 VGS = 4.0V 0 0 1.5 3.0 4.5 6.0 VDS, DRAIN TO SOURCE VOLTAGE (V) 7.5 40 0 0 8 2 4 6 VGS, GATE TO SOURCE VOLTAGE (V) 10 FIGURE 5. SATURATION CHARACTERISTICS FIGURE 6. TRANSFER CHARACTERISTICS 4-483 RFG75N05E Typical Performance Curves 3.0 NORMALIZED DRAIN TO SOURCE ON RESISTANCE ID = 75A, VGS = 10V PULSE DURATION = 80s 2.5 DUTY CYCLE = 0.5% MAX 2.0 1.5 1.0 0.5 0 -50 NORMALIZED GATE THRESHOLD VOLTAGE Unless Otherwise Specified (Continued) 2.0 ID = 250A VGS = VDS 1.6 1.2 0.8 0.4 0 50 100 150 200 0 -50 0 50 100 150 200 TJ, JUNCTION TEMPERATURE (oC) TJ, JUNCTION TEMPERATURE (oC) FIGURE 7. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 2.0 ID = 250A NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE FIGURE 8. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 6000 CISS C, CAPACITANCE (pF) 1.5 4000 COSS 1.0 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD 2000 CRSS 0.5 0 -50 0 50 100 150 200 0 0 TJ, JUNCTION TEMPERATURE (oC) 10 15 20 5 VDS, DRAIN TO SOURCE VOLTAGE (V) 25 FIGURE 9. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 50 VDD = BVDSS FIGURE 10. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 10 VGS , GATE TO SOURCE VOLTAGE (V) VDS , DRAIN TO SOURCE VOLTAGE (V) 40 VDD = BVDSS GATE SOURCE VOLTAGE 8 30 RL = 0.667 IG(REF) = 3.44mA VGS = 10V VDD = 0.75 BVDSS VDD = 0.50 BVDSS VDD = 0.25 BVDSS DRAIN SOURCE VOLTAGE 6 20 4 10 2 0 I G ( REF ) 20 -----------------------I G ( ACT ) t, TIME (s) I G ( REF ) 80 -----------------------I G ( ACT ) 0 NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 11. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT 4-484 RFG75N05E Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD + 0V IAS 0.01 0 tAV FIGURE 12. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 13. UNCLAMPED ENERGY WAVEFORMS tON VDS VDS VGS RL + tOFF td(OFF) tr tf 90% td(ON) 90% DUT RGS VGS - VDD 0 10% 90% 10% VGS 0 10% 50% PULSE WIDTH 50% FIGURE 14. SWITCHING TIME TEST CIRCUIT FIGURE 15. RESISTIVE SWITCHING WAVEFORMS VDS RL VDD VDS VGS = 20V VGS + Qg(TOT) Qg(10) VDD VGS VGS = 2V 0 Qg(TH) Ig(REF) 0 VGS = 10V DUT Ig(REF) FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORM 4-485 RFG75N05E PSpice Electrical Model DPLCAP 5 LDRAIN DRAIN 10 2 .SUBCKT RFG75N05 2 1 3 ; rev 10/30/90 oC *Nominal Temperature = 25 CA 12 8 8.98e-9 CB 15 14 8.81e-9 DBREAK Cin 6 8 4.48e-9 DPLCAP 10 5 DPLCAPMOD 11 RDRAIN Dbody 7 5 DBODYMOD + Dbreak 5 11 DBREAKMOD DBODY ESG 6 EBREAK 17 Eds 14 8 5 8 1 8 18 + Egs 13 8 6 8 1 Esg 6 10 6 8 1 16 EVTO GATE LGATE RGATE Ebreak 11 7 17 18 58.4 + 18 6 1 MOS EVTEMP 20 6 18 8 1 9 20 22 IT 8 17 1 RIN CIN Ldrain 2 5 e-10 LSOURCE Lgate 1 9 5e-9 RSOURCE 8 3 Lsource 3 7 3e-9 7 SOURCE Mos 16 6 8 8 MODMOD Rbreak 17 18 RBREAKMOD 1 S1A S2A Rdrain 5 16 RSOURCEMOD 3.07e-3 RBREAK 12 15 14 13 Rgate 9 20 1.2 18 17 8 13 Rin 6 8 1e9 S1B S2B RVTEMP Rsource 8 7 RSOURCEMOD 2.e-3 13 CB RVTEMP 18 19 RVTONEGMOD 1 19 CA IT 14 S1a 6 12 13 8 S1AMOD + + VBAT 6 S1b 13 12 13 8 S1BMOD EDS 5 EGS + 8 8 S2A 6 15 14 13 S2AMOD 8 S2b 13 15 14 13 S2AMOD Vbat 8 19 DC 1 .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.48 VOFF=-0.48) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.48 VOFF=-2.48) .MODEL S2AMOD VSWITCH (RON=1e=5 ROFF=0.1 VON=-2.25 VOFF=2.75) .MODEL S2ABMOD VSWITCH (RON=1e-5 ROFF=0.1 VON =2.75 VOFF=-2.25) .MODEL DBODYMOD D (IS=2.23e-12 RS=249e-3 TRS1=2.5e-3 CJO=7.55e-9 TT=4e-8) .MODEL DBREAKMOD D (RS=8e-2 TRS1=2.5e-3) .MODEL DPLCAPMOD D (IS=1e-30 N=10 CJO=2.14e-9) .MODEL RBREAKMOD RES (TC1=9.5e-4 TC2=-1.17e-6) .MODEL RSOURCEMOD RES (TC1=5.2e-3 TC2=1.37e-5) .MODEL RVTONEGMOD RES (TC1=-3.78e-3 TC2=-7.51e-7) .MODEL MODMOD NMOS (VTO=3.48 N=10 IS=1e-30 KP=78.5 TOX=1 L=1u W1u) .ENDS All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 4-486 |
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