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| ES3880 Video CD MPEG Processor Product Brief DESCRIPTION The ES3880 Video CD MPEG processor is ESS' third generation highly integrated, optimal quality, and costeffective single chip solution for Video CD players. The ES3880 is the best quality available for both video and audio and easily passes the highest graded level for the China VCD standard. The ES3880 integrates MPEG-1 video and audio processing and a full-fledged MPEG system bit stream parser. The ES3880 can be used as a microcontroller to provide system control, while also performing such basic video operations as arbitrary scaling and video filtering. The MPEG-1 system layer bitstream is decoded at up to 9 Mb/s at Standard Intermediate Format (SIF) resolution with a picture rate of 30 frames per second. Two channels of MPEG-1 Layer 1 or Layer 2 audio are decoded simultaneously. The ES3880 supports SmartScale advanced scaling techniques, along with SmartStream for audio and video error concealment, and SmartZoom for enabling in/out zooming of a particular area of a still picture or movie. Additional features include DiscScan, TrackScan, QuickScan, OnScreen-Display (OSD), Karaoke, Playback Control (PBC) for Video CD 2.0, and entertainment game software. System control and house-keeping functions (keypad and remote control) are also provided. The ES3880 can be implemented with the ES3883 Video CD Video Encoder, which integrates most of the analog discrete components required for a Video CD player. Figure 1 shows a typical Video CD system using the ES3880 and the companion ES3883 video encoder. When the ES3880 and ES3883 are used in the design, enhanced support for 3DSound and SurroundSound is realized, along with support for interactive games. The ES3880 is available in an industry-standard 100-pin Plastic Quad Flat Pack (PQFP) package. FEATURES * * * * * * * * * * * * * * * * * * * * * * * * * Programmable Multimedia Processor (PMP) architecture MPEG-1 audio/video decoder and system parser CD block decoder functions Video interlacing hardware Color Space Conversion (CSC) STC interpretation and video/audio Phase-lock Loop (PLL) Supports both 8- and 16-bit YUV output 256/384 frame sampling frequency for audio system clock Programmable master clock for external audio DAC Independent bit clock for audio transmit and receive SmartScale video scaling supports X- and Y-axis interpolation SmartZoom supports 4X picture enlargement and reduction SmartStream supports audio and video bit stream error concealment SmartVocal: cancels the vocal on an audio-CD Karaoke function Video Fader for fading video image (in and out) On-screen-Display (OSD) Playback Control (PBC) for Video CD 2.0 Trick mode functions (Repeat, Goto, Set A-B, etc.) DiscScan, TrackScan, and QuickScan Video CD 1.1 and 2.0, and Audio CD compatible Power management 3.6 V power supply with 5 V tolerant I/O's 100-pin PQFP Can be used with either serial or parallel interfaces ES3883 Video CD Companion Chip Keypad Panel Interface Audio CD-ROM DRAM 256K X 16 ROM ES3880 Video CD MPEG Processor Echo Audio DAC NTSC/PAL Encoder Interrupt DSC I/O Expansion Video Microphone Speakers Television IR Figure 1 ES3880 System Block Diagram ESS Technology, Inc. SAM0191-052901 1 ES3880 PRODUCT BRIEF ES3880 PINOUT ES3880 PINOUT Figure 2 shows the ES3880 device pinout. LCS0# LCS1# LCS3# LWR# AUX7 AUX5 AUX6 LOE# LA10 LA11 VPP LA12 LA13 LA14 LA15 LA16 LA17 ACLK AOUT/SEL_PLL0 ATCLK ATFS/SEL_PLL1 DA9/DOE# AIN ARCLK ARFS TDMCLK TDMDR TDMFS CAS# VSS 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VDD VSS LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0 LA9 LA8 LA7 LA6 LA5 LA4 LA3 LA2 LA1 LA0 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 VSS AUX4 AUX3 AUX2 AUX1 AUX0 PCLK PCLK2X CPUCLK HSYNC VSYNC YUV7 YUV6 YUV5 YUV4 YUV3 YUV2 YUV1 YUV0 VDD ES3880 100-pin PQFP 1 VDD 23 RAS# DWE# 4 DA0 567 DA1 DA2 DA3 31 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 DBUS11 DBUS12 DBUS10 DBUS14 DBUS15 RESET# DBUS13 DBUS0 DBUS1 DBUS2 DBUS3 DBUS4 DBUS5 DBUS6 DBUS7 DBUS8 DBUS9 DA4 DA5 DA6 DA7 DA8 VSS Figure 2 ES3880 Device Pinout 2 SAM0191-052901 ESS Technology, Inc. ES3880 PRODUCT BRIEF PIN DESCRIPTION PIN DESCRIPTION Table 1 lists the pin descriptions for the ES3880. Table 1 ES3880 Pin Descriptions List Name VDD RAS# DWE# DA[8:0] DBUS[15:0] RESET# VSS YUV[7:0] VSYNC HSYNC CPUCLK PCLK2X PCLK AUX[7:0] LD[7:0] LWR# LOE# LCS[3,1,0]# LA[17:0] VPP ACLK AOUT Number 1, 31, 51 2 3 12:4 28:13 29 30, 50, 80, 100 39:32 40 41 42 43 44 54:52, 49:45 62:55 63 64 65, 66, 67 87:82, 79:68 81 88 I/O I O O O I/O I I O I/O I/O I I/O I/O I/O I/O O O O O I I/O O I 3.3V power supply. Row address strobe. DRAM write enable. DRAM multiplexed row and column address bus. DRAM data bus. System reset. Ground. YUV[7:0] 8-bit video data bus. Vertical sync. Horizontal sync. RISC and system clock input. CPUCLK is used only if SEL_PLL[1:0] = 00 to bypass PLL. Doubled 54 MHz pixel clock. 27 MHz pixel clock. Auxiliary control pins 7:0. AUX0 and AUX1 are open collectors. RISC interface data bus. RISC interface write enable. RISC interface output enable. RISC interface chip select. RISC interface address bus. 5.0V power supply. Master clock for external audio DAC. Audio interface serial data output when selected. System and DSCK output clock frequency selection at reset time. The matrix below lists the available clock frequencies and their respective PLL bit settings. SEL_PLL1 0 0 1 1 SEL_PLL0 0 1 0 1 DCLK Bypass PLL (input mode) 54 MHz (output mode) Default 67.5 MHz (output mode) 81.0 MHz (output mode) Definition SEL_PLL0 89 ATCLK ATFS SEL_PLL1 DA9 DOE# AIN ARCLK ARFS TDMCLK 90 91 92 93 94 95 96 I/O O I O O I I I I Audio transmit bit clock. Audio transmit frame sync. Refer to the description and matrix for SEL_PLL0 pin 89. DRAM multiplexed row and column address line 9. DRAM output enable. Audio serial data input. Audio receive bit clock. Audio receive frame sync. TDM serial clock. ESS Technology, Inc. SAM0191-052901 3 ES3880 PRODUCT BRIEF BLOCK DIAGRAM Table 1 ES3880 Pin Descriptions List (Continued) Name TDMDR TDMFS CAS# Number 97 98 99 I/O I I O TDM serial data receive. TDM frame sync. DRAM column address strobe. Definition BLOCK DIAGRAM Figure 3 provides a functional block diagram of the ES3880. Processor Interface LA[17:0] LD[7:0] LCS3#, LCS#[1:0] LWR# LOE# DRAM Interface RISC Processor Huffman Decoder 2Kx32 ROM 512x32 SRAM RAS# DA[9:0] DBUS[15:0] DOE# DWE# CAS# DRAM Serial Audio Interface ACLK ATCLK AIN AOUT ARFS ATFS ARCLK AUX[7:0] AUX Serial Audio Interface 64x32 ROM 32x32 SRAM Registers MPEG Processor Video Output On Screen Display YUV[7:0] PCLK2X PCLK VSYNC HSYNC Screen Display TDM Interface SEL_PLL[1:0] TDMCLK TDMDR TDMFS TDM Interface DRAM DMA Controller CPUCLK RESET# Misc. Figure 3 ES3880 Functional Block Diagram ORDERING INFORMATION Part Number ES3880 Description Video CD MPEG Processor Package 100-pin PQFP No part of this publication may be reproduced, stored in a retrieval system, transmitted, or translated in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without the prior written permission of ESS Technology, Inc. ESS Technology, Inc. makes no representations or warranties regarding the content of this document. All specifications are subject to change without prior notice. ESS Technology, Inc. assumes no responsibility for any errors contained herein. (P) U.S. Patent 4,384,169 and others, other patents pending. SmartScaleTM, SmartStreamTM, and VideoDriveTM are trademarks of ESS Technology, Inc. MPEG is the Moving Picture Experts Group of the ISO/ IEC. References to MPEG2 in this document refer to the ISO/IEC 13818-1. All other trademarks are owned by their respective holders and are used for identification purposes only. 4 (c) 2000 ESS Technology, Inc. All rights reserved. SAM0191-052901 |
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