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LT1122 Fast Settling, JFET Input Operational Amplifier
FEATURES
s
DESCRIPTIO
340ns Typ 540ns Max 60V/s Min 14MHz 1.2 MHz 60 600V Max 75pA Max 600pA Max 40pA Max 150pA Max
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100% Tested Settling Time to 1mV at Sum Node, 10V Step Tested with Fixed Feedback Capacitor Slew Rate Gain Bandwidth Product Power Bandwidth (20Vp-p) Unity Gain Stable; Phase Margin Input Offset Voltage Input Bias Current 25C 70C Input Offset Current 25C 70C Low Distortion
The LT1122 JFET input operational amplifier combines high speed and precision performance. A unique poly-gate JFET process minimizes gate series resistance and gate-to-drain capacitance, facilitating wide bandwidth performance, without degrading JFET transistor matching. It slews at 80V/s and settles in 340ns. The LT1122 is internally compensated to be unity gain stable, yet it has a bandwidth of 14MHz at a supply current of only 7mA. Its speed makes the LT1122 an ideal choice for fast settling 12-bit data conversion and acquisition systems. The LT1122 offset voltage of 120V, and voltage gain of 500,000 also support the 12-bit accurate applications. The input bias current of 10pA and offset current of 4pA combined with its speed allow the LT1122 to be used in such applications as high speed sample and hold amplifiers, peak detectors, and integrators.
APPLICATI
s s s s s s s s
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Fast 12-Bit D/A Output Amplifiers High Speed Buffers Fast Sample and Hold Amplifiers High Speed Integrators Voltage to Frequency Converters Active Filters Log Amplifiers Peak Detectors
TYPICAL APPLICATI
12-Bit Voltage Output D/A Converter
Large-Signal Response
+
Cf 2 0mA TO 2mA OR 4mA 3 +
- LT1122 6 VOUT 0V TO 10V
5V/DIV
12-BIT CURRENT OUTPUT D/A CONVERTER C f = 5pF TO 17pF (DEPENDING ON D/A CONVERTER USED)
LT1122*TA01
200ns/DIV AV = -1
1122 TA07
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UO
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1
LT1122 ABSOLUTE AXI U RATI GS
Operating Temperature Range LT1122AM/BM/CM/DM .................... - 55C to 125C LT1122AC/BC/CC/DC/CS/DS .............. - 40C to 85C Storage Temperature Range All Devices ....................................... - 65C to 150C Supply Voltage .................................................... 20V Differential Input Voltage ...................................... 40V Input Voltage ........................................................ 20V Output Short Circuit Duration .......................... Indefinite Lead Temperature (Soldering, 10 sec.)................. 300C
PACKAGE/ORDER I FOR ATIO
TOP VIEW VOS TRIM -IN +IN V- 1 2 3 4 LT1122 8 7 6 5 SPEED BOOST/ OVERCOMP V+ OUT VOS TRIM
N8 PACKAGE J8 PACKAGE 8-LEAD PLASTIC DIP 8-LEAD HERMETIC DIP
TJMAX = 150C, JA = 130C/W (N8) TJMAX = 175C, JA = 100C/W (J8)
ORDER PART NUMBER LT1122AMJ8 LT1122CCJ8 LT1122BMJ8 LT1122DCJ8 LT1122CMJ8 LT1122ACN8 LT1122DMJ8 LT1122BCN8 LT1122ACJ8 LT1122CCN8 LT1122BCJ8 LT1122DCN8
Consult factory for Industrial grade parts.
ELECTRICAL CHARACTERISTICS
SYMBOL
VOS IOS IB
VS = 15V, TA = 25C, VCM = 0V unless otherwise noted. (Note 1)
LT1122AM/BM LT1122AC/BC MIN TYP MAX
120 4 10 1012 1012 1011 4 60 80 50 600 40 75
PARAMETER
Input Offset Voltage Input Offset Current Input Bias Current Input Resistance Differential Common Mode Input Capacitance
CONDITIONS
VCM = - 10V to + 8V VCM = + 8V to + 11V AV = - 1 + 10V to 0V, - 10V to 0V 100% Tested: A and C Grades to 1mV at Sum Node B and D Grades to 1mV at Sum Node All Grades to 0.5mV at Sum Node VOUT = 20Vp-p VOUT = 10V, RL = 2k VOUT = 10V, RL = 600 VCM = 10V (Note 3) VS = 10V to 18V 0.1Hz to 10Hz fO = 100Hz fO = 10kHz fO = 100Hz, fO = 10kHz 180 130 83 86
SR
Slew Rate Settling Time (Note 2)
GBW AVOL CMRR PSRR
Gain Bandwidth Product Power Bandwidth Large Signal Voltage Gain Common Mode Rejection Ratio Input Voltage Range Power Supply Rejection Ratio Input Noise Voltage Input Noise Voltage Density Input Noise Current Density
2
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TOP VIEW VOS TRIM -IN +IN V- 1 2 3 4 S8 PACKAGE 8-LEAD PLASTIC SOIC LT1122 8 7 6 5 SPEED BOOST/ OVERCOMP V+ OUT VOS TRIM
ORDER PART NUMBER LT1122CS8 LT1122DS8 PART MARKING 1122C 1122D
TJMAX = 150C, JA = 190C/W
LT1122CM/DM LT1122CC/DC LT1122CS/DS MIN TYP MAX
130 5 12 1012 1012 1011 4 75 900 50 100
UNITS
V pA pA pF V/s
340 350 450 14 1.2 500 250 99 103 3.0 25 14 2
540
350 360 470 13 1.1 150 110 80 10.5 82 450 220 98 11 101 3.3 27 15 2
590
ns ns ns MHz MHz V/mV V/mV dB V dB VP-P nV/Hz nV/Hz fA/Hz
10.5 11
LT1122
ELECTRICAL CHARACTERISTICS
SYMBOL
VOUT IS
VS = 15V, TA = 25C, VCM = 0V unless otherwise noted.
LT1122AM/BM LT1122AC/BC MIN TYP MAX
12 12.5 11.5 12 7.5 10 5 10 4 10 5 4
PARAMETER
Output Voltage Swing Supply Current Minimum Supply voltage Offset Adjustment Range
CONDITIONS
RL = 2k RL = 600 (Note 4) RPOT 10k, Wiper to V+
LT1122CM/DM LT1122CC/DC LT1122CS/DS MIN TYP MAX
12 11.5 12.5 12 7.8 11
UNITS
V V mA V mV
VS = 15V, VCM = 0V, 0C TA 70C, unless otherwise noted. (Note 1)
SYMBOL
VOS
PARAMETER
Input Offset Voltage Average Temperature Coefficient of Input Offset Voltage
CONDITIONS
LT1122AC/BC MIN TYP MAX
LT1122CC/DC LT1122CS/DS MIN TYP MAX
400 6 15 90 100 78 80 10 11.5 40 340 96 99 10.8 12.4 65 2000 25 200 800
UNITS
V V/C pA pA V/mV dB dB V V V/s
*
VOUT = 10V, RL 2k VCM = 10V VS = 10V to 17V RL = 2k AV = - 1
*
350 5 12 80 120 82 84 10 50 380 98 101 10.8 70
1400 18 150 600
IOS IB AVOL CMRR PSRR VOUT SR
Input Offset Current Input Bias Current Large Signal Voltage Gain Common Mode Rejection Ratio Power Supply Rejection Ratio Input Voltage Range Output Voltage Swing Slew Rate
* * * * * * * *
11.5 12.4
VS = 15V, VCM = 0V, - 55C TA 125C, unless otherwise noted. (Note 1)
SYMBOL
VOS
PARAMETER
Input Offset Voltage Average Temperature Coefficient of Input Offset Voltage
CONDITIONS
* * * * * * * * * *
LT1122AM/BM MIN TYP MAX
650 6 0.5 6 70 80 83 10 45 230 97 100 10.5 60 2400 18 6 25
LT1122CM/DM MIN TYP MAX
800 7 0.6 7 60 76 78 10 35 200 94 98 10.5 55 3400 25 9 35
UNITS
V V/C nA nA V/mV dB dB V V V/s
IOS IB AVOL CMRR PSRR VOUT SR
Input Offset Current Input Bias Current Large Signal Voltage Gain Common Mode Rejection Ratio Power Supply Rejection Ratio Input Voltage Range Output Voltage Swing Slew Rate RL = 2k AV = - 1 VOUT = 10V, RL 2k VCM = 10V VS = 10V to 17V
11.3 12.1
11.3 12.1
The * denotes the specifications which apply over the full operating temperature range. Note 1: The LT1122 is measured in an automated tester in less than one second after application of power. Depending on the package used, power dissipation, heat sinking, and air flow conditions, the fully warmed up chip temperature can be 10C to 50C higher than the ambient temperature. Note 2: Settling time is 100% tested for A and C grades using the settling time test circuit shown. This test is not included in quality assurance sample testing.
Note 3: Input voltage range functionality is assured by testing offset voltage at the input voltage range limits to a maximum of 4mV (A, B grades), to 5.7mV (C, D grades). Note 4: Minimum supply voltage is tested by measuring offset voltage to 7mV maximum at 5V supplies. Note 5: The LT1122 is not tested and not quality-assurance-sampled at - 40C and at 85C. These specifications are guaranteed by design, correlation and/or inference from - 55C, 0C, 25C, 70C and/or 125C tests.
3
LT1122
VS = 15V, VCM = 0V, - 40C TA 85C, unless otherwise noted. (Note 5)
SYMBOL
VOS
ELECTRICAL CHARACTERISTICS
PARAMETER
Input Offset Voltage Average Temperature Coefficient of Input Offset Voltage
CONDITIONS
* * * * * * * * * *
LT1122AC/BC MIN TYP MAX
450 6 30 230 95 80 83 10 45 340 98 100 10.6 65 1900 20 600 2000
LT1122CC/DC LT1122CS/DS MIN TYP MAX
500 7 40 260 80 76 78 10 11.3 35 300 96 98 10.6 12.2 60 2700 28 900 2700
UNITS
V V/C pA pA V/mV dB dB V V V/s
IOS IB AVOL CMRR PSRR VOUT SR
Input Offset Current Input Bias Current Large Signal Voltage Gain Common Mode Rejection Ratio Power Supply Rejection Ratio Input Voltage Range Output Voltage Swing Slew Rate RL = 2k AV = - 1 VOUT = 10V, RL 2k VCM = 10V VS = 10V to 17V
11.3 12.2
Settling Time Test Fixture
DEVICE UNDER TEST 5pF
+10V (REGULATED) 51
+15V 7 1 4 HA5002 2 5 -15V 8 51 2k 1% 2
2k 1% +15V 7 - LT1122 3 + 4 -15V 6
4 74LS00 GROUND ALL OTHER INPUTS 5
6
1
16
2
15 V IN (MEASURE INPUT PULSE HERE) 5.1k* 1%
3
14
5.1k 1%
TTL IN
1 2
4 3 5 LTC201A
13
12
6
11
7
10
8
9 +15V 7 + 3 51 1 8 2 - 2 -15V 79 1N5712 5 HA5002 4 51 SUMMING NODE OUTPUT
-10V (REGULATED) +15V 0.1F
NO CONNECTION ON PINS 10, 11, 12, 14, AND 15 1k 6
+15V 7 LT1223 4 1.5k -15V
+
1F TANT
SETTLING TIME OUTPUT (20 TIMES SUM NODE OUTPUT) 1N5712
TYPICAL SUPPLY BYPASSING FOR EACH AMP/BUFFER -15V 0.1F 1F TANT
+
*THIS RESISTOR CAN BE ADJUSTED TO NULL OUT ALL OFFSETS AT THE SETTLING TIME OUTPUT. THE AUTOMATED TESTER USES A SEPARATE AUTOZERO CIRCUIT.
LT1122*TA02
4
LT1122
TYPICAL PERFOR A CE CHARACTERISTICS
Settling Time (Input From -10V to 0V)
1mV/DIV AT SUM NODE
100ns/DIV
1122 G01
1mV/DIV AT SUM NODE
100ns/DIV
1122 G02
1mV/DIV AT SUM NODE
Settling Time (Input From 0V to -10V)
PEAK TO PEAK OUTPUT SWING (V)
1mV/DIV AT SUM NODE
5V/DIV
100ns/DIV
1122 G04
Voltage Gain vs Frequency
120 100 80 VS = 15V TA = 25C
20
100 120
PHASE SHIFT (DEGREES)
COMMON-MODE REJECTION RATIO (dB)
GAIN (dB)
GAIN (dB)
60 40 20 0 -20 -40 1 10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
LT1122*TPC02
UW
Settling Time (Input From +10V to 0V)
Settling Time (Input From 0V to +10V)
100ns/DIV
1122 G03
Large Signal Response
30 25 20 15 10 5
Undistorted Output Swing vs Frequency
VS = 15V TA = 25C
200ns/DIV AV = +1
1122 G05
0 100k
1M
10M
100M
FREQUENCY (Hz)
LT1122*TPC01
Gain, Phase vs Frequency
80
120 100 80 60 40 20
Common Mode Rejection vs Frequency
VS = 15V TA = 25C
10
140 160
0 VS = 15V TA = 25C C L = 15pF
180 200
-10 1M 10M FREQUENCY (Hz)
LT1122*TPC03
100M
0 100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
LT1122*TPC04
5
LT1122
TYPICAL PERFOR A CE CHARACTERISTICS
Distribution of Input Offset Voltage
800 3370 UNITS TESTED IN ALL PACKAGES 600 VS = 15V TA = 25C (NOT WARMED UP)
INPUT BIAS AND OFFSET CURRENTS (pA)
30K 10K 3K 1K 300 100 30 10 3 1 0 25 50
VS = 15V VCM = 0V BIAS CURRENT
INPUT BIAS AND OFFSET CURRENT (pA)
NUMBER OF UNITS
400
200
0 -900
-500
-100 100
INPUT OFFSET VOLTAGE (V)
LT1122*TPC05
Warm-up Drift
250
N PACKAGE 150 J PACKAGE 100
100
50 IN STILL AIR (SO PACKAGE SOLDERED ONTO BOARD) 1 0 1 2 3 TIME AFTER POWER ON (MINUTES)
LT1122*TPC08
10 1 3 10 30 100 300 1k 3k 10k
0 2 4 6 8 10
NOISE VOLTAGE (1 V/DIV)
200
VOLTAGE NOISE DENSITY (nV/Hz)
CHANGE IN OFFSET VOLTAGE (V)
VS = 15V TA = 25C
SO PACKAGE
Total Harmonic Distortion + Noise vs Frequency Inverting Gain
TOTAL HARMONIC DISTORTION + NOISE (%)
TOTAL HARMONIC DISTORTION + NOISE (%)
T A = 25C VS = 15V Z L = 5k//15pF VO = 7V RMS 0.01 A V = -50
INTERMODULATION DISTORTION (IMD) (%)
0.1
0.001
A V = -10 A V = -1
0.0001 20
100
1k FREQUENCY (Hz)
6
UW
500
LT1122*TPC11
Input Bias and Offset Currents Over Temperature
100K
Bias and Offset Currents Over The Common-Mode Range
120 100 80 60 40 20 0 -15 BIAS CURRENT VS = 15V TA = 25C (NOT-WARMED UP)
OFFSET CURRENT
OFFSET CURRENT
900
75
100
125
-10
-5
0
5
10
15
CHIP TEMPERATURE (C)
LT1122*TPC06
COMMON-MODE INPUT VOLTAGE (V)
LT1122*TPC07
Noise Spectrum
1000 VS = 15V TA = 25C
0.1Hz to 10Hz Noise
FREQUENCY (Hz)
LT1122*TPC09
TIME (SECONDS)
LT1122*TPC10
Total Harmonic Distortion + Noise vs Frequency Non-Inverting Gain
0.1
0.1
Intermodulation Distortion (CCIF Method) vs Frequency LT1122 and LF156*
LF156 0.01 VS = 15V T A = 25C AV = -10 VO = 7V RMS Z L = 5k//15pF LT1122 0.0001 3k
0.01 A V = +50 AV = +10 0.001 A V = +1 T A = 25C VS = 15V Z L = 5k//15pF VO = 7V RMS 1k FREQUENCY (Hz)
LT1122*TPC12
0.001
10k 20k
0.0001 20
100
10k 20k
10k FREQUENCY (Hz)
20k
*SEE LT1115 DATA SHEET FOR DEFINITION OF CCIF TESTING LT1122*TPC13
LT1122
APPLICATI
S I FOR ATIO
Settling Time Measurements Settling time test circuits shown on some competitive devices' data sheets require: 1. A "flat top" pulse generator. Unfortunately, flat top pulse generators are not commercially available. 2. A variable feedback capacitor around the device under test. This capacitor varies over a four to one range. Presumably, as each op amp is measured for settling time, the capacitor is fine tuned to optimize settling time for that particular device. 3. A small inductor load to optimize settling. The LT1122's settling time is 100% tested in the test circuit shown. No "flat top" pulse generator is required. The test circuit can be readily constructed, using commercially available ICs. Of course, standard high frequency board construction techniques should be followed. All LT1122s are measured with a constant feedback capacitor. No fine tuning is required. Speed Boost/Overcompensation Terminal Pin 8 of the LT1122 can be used to change the input stage operating current of the device. Shorting pin 8 to the positive supply (Pin 7) increases slew rate and bandwidth by about 25%, but at the expense of a reduction in phase margin by approximately 18 degrees. Unity gain capacitive load handling decreases from typically 500pF to 100pF. Conversely, connecting a 15k resistor from pin 8 to ground pulls 1mA out of pin 8 (with V+ = 15V). This reduces slew rate and bandwidth by 25%. Phase margin and capacitive load handling improve; the latter typically increasing to 800pF. High Speed Operation As with most high speed amplifiers, care should be taken with supply decoupling, lead dress and component placement.
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of circuits as described herein will not infringe on existing patent rights.
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The power supply connections to the LT1122 must maintain a low impedance to ground over a bandwidth of 20MHz. This is especially important when driving a significant resistive or capacitive load, since all current delivered to the load comes from the power supplies. Multiple high quality bypass capacitors are recommended for each power supply line in any critical application. A 0.1F ceramic and a 1F electrolytic capacitor, as shown, placed as close as possible to the amplifier (with short lead lengths to power supply common) will assure adequate high frequency bypassing, in most applications.
V+
W
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+
2 7 - LT1122 3 + 4 6
1F
0.1F
V-
+
1F
0.1F
LT1122*TA03
When the feedback around the op amp is resistive (RF), a pole will be created with RF, the source resistance and capacitance (RS, CS), and the amplifier input capacitance (CIN 4pF). In low closed loop gain configurations and with RS and RF in the kilohm range, this pole can create excess phase shift and even oscillation. A small capacitor (CF) in parallel with RF eliminates this problem. With RS (CS + CIN) = RFCF, the effect of the feedback pole is completely removed.
CF
RF
- CIN RS CS +
LT1122*TA04
OUTPUT
7
LT1122
TYPICAL APPLICATIONS
Quartz Stabilized Oscillator With 9ppm Distortion
OUTPUT -15V 4.7k
4kHz J CUT
47k +
430pF 50k 560k
DISTORTION TRIM
- LT1122 + -15V 1/4 LTC201 Q1 2N3904 100k +15V 1M 560k
20k 1% VIN - LT1122 + +
OUTPUT DC = RMS VALUE OF INPUT BANDWIDTH WITH 10Vp-p INPUT = 2MHz
PACKAGE DESCRIPTION
Please see the 1994 Linear Databook Volume III for package descriptions.
8
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LT1004 2.5V OUTPUT AMPLITUDE 10 F TRIM +15V 4.7k
LT1122 LT1010
4.7k
5k
+
- LT1006 MOUNT IN CLOSE PROXIMITY +
-
470
2k
+15V GROUND CRYSTAL CASE = VACTEC VTL5C10 OR CLAIREX CLM410
= 1N4148
LT1122*TA05
Wide-Band, Filtered, Full Wave Rectifier
200k 1% 200k 1% 20k 1% 100k 1% 1k - LT1122 EOUT DC 1 F
50k
LT1122*TA06

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