 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Multiphase IMVP-IV Core Controller for Mobile CPUs ADP3205 FEATURES Pin Programmable 1-, 2-, or 3-Phase Operation Excellent Static and Dynamic Current Sharing Superior Load Transient Response when Used with ADOPTTM Optimal Positioning Technology Noise-Blanking for Speed and Stability Synchronous Rectification Control for Optimized Light Load Efficiency Soft DAC Output Voltage Transition for VID Change Cycle-by-Cycle Current Limiting Latched or Hiccup Current Overload Protection Masked Power Good during Output Voltage Transients Soft Start-Up without Power-On In-Rush Current Surge 2-Level Overvoltage and Reverse-Voltage Protection APPLICATIONS IMVP-IV CPU Core DC-to-DC Converters Programmable Output Power Supplies GENERAL DESCRIPTION The ADP3205 is a 1-, 2-, or 3-phase hysteretic peak current mode dc-to-dc buck converter controller dedicated to powering a mobile processor's core. The chip optimized low voltage design runs from the 3.3 V system supply. The chip contains a precision 6-bit DAC whose nominal output voltage is set by VID code. The ADP3205 features high speed operation to allow a minimized inductor size that results in the fastest possible change of current to the output. To further minimize the number of output capacitors, the converter features active voltage positioning enhanced with ADOPT optimal compensation to ensure a superior load transient response. The output signals interface with ADP3415 MOSFET drivers, which that are optimized for high speed and high efficiency. The ADP3205 is capable of providing synchronous rectification control to extend battery lifetime in light load conditions. The ADP3205 is specified over the extended commercial temperature range of 0C to 100C and is available in a 40-lead LFCSP package. FUNCTIONAL BLOCK DIAGRAM DRV3 DRVLSD3 39 38 DRV2 37 DRVLSD2 36 DRV1 DRVLSD1 35 34 ADP3205 TSYNC 40 PSI HYSSET CLIM/ZCS CMP HYS/CLIM CONTROL AND CS MUX/ PHASE CONTROL VDACREF CURRENT SENSE HYSTERESIS SET MUX AND VBG CLIM SET 33 CS3 CS2 CS1 CS+ CS- CORE CMP RAMP REG DRVCTRL DPSLP VREF BOOTSET DPRSET DPRSLP VID5 VID4 VID3 VID2 VID1 VID0 PWRGD CLKEN TPWRGD DPWRGD BOOT SS 19 SS/LATCH-OFF TIMER PRWGD DELAY VREF VBG PRWGD MASKING COREGD EOFSS ALARM LATCHEN CORE BELOW CMP DAC RES NETWORK CORE ABOVE CMP DACREFFB VREF VBG BOOT REF MUX DACREF DPSHIFT SET DPSHIFT DAC REF DIVIDER COREFB PWRGD LATCH ALARM CONTROL MASK DRVCTRL DVP CMP OVP LATCH VOV SD VCC 22 REV. 0 UVLO CMP BIAS ENABLER ALARM RST BAND GAP AND REF AMP VREF VBG RST RVP LATCH RVP CMP VRV CLAMP GND Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved. |
Price & Availability of ADP3205
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |