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| CXD2548R CD Digital Signal Processor with Built-in Digital Servo and DAC For the availability of this product, please contact the sales office. Description The CXD2548R is a digital signal processor LSI for CD players. This LSI incorporates a digital servo, digital filter, zero detection circuit, 1-bit DAC and analog low-pass filter on a single chip. Features * All digital signal processing during playback is performed with a single chip * Highly integrated mounting possible due to a builtin RAM Digital Signal Processor (DSP) Block * Playback mode which supports CAV (Constant Angular Velocity) * Frame jitter free * 0.5 x to 2.5 x continuous playback possible * Allows relative rotational velocity readout * Supports spindle external control * Wide capture range playback mode * Spindle rotational velocity following method * Supports normal-speed, double-speed playback * 16K RAM * EFM data demodulation * Enhanced EFM frame sync signal protection * SEC strategy-based error correction * Subcode demodulation and Sub Q data error detection * Digital spindle servo * 16-bit traverse counter * Asymmetry compensation circuit * CPU interface on serial bus * Error correction monitor signal, etc. output from a new CPU interface * Servo auto sequencer * Digital audio interface outputs * Digital level meter, peak meter Digital Servo (DSSP) Block * Microcomputer software-based flexible servo control * Offset cancel function for servo error signal * Auto gain control function for servo loop * E:F balance, focus bias adjustment functions * Surf jump function supporting micro two-axis Digital Filter, DAC and Analog Low-Pass Filter Blocks * Digital de-emphasis * Digital attenuation * Zero detection function * 8Fs oversampling digital filter * S/N: 100dB or more (master clock: 384Fs, typ.) * THD + N: 0.007% or more (master clock: 384Fs, typ.) * Rejection band attenuation: -60dB or more Applications CD players Structure Silicon gate CMOS IC Absolute Maximum Ratings -0.3 to +7.0 V * Supply voltage VDD * Input voltage VI -0.3 to +7.0 V (VSS - 0.3V to VDD + 0.3) * Output voltage VO -0.3 to +7.0 V * Storage temperature Tstg -40 to +125 C * Supply voltage difference VSS - AVSS -0.3 to +0.3 V VDD - AVDD -0.3 to +0.3 V Recommended Operating Conditions -3.4 to +5.25 V * Supply voltage VDDNote) * Operating temperature Topr -20 to +75 C Note) The VDD (Min.) for the CXD2548R varies according to the playback speed selection. VDD (min.) [V] Playback speed CD-DSP block DAC block DSSP block 2x 1x 1 x1 3.4V 3.4V 3.4V 4.5V 3.4V 3.4V 3.4V 3.4V 112 pin LQFP (Plastic) 1 When the internal operation of the CD-DSP side is set to double-speed mode and the crystal oscillation frequency is halved, normal-speed playback results. I/O Capacitance * Input pin * Output pin CI CO 12 (Max.) 12 (Max.) pF pF Note) Measurement conditions VDD = VI = 0V fM = 1MHz Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E96404-PS CXD2548R Block Diagram 4 104 103 3 2 1 CKOUT XTAO XTAI LMUT2(CH2) RMUT1(CH1) SYSM 4 104 103 3 2 1 90 92 88 94 Digital Filter + 1 bit DAC 98 99 100 109 108 107 AOUT1 AIN1 LOUT1 AOUT2 AIN2 LOUT2 98 99 100 109 108 107 PCMDI 90 92 88 94 91 89 87 85 26 25 BCK PCMD LRCK WDCK C2PO RFCK TES0 29 30 31 MNT0 MNT1 MNT3 29 30 31 Error Corrector 91 89 87 85 26 25 EMPHI LRCKI BCKI DOUT 33 33 15 D/A Interface Digital OUT Digital CLV 27 77 78 79 17 XRST XROF LOCK MDS MDP PWMI 15 27 77 78 79 17 16K RAM 8 9 7 SQCK SQSO EXCK SBSO SCOR XLON SPOA CLOK XLAT DATA 8 9 7 6 28 18 19 14 13 12 20 93 24 22 21 WFCK EMPH GFS XUGF GTOP 20 93 24 22 21 Sub Code Processor OSC Servo Auto SEquencer Clock Generator Digital PLL Servo Interface MIRR DFCT FOK SERVO DSP Asymmetry Corector A/D CONVERTER FOCUS SERVO TRACKING SERVO OpAmp A Sw 23 45 46 44 48 SLED SERVO PWM GENERATOR FOCUS PWM GENERATOR TRACKING PWM GENERATOR SLED PWM GENERATOR 59 57 56 55 54 58 60 61 CPU Interface EFM demodurator 6 28 18 19 14 13 12 43 42 41 39 40 83 VCTL V16M VCKI VPCO1 VPCO2 XTSL 43 42 41 39 40 83 10 SENS 10 84 16 50 52 53 51 XTAO 104 XTAI 103 FSTO 81 C4M 84 ACDT 16 RFAC 50 ASYI 52 ASYO 53 BIAS 51 36 35 76 37 DFCT MIRR COUT FOK 36 35 76 37 69 70 71 72 73 74 SFDR SRDR TFDR TRDR FFDR FRDR 69 70 71 72 73 74 XPCK FILO PCO FILI CLTV SE RFDC 23 45 46 44 48 59 57 56 55 54 58 60 61 -2- ADIO TE RFC VC CE FE CXD2548R Pin Configuration AVDD3 COUT SRDR FRDR AVSS3 TRDR LOCK FFDR TFDR TES2 XTSL TES3 MDP VSS2 ADIO C4M MDS RFC RFDC FSTO SFDR SSTP TEST FSTI VDD2 IGEN CE XROF 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 WDCK 85 VDD3 86 LRCK 87 LRCKI 88 PCMD 89 PCMDI 90 BCK 91 BCKI 92 EMPH 93 EMPHI 94 VSS3 95 AVSS1 96 AVDD1 97 AOUT1 98 AIN1 99 LOUT1 100 AVSS1 101 XVDD 102 XTAI 103 XTAO 104 XVSS 105 AVSS2 106 LOUT2 107 AIN2 108 AOUT2 109 AVDD2 110 AVSS2 111 VSS0 112 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 SE 55 FE 54 VC 53 ASYO 52 ASYI 51 BIAS 50 RFAC 49 AVDD4 48 CLTV 47 AVSS4 46 FILI 45 FILO 44 PCO 43 VCTL 42 V16M 41 VCKI 40 VPCO2 39 VPCO1 38 VDD1 37 FOK 36 DFCT 35 MIRR 34 ATSK 33 DOUT 32 VSS1 31 MNT3 30 MNT1 29 MNT0 PWMI XPCK SCLK VDD0 CKOUT LMUT2 SQSO RMUT1 WFCK SQCK SYSM -3- SCOR GTOP XUGF SENS ACDT XRST CLOK SPOA EXCK SBSO XLON RFCK C2PO XLAT DATA GFS TE CXD2548R Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Symbol SYSM RMUT1 LMUT2 CKOUT VDD0 SBSO EXCK SQCK SQSO SENS SCLK DATA XLAT CLOK XRST ACDT PWMI XLON SPOA WFCK GTOP XUGF XPCK GFS RFCK C2PO XROF SCOR MNT0 MNT1 MNT3 Vss1 DOUT ATSK MIRR DFCT O I O O 1, 0 1, 0 1, 0 O I I O O I I I I I O I O I O O O O O O O O O O O O 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 I O O O 1, 0 1, 0 1, 0 I/O Description System mute input. (high = on, low = off) R ch zero detection output. (high = on, low = off) L ch zero detection output. (high = on, low = off) DAC master clock frequency division output. Either the clock input from XTAI x 1, x 1/2 or x 1/4, or low output is selected and output. Digital power supply. Sub P to W serial output. SBSO readout clock input. SQSO readout clock input. Sub Q 80-bit and PCM peak and level data 16-bit output. SENS output to CPU. SENS serial data readout clock input. Serial data input from CPU. Latch input from CPU. Serial data is latched at the falling edge. Serial data transfer clock input from CPU. System reset. Reset when low. Normally not used. Leave open. Spindle motor external control input. Microcomputer extension interface (output). Microcomputer extension interface (input A). WFCK (Write Flame Clock) output. GTOP output. XUGF output. XPLCK output. GFS output. RFCK output. C2PO output. XRAOF output. Outputs a high signal when either subcode sync S0 or S1 is detected. MNT0 output. MNT1 output. MNT3 output. Digital GND. Digital Out output pin. Anti-shock pin. Mirror signal output. Defect signal output. -4- CXD2548R Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 Symbol FOK VDD1 VPCO1 VPCO2 VCKI V16M VCTL PCO FILO FILI AVss4 CLTV AVDD4 RFAC BIAS ASYI ASYO VC FE SE TE CE RFDC RFC ADIO AVss3 IGEN AVDD3 TES2 TES3 Vss2 TEST SFDR SRDR TFDR TRDR FFDR I O O O O O I I I I I I O I I I I I I I O I O O I O I O O I O I/O 1, 0 Focus OK signal output. Digital power supply. 1, Z, 0 1, Z, 0 Description Wide-band EFM PLL charge pump output. Wide-band EFM PLL VCO2 charge pump output. Wide-band EFM PLL VCO2 oscillation input. 1, 0 Wide-band EFM PLL VCO2 oscillation output. Wide-band EFM PLL VCO2 control input. 1, Z, 0 Analog Master PLL charge pump output. Master PLL filter output (slave = digital PLL). Master PLL filter input. Analog GND. Master VCO control voltage input. Analog power supply. EFM signal input. Asymmetry circuit constant current input. Asymmetry comparator voltage input. 1, 0 EFM full-swing output (low = VSS, high = VDD). Center voltage input. Focus error signal input. Sled error signal input. Tracking error signal input. Center error signal input. RF signal input. Input range: 2.15 to 5.0V. (when DVDD = AVDD = 5.0V) Connects an RF signal LPF time-constant capacitor. Operational amplifier output. Analog GND. Connects an operational amplifier current source reference resistor. Analog power supply. Test pin. Normally fixed to low. Test pin. Normally fixed to low. Digital GND. Test pin. Normally fixed to low. 1, 0 1, 0 1, 0 1, 0 1, 0 Sled drive output. Sled drive output. Tracking drive output. Tracking drive output. Focus drive output. -5- CXD2548R Pin No. 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 Symbol FRDR VDD2 COUT LOCK MDS MDP SSTP FSTO FSTI XTSL C4M WDCK VDD3 LRCK LRCKI PCMD PCMDI BCK BCKI EMPH EMPHI Vss3 AVss1 AVDD1 AOUT1 AIN1 LOUT1 AVss1 XVDD XTAI XTAO XVss AVss2 LOUT2 AIN2 AOUT2 O I O I O O I O O I O I O I O I O O O O I O I I O O O I/O 1, 0 Focus drive output. Digital power supply. 1, 0 1, 0 1, 0 1, 0 Track count signal output. Description GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low. Spindle motor servo control output. Spindle motor servo control output. Disc innermost track detection signal input. 1, 0 2/3-frequency division output for Pins 103 and 104. Digital servo reference clock input. Crystal selection input. Low when the crystal is 16.9344MHz; high when the crystal is 33.8688MHz. 1, 0 1, 0 4.2336MHz output. D/A interface. Word clock f = 2Fs Digital power supply. 1, 0 D/A interface. LR clock f = Fs LR clock input to DAC (48-bit slot). 1, 0 D/A interface. Serial data. (two's complement, MSB first) Audio data input to DAC (48-bit slot). 1, 0 D/A interface. Bit clock. Bit clock input to DAC (48-bit slot). 1, 0 Outputs a high signal when the playback disc has emphasis, and a low signal when there is no emphasis. DAC de-emphasis ON/OFF. (high = on, low = off) Digital GND. L ch, analog GND. L ch, analog power supply. Analog L ch, analog output. L ch, operational amplifier input. Analog L ch, LINE output. L ch, analog GND. Master clock analog power supply. Master clock 16.9344MHz crystal oscillation circuit input, or 33.8688MHz input. 1, 0 Master clock 16.9344MHz crystal oscillation circuit output. Master clock analog GND. R ch, analog GND. Analog R ch, LINE output. R ch, operational amplifier input. Analog R ch, analog output. -6- CXD2548R Pin No. 110 111 112 Symbol AVDD2 AVss2 Vss0 I/O R ch, analog power supply. R ch, analog GND. Digital GND. Description Notes) * PCMD is a MSB first, two's complement output. * GTOP is used to monitor the frame sync protection status. (High: sync protection window released.) * XUGF is the frame sync obtained from the EFM signal, and negative pulse. It is the signal before sync protection. * XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal transition point coincide. * The GFS signal goes high when the frame sync and the insertion timing match. * RFCK is derived from the crystal accuracy, and has a cycle of 136s (during normal speed). * C2PO represents the data error status. * XRAOF is generated when the 16K RAM exceeds the 4F jitter margin. -7- CXD2548R Electrical Characteristics 1. DC Characteristics Item Input voltage (1) High level input voltage Low level input voltage High level input voltage Input voltage (2) Low level input voltage (VDD = AVDD = 5.0V 5%, Vss = AVss = 0V, Topr = -20 to +75C) Conditions VIH (1) VIL (1) VIH (2) VIL (2) VIN(3) Schmitt input Analog input IOH = -4mA IOL = 4mA IOH = -2mA IOL = 4mA 0.8VDD 0.2VDD Vss VDD - 0.8 0 VDD - 0.8 0 VDD VDD 0.4 VDD 0.4 VDD 0.4 10 20 600 5 Min. 0.7VDD 0.3VDD Typ. Max. Unit Applicable pins V V V V V V V V V V V A A A A 1, 2 7 8 9 6 5 3, 7, 8, 10 4 2 1 Input voltage (3) Input voltage Output voltage (1) Output voltage (2) Output voltage (3) High level output voltage VOH(1) Low level output voltage VOL(1) High level output voltage VOH(2) Low level output voltage VOL(2) High level output voltage VOH(3) Low level output voltage VOL(3) ILI (1) ILI (2) ILI (3) ILO IOH = -0.28mA VDD - 0.5 IOL = 0.36mA VI = 0 to 5.5V VI = 1.5 to 3.5V VI = 0 to 5.0V VO = 0 to 5.5V 0 -10 -20 -40 -5 Input leak current (1) Input leak current (2) Input leak current (3) Tri-state pin output leak current Applicable pins 1 XTSL, DATA, XLAT, TEST, TES2, TES3, SSTP, ATSK, PWMI, SYSM, EMPHI, PCMDI 2 CLOK, XRST, EXCK, SQCK, VCKI, LRCKI, BCKI, SPOA, SCLK 3 CLTV, FILI, RFAC, VCTL, AIN1, AIN2, ASYI 4 MDP, PCO, PDO, VPCO1, VPCO2 5 ASYO, DOUT, FSTO, C4M, SBSO, SQSO, SCOR, EMPH, LOCK, WDCK, SENS, MDS, MNT0, MNT1, MNT3, WFCK, V16M, CKOUT, LMUT2, RMUT1, XLON, LRCK, PCMD, BCK, GTOP, XUGF, XPCK, GFS, RFCK, C2PO, XRAOF, MIRR, DFCT, COUT, FFDR, FRDR, TFDR, TRDR, SFDR, SRDR 6 FILO 7 TE, SE, FE, CE, VC 8 RFDC 9 SENS, MDS, MDP, PDO, PCO, VPCO1, VPCO2 10 RFC -8- CXD2548R 2. AC Characteristics (1) XTAI pin (a) When using self-excited oscillation (Topr = -20 to +75C, VDD = AVDD = 5.0V 5%) Item Oscillation frequency Symbol fMAX Min. 7 Typ. Max. 34 Unit MHz (b) When inputting pulses to XTAI pin (Topr = -20 to +75C, VDD = AVDD = 5.0V 5%) Item High level pulse width Low level pulse width Pulse cycle Input high level Input low level Rise time, fall time Symbol Min. 13 13 26 VDD - 1.0 0.8 10 Typ. Max. 500 500 1,000 Unit ns ns ns V V ns tWHX tWLX tCK VIHX VILX tR, tF tCX tWHX tWLX VIHX VIHX x 0.9 XTLI VDD/2 VIHX x 0.1 VILX tR tF (c) When inputting sine waves to XTLI pin via a capacitor (Topr = -20 to +75C, VDD = AVDD = 5.0V 5%) Item Input amplitude Symbol VI Min. 2.0 Typ. Max. Unit VDD + 0.3 Vp-p -9- CXD2548R (2) CLOK, DATA, XLAT, SQCK, and EXCK pins (VDD = AVDD = 5.0V 5%, VSS = AVSS = 0V, Topr = -20 to +75C) Item Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width EXCK, SQCK frequency Symbol fCK Min. Typ. Max. 0.65 750 300 300 300 750 0.651 7501 1/fCK tWCK CLK tWCK Unit MHz ns ns ns ns ns MHz ns tWCK tSU tH tD tWL fT EXCK, SQCK pulse width fWT DATA XLT tSU EXCK SQCK tWT 1/fT SUBQ SQCK tSU tH tWT tH tD tWL 1 In quasi double-speed playback mode, except when SQSO is Sub Q Read, the SQCL maximum operating frequency is 300kHz and its minimum pulse width is 1.5s. (3) BCKI, LRCKI and PCMDI pins (VDD = AVDD = 5.0V 5%, VSS = AVSS = 0V, Topr = -20 to +75C) Item BCK pulse width DATAL, R setup time DATAL, R hold time LRCK setup time Symbol Conditions Min. 94 18 18 18 tW(BCKI) tW(BCKI) VDD/2 tSU tH (PCMDI) (PCMDI) VDD/2 Typ. Max. Unit ns ns ns ns tW tSU tH tSU BCKI PCMDI tSU (LRCKI) LRCKI - 10 - CXD2548R (4) SCLK pin XLAT tDLS tSPW SCLK 1/fSCLK Serial Read Out Data (SENS) *** MSB *** LSB Item SCLK frequency SCLK pulse width Delay time Symbol fSCLK Min. Typ. Max. 1 Unit MHz ns s tSPW tDLS 500 15 (5) COUT, MIRR and DFCT pins Operating frequency (VDD = AVDD = 5.0V 5%, VSS = AVSS = 0V, Topr = -20 to +75C) Item COUT maximum operating frequency MIRR maximum operating frequency DFCT maximum operating frequency Symbol fCOUT fMIRR fDFCTH Min. 40 40 5 Typ. Max. Unit kHz kHz kHz Conditions 1 2 3 1 When using a high-speed traverse TZC 2 B A When the RF signal continuously satisfies the following conditions during the above traverse. * A = 0.6 to 1.3V * B = 25% or less A+B 3 During complete RF signal omission When settings related to DFCT signal generation are Typ. - 11 - CXD2548R 1-bit DAC and LPF Block Analog Characteristics Analog characteristics (VDD = AVDD = 5.0V, VSS = AVSS = 0V, Ta = 25C) Item Total harmonic distortion Signal-to-noise ratio Symbol THD Conditions 1kHz, 0dB data 1kHz, 0dB data (Using A-weighting filter) Crystal 384Fs 768Fs 384Fs 768Fs 96 96 Min. Typ. 0.0050 0.0045 100 100 Max. 0.0070 0.0065 dB Unit % S/N Fs = 44.1kHz in all cases. The total harmonic distortion and signal-to-noise ratio measurement circuits are shown below. 12k AOUT1 (2) 680p 12k AIN1 (2) 150p LOUT1 (2) 22 100k Audio Analyzer 12k SHIBASOKU (AM51A) LPF external circuit diagram 768Fs/384Fs Rch TEST DISC DATA RF CXD2548R Lch A Audio Analyzer B Block diagram of analog characteristics measurement - 12 - CXD2548R (VDD = AVDD = 5.0V, VSS = AVSS = 0V, Topr = -20 to +75C) Item Output voltage Load resistance Symbol VOUT RL 8 Min. Typ. 1.15 Max. Unit Vrms k Applicable pins 1 1 When a sine wave of 1kHz and 0dB is output. Applicable pins 1 LOUT1, LOUT2 - 13 - CXD2548R Contents [1] CPU Interface 1-1. CPU Interface Timing ...................................................................................................................... 15 1-2. CPU Interface Command Table . ..................................................................................................... 16 1-3. CPU Command Presets .................................................................................................................. 25 1-4. Description of SENS Signals ........................................................................................................... 30 [2] Description of CD Signal Processing and DAC System Commands and Subcode Interface 2-1. Description of Commands and Data Sets ....................................................................................... 31 2-2. Subcode Interface ........................................................................................................................... 50 [3] Description of Other CD Signal Processing and DAC System Functions 3-1. Description of DSP Operating Modes ............................................................................................. 55 (a) CLV-N Mode .................................................................................................................................... 55 (b) CLV-W Mode ................................................................................................................................... 55 (c) CAV-W Mode .................................................................................................................................. 55 3-2. Frame Sync Protection .................................................................................................................... 57 3-3. Error Correction ............................................................................................................................... 57 3-4. DA Interface .................................................................................................................................... 58 3-5. Digital Out ........................................................................................................................................ 60 3-6. Servo Auto Sequence ..................................................................................................................... 60 3-7. Asymmetry Compensation .............................................................................................................. 67 3-8. Channel Clock Regeneration by the Digital PLL Circuit .................................................................. 68 3-9. Digital CLV ...................................................................................................................................... 70 3-10. 1-bit DAC Block ............................................................................................................................... 71 3-11. LPF Block ........................................................................................................................................ 73 3-12. Setting the Playback Speed for the CD-DSP and 1-bit DAC Blocks ............................................... 74 [4] Description of Servo Signal Processing System Functions and Commands 4-1. General Description of the Servo Signal Processing System ......................................................... 75 4-2. Digital Servo Block Master Clock (MCK) ......................................................................................... 76 4-3. AVRG Measurement and Compensation ........................................................................................ 76 4-4. E:F Balance Adjustment Function ................................................................................................... 78 4-5. FCS Bias Adjustment Function ....................................................................................................... 78 4-6. AGCNTL Function ........................................................................................................................... 80 4-7. FCS Servo and FCS Search ........................................................................................................... 82 4-8. TRK and SLD Servo Control ........................................................................................................... 83 4-9. MIRR and DFCT Signal Generation ................................................................................................ 84 4-10. DFCT Countermeasure Circuit ........................................................................................................ 85 4-11. Anti-Shock Circuit ............................................................................................................................ 85 4-12. Brake Circuit .................................................................................................................................... 86 4-13. COUT Signal ................................................................................................................................... 87 4-14. Serial Readout Circuit ..................................................................................................................... 87 4-15. Writing the Coefficient RAM ............................................................................................................ 88 4-16. PWM Output .................................................................................................................................... 88 4-17. Servo Status Changes Produced by the LOCK Signal ................................................................... 90 4-18. Description of Commands and Data Sets ........................................................................................ 90 4-19. List of Servo Filter Coefficients ...................................................................................................... 102 4-20. FILTER Composition ..................................................................................................................... 104 4-21. TRACKING and FOCUS Frequency Response ............................................................................ 111 [5] Application Circuit 5-1. Application Circuit .......................................................................................................................... 112 Explanation of abbreviations AVRG: AGCNTL: FCS: TRK: SLD: DFCT: Average auto gain control Focus Tracking Sled Defect - 14 - CXD2548R [1] CPU Interface 1-1. CPU Interface Timing * CPU Interface This interface uses DATA, CLOK, and XLAT to set the modes. The interface timing chart is shown below. 750ns or more CLOK DATA (Example) D18 D19 D20 D21 D22 D23 750ns or more XLAT Registers Valid * The internal registers are initialized by a reset when XRST = 0. Note) Be sure to set SQCK to high when XLAT is low. - 15 - 1-2. CPU Interface Command Table Command Table ($0X to 1X) Data 2 Data 3 Data 4 D8 D7 D4 D0 D6 D5 D3 D2 D1 Data 5 D12 D11 D10 D9 D16 D15 D14 D13 Address Data 1 Register Command D23 to D20 D19 D18 D17 1 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FOCUS SERVO ON (FOCUS GAIN NORMAL) FOCUS SERVO ON (FOCUS GAIN DOWN) FOCUS SERVO OFF, 0V OUT 1 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 FOCUS CONTROL 0000 0 -- 0 0 -- 1 FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT FOCUS SEARCH VOLTAGE DOWN FOCUS SEARCH VOLTAGE UP ANTI SHOCK ON ANTI SHOCK OFF BRAKE ON BRAKE OFF TRACKING GAIN NORMAL TRACKING GAIN UP TRACKING GAIN UP FILTER SELECT 1 TRACKING GAIN UP FILTER SELECT 2 --: Don't care 0 -- 1 - 16 - -- -- -- -- -- -- 1 0 0 -- 1 1 0 -- 0 -- -- -- 1 -- -- 0 -- 1 TRACKING CONTROL 0001 -- -- 0 -- -- 1 -- -- -- -- -- -- CXD2548R Command Table ($2X to 3X) Data 2 Data 3 Data 4 Data 5 D4 D3 D2 D1 D0 D8 D6 D5 D7 D12 D11 D10 D9 D16 D13 D15 D14 Address Data 1 Register Command D23 to D20 D19 D18 D17 0 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 5 D4 D3 D2 D1 D0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 4 D8 D7 D6 D5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 3 D12 D11 D10 D9 TRACKING SERVO OFF TRACKING SERVO ON FORWARD TRACK JUMP REVERSE TRACK JUMP SLED SERVO OFF SLED SERVO ON 0 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 2 D15 D13 D14 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 1 0 1 1 0 -- 1 1 -- 2 TRACKING MODE 0010 -- -- 0 -- -- 0 -- -- 1 -- -- FORWARD SLED MOVE REVERSE SLED MOVE - 17 - D16 0 -- -- 1 Address Data 1 Register Command D23 to D20 D19 D18 D17 0 0 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SLED KICK LEVEL (1 x basic value) (Default) SLED KICK LEVEL (2 x basic value) SLED KICK LEVEL (3 x basic value) SLED KICK LEVEL (4 x basic value) --: Don't care 0 0 1 0 0 1 3 SELECT 0011 0 0 1 0 0 1 CXD2548R Command Table ($340X) Address 4 D10 D8 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K02) SLED LOW BOOST FILTER A-L KRAM DATA (K03) SLED LOW BOOST FILTER B-H KRAM DATA (K04) SLED LOW BOOST FILTER B-L KRAM DATA (K05) SLED OUTPUT GAIN KRAM DATA (K06) FOCUS INPUT GAIN KRAM DATA (K07) SLED AUTO GAIN KRAM DATA (K08) FOCUS HIGH CUT FILTER A KRAM DATA (K09) FOCUS HIGH CUT FILTER B KRAM DATA (K0A) FOCUS LOW BOOST FILTER A-H KRAM DATA (K0B) FOCUS LOW BOOST FILTER A-L KRAM DATA (K0C) FOCUS LOW BOOST FILTER B-H KRAM DATA (K0D) FOCUS LOW BOOST FILTER B-L KRAM DATA (K0E) FOCUS PHASE COMPENSATE FILTER A KRAM DATA (K0F) FOCUS DEFECT HOLD GAIN KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K01) SLED LOW BOOST FILTER A-H KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K00) SLED INPUT GAIN D5 D4 D1 D0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D9 D7 D6 D3 D2 Data 1 Data 2 Address 1 Address 2 Address 3 Register Command D23 to D20 D19 to D16 D15 to D12 D11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 - 18 - 3 SELECT 0011 0100 0000 CXD2548R Command Table ($341X) Address 4 D10 D8 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K13) FOCUS AUTO GAIN KRAM DATA (K14) HPTZC / AUTO GAIN HIGH PASS FILTER A KRAM DATA (K15) HPTZC / AUTO GAIN HIGH PASS FILTER B KRAM DATA (K16) ANTI SHOCK HIGH PASS FILTER A KRAM DATA (K17) HPTZC / AUTO GAIN LOW PASS FILTER B KRAM DATA (K18) FIX KRAM DATA (K19) TRACKING INPUT GAIN KRAM DATA (K1A) TRACKING HIGH CUT FILTER A KRAM DATA (K1B) TRACKING HIGH CUT FILTER B KRAM DATA (K1C) TRACKING LOW BOOST FILTER A-H KRAM DATA (K1D) TRACKING LOW BOOST FILTER A-L KRAM DATA (K1E) TRACKING LOW BOOST FILTER B-H KRAM DATA (K1F) TRACKING LOW BOOST FILTER B-L CXD2548R KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K12) ANTI SHOCK INPUT GAIN KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K11) FOCUS OUTPUT GAIN KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K10) FOCUS PHASE COMPENSATE FILTER B D4 D0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D9 D7 D6 D5 D3 D2 D1 Data 1 Data 2 Address 1 Address 2 Address 3 Register Command D23 to D20 D19 to D16 D15 to D12 D11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 - 19 - 3 SELECT 0011 0100 0001 Command Table ($342X) Address 4 D10 D9 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K23) TRACKING AUTO GAIN KRAM DATA (K24) FOCUS GAIN DOWN HIGH CUT FILTER A KRAM DATA (K25) FOCUS GAIN DOWN HIGH CUT FILTER B KRAM DATA (K26) FOCUS GAIN DOWN LOW BOOST FILTER A-H KRAM DATA (K27) FOCUS GAIN DOWN LOW BOOST FILTER A-L KRAM DATA (K28) FOCUS GAIN DOWN LOW BOOST FILTER B-H KRAM DATA (K29) FOCUS GAIN DOWN LOW BOOST FILTER B-L KRAM DATA (K2A) FOCUS GAIN DOWN PHASE COMPENSATE FILTER A KRAM DATA (K2B) FOCUS GAIN DOWN DEFECT HOLD GAIN KRAM DATA (K2C) FOCUS GAIN DOWN PHASE COMPENSATE FILTER B KRAM DATA (K2D) FOCUS GAIN DOWN OUTPUT GAIN KRAM DATA (K2E) NOT USED KRAM DATA (K2F) NOT USED 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K22) TRACKING OUTPUT GAIN 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K21) TRACKING PHASE COMPENSATE FILTER B 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K20) TRACKING PHASE COMPENSATE FILTER A D8 D5 D4 D2 D1 D0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D7 D6 D3 Data 1 Data 2 Address 1 Address 2 Address 3 Register Command D23 to D20 D19 to D16 D15 to D12 D11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 - 20 - 3 SELECT 0011 0100 0010 CXD2548R Command Table ($343X) Address 4 D10 D9 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K32) NOT USED KRAM DATA (K33) ANTI SHOCK HIGH PASS FILTER B-H KRAM DATA (K34) ANTI SHOCK HIGH PASS FILTER B-L KRAM DATA (K35) ANTI SHOCK FILTER COMPARATE GAIN KRAM DATA (K36) TRACKING GAIN UP2 HIGH CUT FILTER A KRAM DATA (K37) TRACKING GAIN UP2 HIGH CUT FILTER B KRAM DATA (K38) TRACKING GAIN UP2 LOW BOOST FILTER A-H KRAM DATA (K39) TRACKING GAIN UP2 LOW BOOST FILTER A-L KRAM DATA (K3A) TRACKING GAIN UP2 LOW BOOST FILTER B-H KRAM DATA (K3B) TRACKING GAIN UP2 LOW BOOST FILTER B-L KRAM DATA (K3C) TRACKING GAIN UP PHASE COMPENSATE FILTER A KRAM DATA (K3D) TRACKING GAIN UP PHASE COMPENSATE FILTER B KRAM DATA (K3E) TRACKING GAIN UP OUTPUT GAIN KRAM DATA (K3F) NOT USED CXD2548R 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K31) ANTI SHOCK LOW PASS FILTER B 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K30) FIX D8 D6 D5 D4 D2 D1 D0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D7 D3 Data 1 Data 2 Address 1 Address 2 Address 3 Register Command D23 to D20 D19 to D16 D15 to D12 D11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 - 21 - 3 SELECT 0011 0100 0011 Command Table ($344X) Address 4 D10 D9 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K43) TRACKING HOLD FILTER B-H KRAM DATA (K44) TRACKING HOLD FILTER B-L KRAM DATA (K45) TRACKING HOLD FILTER OUTPUT GAIN KRAM DATA (K46) NOT USED KRAM DATA (K47) NOT USED KRAM DATA (K48) FOCUS HOLD FILTER INPUT GAIN KRAM DATA (K49) FOCUS HOLD FILTER A-H KRAM DATA (K4A) FOCUS HOLD FILTER A-L KRAM DATA (K4B) FOCUS HOLD FILTER B-H KRAM DATA (K4C) FOCUS HOLD FILTER B-L KRAM DATA (K4D) FOCUS HOLD FILTER OUTPUT GAIN KRAM DATA (K4E) NOT USED KRAM DATA (K4F) NOT USED 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K42) TRACKING HOLD FILTER A-L 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K41) TRACKING HOLD FILTER A-H 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K40) TRACKING HOLD FILTER INPUT GAIN D8 D6 D5 D4 D2 D1 D0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D7 D3 Data 1 Data 2 Address 1 Address 2 Address 3 Register Command D23 to D20 D19 to D16 D15 to D12 D11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 - 22 - 3 SELECT 0011 0100 0100 CXD2548R Command Table ($34FX to 3FX) Address Data 1 D14 D12 D9 FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1 -- FOCUS BIAS LIMIT FOCUS BIAS DATA TRVSC DATA -- TV0 FB9 FB8 FB6 FB2 FB1 TV2 TV1 Data 4 D4 D3 D2 D1 D0 FOCUS SEARCH SPEED/ VOLTAGE/AUTO GAIN DTZC/TRACK JUMP VOLTAGE/AUTO GAIN FZSL/SLED MOVE/ Voltage/AUTO GAIN LEVEL/AUTO GAIN/ DFSW/ (Initialize) 0 0 0 0 0 0 SERIAL DATA READ MODE/SELECT TV6 Data 3 D8 FTZ FG6 FG5 FG4 FG3 FG2 FG1 FG0 D7 D5 D6 TV5 TV4 TV3 FB5 FB4 FB3 TV9 TV8 TV7 FB7 D8 D5 D4 D2 D1 D0 1 1 1 Data 2 D12 D9 FS3 TJ3 TJ2 TJ1 FS2 FS1 FS0 D11 D10 0 0 0 1 1 0 D11 D10 D7 D6 D3 1 1 1 1 1 1 Data 1 D16 1 0 1 0 1 0 1 Data 1 Data 2 D13 D12 -- -- -- -- -- -- D11 D10 -- -- D9 -- -- Data 2 D12 D11 D10 D9 D8 D7 D8 -- -- D7 -- -- D16 0 -- -- Data 1 D16 0 1 0 D15 D14 D13 -- -- 1 D15 D14 0 FBON FBSS FBUP FBV1 FBV0 0 DAC SD6 SD5 SD4 SD3 SD2 SD1 SD0 0 0 0 DTZC TJ5 TJ4 FT1 FT0 FS5 FS4 D15 D14 D13 D13 Data 2 Data 3 D16 0 0 0 1 1 1 D15 Register Command D23 to D20 D19 D18 D17 0 1 0 0011 0 1 0 0 1 0 Address D23 to D20 D19 D18 D17 0 1 0 0 1 1 TJ0 SFJP TG6 TG5 TG4 TG3 TG2 TG1 TG0 0 1 1 FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0 - 23 - Data 3 D6 -- -- D5 -- -- Data 3 D6 D5 D4 0 0 DRR2 DRR1 DRR0 0 ASFG 0 AGG4 XT4D XT2D D4 -- -- F1NM F1DM F3NM F3DM T1NM T1UM T3NM T3UM DFIS TLCD RFLP 0011 1 0 0 3 SELECT 1 0 0 1 0 1 TJD0 FPS1 FPS0 TPS1 TPS0 CEIT SJHD INBK MTI0 FOCUS BIAS 0 0 Data 4 D3 -- -- D2 -- -- D1 -- -- Data 4 D3 0 LPAS SRO1 D2 0 0 D1 D0 MIRI XT1D Filter AGHF COT2 Others --: Don't care D0 -- -- TZC for COUT SLCT HPTZC (Default) TZC for COUT SLCT DTZC 0 Operation for MIRR/ DFCT/FOK 1 0 1 SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 RINT Address D23 to D20 D19 D18 D17 1 1 0 0011 1 1 0 Address D23 to D20 D19 D18 D17 1 1 1 CXD2548R 0011 1 1 1 Command Table ($4X to EX) Data 1 Data 2 Data 3 Data 4 Data 5 D8 D6 -- -- -- -- -- D5 D4 -- -- D7 D3 D2 D1 -- D12 D10 -- -- D9 -- -- D11 D16 D14 -- -- D13 -- -- D15 D20 D17 -- -- -- D19 D18 D22 D21 Data 6 D0 -- Address Register name Command D27 D26 D25 D24 D23 4 Auto sequence 0 1 0 0 AS3 AS2 AS1 AS0 5 -- -- -- -- -- -- -- -- 0 -- -- -- -- -- -- -- 1 0 1 0.18ms 0.09ms 0.05ms 0.02ms -- -- -- -- -- Blind (A, E), Overflow (C) Brake (B) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.36ms 0.18ms 0.09ms 0.05ms -- -- -- -- 6 Kick (D) 0 1 1 0 11.6ms 5.8ms 2.9ms 1.45ms 7 128 16 1 -- 64 Auto sequence (N) track jump count 256 32 8 4 2 -- VCO DOUT DOUT WSEL SEL1 Mute ON/OFF 0 0 SOCT 0 0 VCO KSL3 KSL2 KSL1 KSL0 SEL2 1 0 0 MCSL CKOSL1 CKOSL0 ZDPL ZMUT -- -- DSPB ON/OFF 0 0 0 0 0 0 Mute ATT 0 0 0 OPSL EMPH SMUT -- -- 0 1 1 1 32768 16384 8192 4096 2048 1024 512 -- -- -- -- -- -- 8 Mode specification 1 0 0 0 CDROM -- -- -- -- -- -- 9 Function specification 1 0 0 1 0 -- -- -- -- -- -- -- -- - 24 - SL0 CPUSR -- -- -- -- 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TP Gain VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0 CLVS -- -- A Audio CTRL 1 0 1 0 0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 FMUT 0 0 0 B Serial bus CTRL 1 0 1 1 SL1 -- -- -- -- -- -- -- -- -- -- C Spindle servo coefficient setting 1 1 0 0 Gain Gain Gain Gain MDP1 MDP0 MDS1 MDS0 -- -- -- -- -- -- -- -- -- -- D CLV CTRL 1 1 0 1 DCLV TB PWM MD -- -- -- -- -- -- -- -- -- -- E CLV MODE 1 1 1 0 CM3 CM2 CM1 CM0 EPWM SPDC ICAP SFSL VC2C HIFC LPWR VPON Gain Gain FCSW CAV1 CAV0 0 -- -- -- -- -- -- -- -- --: Don't care CXD2548R 1-3. CPU Command Presets Command Preset Table ($0X to 34X) Data 2 Data 5 D4 D3 -- -- -- Data 5 D4 D3 -- -- D2 -- D0 -- Data 2 D4 D3 D2 D0 D0 KRAM DATA ($3400XX to $344fXX) --: Don't care D0 -- SLED KICK LEVEL (1 x basic value) (Default) -- -- -- -- -- -- -- -- -- D2 D1 D0 FOCUS SERVO OFF, 0V OUT TRACKING GAIN UP FILTER SELECT 1 TRACKING SERVO OFF SLED SERVO OFF -- -- -- D16 0 -- -- -- -- -- Data 4 D8 -- -- Data 1 D8 D7 D6 D5 -- -- D7 D6 D5 -- -- -- -- -- Data 3 D12 -- -- Address 3 D12 D11 D10 D9 -- -- D11 D10 D9 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 0 Data 2 D15 D13 -- -- -- Address 2 D16 0 0 D15 D13 D14 D14 -- -- -- -- -- -- D15 D13 D12 D10 D9 D8 D6 D5 D14 D11 D7 Data 3 Data 4 Address Data 1 Register Command D23 to D20 D19 D18 D17 0 FOCUS CONTROL 0000 0 0 0 1 TRACKING CONTROL 0001 0 0 0 2 TRACKING MODE 0010 0 0 0 Address D16 0 Data 1 Register Command D23 to D20 D19 D18 D17 0011 0 0 0 Address 1 3 SELECT - 25 - See "Coefficient ROM Preset Values Table". D23 to D20 D19 D18 D17 0011 0 1 0 CXD2548R Command Preset Table ($34FX to 3FX) Address 2 Data 1 Data 3 D4 D3 0 0 FOCUS BIAS LIMIT FOCUS BIAS DATA TRVSC DATA 0 0 0 0 Data 4 D4 D3 1 1 1 0 0 0 1 0 Data 3 D8 -- Data 2 D12 0 0 0 D11 0 0 D10 0 0 0 D9 0 0 D8 0 0 D7 0 0 -- D7 D9 -- D6 -- D5 -- Data 3 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D4 -- D3 -- 0 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 Data 4 D2 -- D1 -- Data 4 D2 0 0 D1 0 0 D0 0 0 Filter Others --: Don't care D0 -- TZC for COUT SLCT HPTZC (Default) -- 1 0 1 0 0 0 0 0 0 D2 D1 D0 FOCUS SEARCH SPEED/ VOLTAGE AUTO GAIN DTZC/TRACK JUMP VOLTAGE AUTO GAIN FZSL/SLED MOVE/ Voltage/AUTO GAIN LEVEL/AUTO GAIN/ DFSW/ (Initialize) 0 SERIAL DATA READ MODE/SELECT 0 FOCUS BIAS Operation for MIRR/ DFCT/FOK 0 0 0 1 0 0 0 0 0 0 D2 D1 D0 0 0 0 D11 D10 0 0 0 0 0 Data 3 D8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 1 D7 D6 D5 0 0 0 0 0 0 0 0 0 0 0 1 0 Data 2 D12 1 1 1 0 0 0 0 0 Data 2 D13 -- -- -- D12 D11 D10 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 D11 D10 D9 D9 D8 D6 D5 1 0 0 D7 Data 2 D16 D13 1 1 1 1 1 1 D12 0 0 0 Data 1 D16 D13 0 0 0 0 0 0 1 1 0 1 0 1 0 1 Data 1 D16 0 -- Data 1 D16 D13 0 0 1 0 0 0 D15 D14 -- D15 D14 1 1 0 0 0 0 0 0 0 1 0 0 0 1 D15 D14 1 1 1 1 1 1 D15 D14 Address 1 Register Command D23 to D20 D19 D18 D17 0 1 0 0011 0 1 0 0 1 0 Address D23 to D20 D19 D18 D17 0 1 0 0 1 1 0 1 1 - 26 - 0011 1 0 0 3 SELECT 1 0 0 1 0 1 1 0 1 Address D23 to D20 D19 D18 D17 0011 1 1 0 Address D23 to D20 D19 D18 D17 1 1 1 0011 CXD2548R 1 1 1 Command Preset Table ($4X to EX) Data 1 Data 2 Data 3 Data 4 Data 5 D8 D6 -- -- -- -- -- D5 D4 -- -- D7 D3 D2 D1 -- D12 D9 -- -- -- -- D11 D10 D16 D13 -- -- -- -- D15 D14 D20 0 -- -- -- D19 D18 D17 D22 0 0 D21 Data 6 D0 -- Address Register name 0 Command D27 D26 D25 D24 D23 4 Auto sequence 0 1 0 0 5 -- -- -- -- -- -- -- -- -- -- -- -- -- Blind (A, E), Overflow (C) Brake (B) 0 0 1 -- -- -- 1 0 1 -- -- -- -- -- -- -- -- -- -- -- -- 1 -- -- -- 1 -- 0 1 0 1 -- -- -- -- 6 Kick (D) 0 1 1 0 -- -- -- -- 7 1 0 0 0 0 -- 0 0 0 0 Auto sequence (N) track jump count 0 0 0 0 0 0 0 -- 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 -- -- 0 1 1 1 -- -- -- -- -- -- 8 Mode specification 0 0 0 0 0 -- 0 0 0 0 0 0 0 0 0 -- 1 0 0 0 -- -- -- -- -- -- 9 Function specification 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 -- -- -- -- -- -- -- -- - 27 - 0 1 -- -- -- -- -- 0 -- -- -- 0 -- -- 0 1 -- -- -- -- 0 -- -- -- 1 -- -- -- 0 0 0 0 0 0 1 1 1 0 0 0 -- -- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A Audio CTRL 1 0 1 0 0 0 0 0 0 0 0 0 0 B Serial bus CTRL 1 0 1 1 -- -- -- -- -- -- -- -- -- -- C Spindle servo coefficient setting 1 1 0 0 -- -- -- -- -- -- -- -- -- -- D CLV CTRL 1 1 0 1 -- -- -- -- -- -- -- -- -- -- E CLV MODE 1 1 1 0 0 0 -- -- -- -- -- -- -- -- --: Don't care CXD2548R CXD2548R - 28 - CXD2548R Fix indicates that normal preset values should be used. - 29 - CXD2548R 1-4. Description of SENS Signals SENS output Microcomputer serial register (latching not required) $0X $1X $2X $38 $38 $30 to 37, $3A to 3F $3900 $3901 $3902 $3903 $3904 $3908 $390C $391C $391D $391E $391F $3920 to $393F $3940 to $397F $4X $5X $6X $AX $EX $7X, 8X, 9X, BX, CX, DX, FX ASEQ = 1 FZC AS TZC AGOK1 XAVEBSY1 SSTP VC In Reg. SLD In Reg. TRK In Reg. FCS In Reg. TE Avrg Reg. FE Avrg Reg. VC Avrg Reg. TRVSC Reg. FB Reg. RFDC In Reg. RFDC Avrg Reg. Address 5-bit (M00 to 1F) data RAM data Address 6-bit (K00 to 3F) coefficient RAM data XBUSY FOK 0 GFS OV64 0 Output data length -- -- -- -- -- -- 8 bit 8 bit 8 bit 8 bit 9 bit 9 bit 9 bit 9 bit 9 bit 8 bit 8 bit 16 bit 8 bit -- -- -- -- -- -- 1 $38 outputs AGOK during AGT and AGF command settings, and XAVEBSY during AVRG measurement. SSTP is output in all other cases. Note) The SENS output can be read from the SQSO pin when SOCT = 0, SL1 = 1 and SL0 = 0. (See "$BX Commands".) Description of SENS Signals SENS output XBUSY FOK GFS OV64 Low while the auto sequencer is in operation, high when operation terminates. Outputs the same signal as the FOK pin. High for "focus OK". High when the regenerated frame sync is obtained with the correct timing. Low when the EFM signal is lengthened by 64 channel lock pulses or more after passing through the sync detection filter. - 30 - CXD2548R [2] Description of CD Signal Processing and DAC System Commands and Subcode Interface 2-1. Description of Commands and Data Sets $4X commands Command CANCEL FOCUS-ON 1 TRACK JUMP 10 TRACK JUMP 2 NTRACK JUMP N TRACK MOVE AS3 0 0 1 1 1 1 AS2 0 1 0 0 1 1 AS1 0 1 0 1 0 1 AS0 0 1 RXF RXF RXF RXF RXF = 0 FORWARD RXF = 1 REVERSE * When the Focus-on command ($47) is canceled, $02 is sent and the auto sequence is interrupted. * When the Track jump/Move commands ($48 to $4F) are canceled, $25 is sent and the auto sequence is interrupted. $5X commands Auto sequence timer setting Set timers: A, E, C, B Command Blind (A, E), Over flow (C) Brake (B) D23 0.18ms 0.36ms D22 0.09ms 0.18ms D21 0.05ms 0.09ms D20 0.02ms 0.05ms e.g.) D2 = D0 = 1, D3 = D1 = 0 (Initial Reset) A = E = C = 0.11ms B = 0.23ms $6X commands Auto sequence timer setting Set timer: D Command KICK (D) D23 11.6ms D22 5.8ms D21 2.9ms D20 1.45ms e.g.) D3 = 0, D2 = D1 = D0 = 1 (Initial Reset) D = 10.15ms $7X commands Auto sequence track jump/move count setting (N) Data 1 Command Data 2 Data 3 Data 4 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 29 28 27 26 25 24 23 22 21 20 Auto sequence track jump 215 214 213 212 211 210 count setting This command is used to set N when a 2N-track jump or N-track move is executed for auto sequence. * The maximum track count is 65,535, but note that with a 2N-track jump the maximum track jump count depends on the mechanical limitations of the optical system. * When the track jump count is from 0 to 15, the COUT signal is counted; when the count is 16 or over, the MIRR signal is counted. - 31 - CXD2548R $8X commands Command D23 Data 1 D22 D21 D20 D19 Data 2 D18 0 D17 SOCT D16 VCO SEL2 D15 KSL3 Data 3 D14 KSL2 D13 KSL1 D12 KSL0 DOUT DOUT VCO Mode CDROM WSEL Mute ON/OFF SEL1 specification See "$BX Commands". Data 4 D11 0 D10 0 D9 1 D8 0 Command bit CDROM = 1 CDROM = 0 C2PO timing See Timing Chart 1-1. See Timing Chart 1-1. Processing CDROM mode; average value interpolation and pre-value hold are not performed. Audio mode; average value interpolation and pre-value hold are performed. Command bit DOUT Mute = 1 DOUT Mute = 0 Processing Digital Out output is muted. (DA output is not muted.) If other mute conditions are not set, Digital Out is not muted. Command bit DOUT ON/OFF = 1 DOUT ON/OFF = 0 Processing Digital Out is output from the DOUT pin. Digital Out is not output from the DOUT pin. Command bit WSEL = 1 WSEL = 0 Sync protection window width 26 channel clock1 6 channel clock Application Anti-rolling is enhanced. Sync window protection is enhanced. 1 In normal-speed playback, channel clock = 4.3218MHz. - 32 - CXD2548R Command bit VCOSEL1 0 0 0 0 1 1 1 1 KSL3 0 0 1 1 0 0 1 1 KSL2 0 1 0 1 0 1 0 1 Processing Multiplier PLL VCO1 is set to normal speed, and the output is 1/1 frequency-divided. Multiplier PLL VCO1 is set to normal speed, and the output is 1/2 frequency-divided. Multiplier PLL VCO1 is set to normal speed, and the output is 1/4 frequency-divided. Multiplier PLL VCO1 is set to normal speed, and the output is 1/8 frequency-divided. Multiplier PLL VCO1 is set to high speed1, and the output is 1/1 frequency-divided. Multiplier PLL VCO1 is set to high speed1, and the output is 1/2 frequency-divided. Multiplier PLL VCO1 is set to high speed1, and the output is 1/4 frequency-divided. Multiplier PLL VCO1 is set to high speed1, and the output is 1/8 frequency-divided. 1 Approximately twice the normal speed Command bit VCOSEL2 0 0 0 0 1 1 1 1 KSL1 0 0 1 1 0 0 1 1 KSL0 0 1 0 1 0 1 0 1 Processing Wide-band PLL VCO2 is set to normal speed, and the output is 1/1 frequency-divided. Wide-band PLL VCO2 is set to normal speed, and the output is 1/2 frequency-divided. Wide-band PLL VCO2 is set to normal speed, and the output is 1/4 frequency-divided. Wide-band PLL VCO2 is set to normal speed, and the output is 1/8 frequency-divided. Wide-band PLL VCO2 is set to high speed2, and the output is 1/1 frequency-divided. Wide-band PLL VCO2 is set to high speed2, and the output is 1/2 frequency-divided. Wide-band PLL VCO2 is set to high speed2, and the output is 1/4 frequency-divided. Wide-band PLL VCO2 is set to high speed2, and the output is 1/8 frequency-divided. 2 Approximately twice the normal speed - 33 - Timing Chart 2-1 LRCK WDCK - 34 - Rch 16bit C2 Pointer Lch 16bit C2 Pointer C2 Pointer for lower 8bits C2 Pointer for upper 8bits Rch C2 Pointer Lch C2 Pointer CDROM = 0 If C2 Pointer = 1, data is NG C2PO CDROM = 1 C2 Pointer for lower 8bits C2PO C2 Pointer for upper 8bits CXD2548R CXD2548R $9X commands Command Function specification Data 1 D23 0 D22 DSPB ON/OFF D21 0 Data 3 and subsequent data are DF/DAC function settings. Data 2 D20 D19 to D16 D15 0 0000 0 Data 3 D14 D13 D12 D11 Data 4 D10 D9 -- D8 -- MCSL CKOSL1 CKOSL0 ZDPL ZMUT Command bit DSPB = 1 DSPB = 0 Processing Double-speed playback (CD-DSP block) Normal-speed playback (CD-DSP block) Command bit MCSL = 1 MCSL = 0 Processing DF/DAC block master clock selection. Crystal = 768Fs (33.8688MHz). DF/DAC block master clock selection. Crystal = 384Fs (16.9344MHz). Command bit CKOSL1 0 0 1 1 CKOSL0 0 1 0 1 Processing CKOUT pin output is the 1/1 frequency-divided crystal input. CKOUT pin output is the 1/2 frequency-divided crystal input. CKOUT pin output is the 1/4 frequency-divided crystal input. CKOUT pin output is fixed low. Command bit ZDPL = 1 ZDPL = 0 Processing Mute flag (LMUT2 and RMUT1 pins) polarity setting. Muted when high. Mute flag (LMUT2 and RMUT1 pins) polarity setting. Muted when low. Command bit ZMUT = 1 ZMUT = 0 Zero detection mute on. Zero detection mute off. Processing - 35 - CXD2548R $AX commands Command Audio CTRL Data 1 D23 0 D22 0 D21 Mute D20 ATT Data 2 and subsequent data are DF/DAC function settings. Data 2 D19 0 D18 0 D17 D16 D15 Data 3 D14 0 D13 AD9 D12 AD8 OPSL EMPH SMUT Data 4 D11 AD7 D10 AD6 D9 AD5 D8 AD4 D7 AD3 Data 5 D6 AD2 D5 AD1 D4 AD0 D3 FMUT Data 6 D2 0 D1 0 D0 0 Command bit Mute = 1 Mute = 0 Processing Mute on. Zero data is output from DSP. Mute off. Command bit ATT = 1 ATT = 0 DSP output -12dB Attenuation off Processing Command bit OPSL = 1 OPSL = 0 Processing Set to 1 when changing the FMUT setting. Set to 0 when not changing the FMUT setting. Command bit EMPH = 1 EMPH = 0 De-emphasis on. De-emphasis off. Processing If either the EMPHI pin or EMPH are high, de-emphasis is on. Command bit SMUT = 1 SMUT = 0 Soft mute on. Soft mute off. Processing If either the SYSM pin or SMUT are high, soft mute is on. - 36 - CXD2548R Command bit AD9 to 0 Attenuation data Processing The attenuation data is 10 bits, and is set as follows. Attenuation data 3FFh 3FEh 3FEh : 001h 000h Audio output 0dB -0.0085dB -0.017dB -60.198dB - Command bit FMUT = 1 FMUT = 0 Forced mute on. Forced mute off. Processing FMUT can be set when OPSL is high. - 37 - $BX commands SOCT SL1 0 0 SubQ Peak meter SENS D SubQ A B C 1 0 1 0 1 0 1 0 1 1 0 0 1 1 SL0 mode 0 0 0 0 1 1 1 1 Command Data 1 D3 D2 D1 D0 Serial bus CTRL SL1 SL0 CPUSR 0 The SQSO pin output is switched to the various signals by setting the SOCT command of $8X and the SL1 and SL0 commands of $BX. Set SQCK to high at the fall of XLAT. Modes other than Sub Q and peak meter are loaded to the register when set at the fall of XLAT. Sub Q is loaded to the register with each SCOR, and peak meter is loaded during peak detection. XLAT - 38 - PER5 PER6 PER7 C1F1 C1F2 0 C2F1 C2F2 0 FOK GFS LOCK VF3 VF4 VF5 VF6 VF7 ALOCK C1F1 C1F2 0 C2F1 C2F2 0 FOK GFS PER4 PER5 PER6 PER7 0 C1F1 C1F2 0 C2F1 C2F2 0 FOK GFS SCOR GFS GTOP EMPH FOK LOCK RFCK XRAOF C1F1 C1F2 C2F1 C2F2 L3 L4 L5 L6 L7 R0 R1 R2 R3 R4 R5 R6 R7 SQCK mode A PER0 PER1 PER2 PER3 PER4 EMPH ALOCK VF0 VF1 VF2 VF3 VF4 VF5 VF6 VF7 mode B VF0 VF1 VF2 LOCK EMPH mode C PER0 PER1 PER2 PER3 LOCK EMPH mode D SPOA 0 0 0 WFCK Peak meter L0 L1 L2 CXD2548R CXD2548R Signal PER0 to 7 FOX GFS LOCK EMPH ALOCK VF0 to 7 SPOA WFCK SCOR GTOP RFCK XRAOF L0 to L7, R0 to R7 Description RF jitter amount (used to adjust the focus bias). 8-bit binary data in PER0 = LSB, PER7 = MSB. Focus OK High when the frame sync and the insertion protection timing match. GFS is sampled at 460Hz; when GFS is high, a high signal is output. If GFS is low eight consecutive samples, a low signal is output. High when the playback disc has emphasis. GFS is sampled at 460Hz; when GFS is high eight consecutive samples, a high signal is output. If GFS is low eight consecutive samples, a low signal is output. Used during CAV-W mode. Disc rotational speed measurement results. (See Timing Chart 2-3.) VF0 = LSB, VF7 = MSB. SPOA pin input Write frame clock output High when either subcode sync S0 or S1 is detected. High when the sync protection window is open. Read frame clock output Low when the built-in 16K RAM exceeds the 4 frame jitter margin. Peak meter register output. Lch L0 to 7 and Rch R0 to 7 peak data. L0 and R0 are LSB. C1F1 0 1 1 C1F2 0 0 1 C1 correction status No Error Single Error Correction Irretrievable Error C2F1 0 1 1 C2F2 0 0 1 C2 correction status No Error Single Error Correction Irretrievable Error Command bit CPUSR = 1 CPUSR = 0 XLON pin is high. XLON pin is low. Processing - 39 - CXD2548R Peak Meter XLAT SQCK SQSO (Peak meter) L0 L1 L2 L3 L4 L5 L6 L7 R0 R1 R2 R3 R4 R5 R6 R7 Setting the SOCT command of $8X to 0 and the SL1 and SL0 commands of $BX to 0 and 1, respectively, results in peak detection mode. The SQSO output is connected to the peak register. The maximum PCM data values (absolute value, upper 8 bits) for Lch and Rch can be read from SQSO by inputting 16 clocks to SQCK. Peak detection is not performed during SQCK input, and the peak register does not change during readout. This SQCK input judgment uses a retriggerable monostable multivibrator with a time constant of 270s to 400s. The time during which SQCK input is high should be 270 s or less. Also, peak detection is restarted 270s to 400s after SQCK input. The peak detection register is reset with each readout (16 clocks input to SQCK). The maximum value during peak detection mode is detected and held in this status until the next readout. When switching to peak detection mode, readout should be performed one time initially to reset the peak detection register. Peak detection can also be performed for previous value hold and average value interpolation data. - 40 - CXD2548R $CX commands Command Servo coefficient setting CLV CTRL ($DX) D23 Gain MDP1 D22 Gain MDP0 D21 Gain MDS1 D20 Gain MDS0 Gain CLVS * CLV mode gain setting: GCLVS Gain MDS1 0 0 0 0 1 1 Gain MDS0 0 0 1 1 0 0 Gain CLVS 0 1 0 1 0 1 GCLVS -12dB -6dB -6dB 0dB 0dB +6dB * CLVP mode gain setting: GMDP, GMDS Gain MDP1 0 0 1 Gain MDP0 0 1 0 GMDP -6dB 0dB +6dB Gain MDS1 0 0 1 Gain MDS0 0 1 0 GMDS -6dB 0dB +6dB - 41 - CXD2548R $DX commands Command D23 CLV CTRL DCLV PWM MD Data 1 D22 TB D21 TP D20 Gain CLVS D19 VP7 Data 2 D18 VP6 D17 VP5 D16 VP4 D15 VP3 Data 3 D14 VP2 D13 VP1 D12 VP0 See "$CX Commands". Command bit DCLV PWM MD = 1 DCLV PWM MD = 0 Description Digital CLV PWM mode specified. Both MDS and MDP are used. CLV-W and CAV-W modes can not be used. Digital CLV PWM mode specified. Ternary MDP values are output. CLV-W and CAV-W modes can be used. Command bit TB = 0 TB = 1 TP = 0 TP = 1 Description Bottom hold at a cycle of RFCK/32 in CLVS mode. Bottom hold at a cycle of RFCK/16 in CLVS mode. Peak hold at a cycle of RFCK/4 in CLVS mode. Peak hold at a cycle of RFCK/2 in CLVS mode. The rotational velocity R of the spindle can be expressed with the following equation. Command bit VP0 to 7 = F0 (H) : VP0 to 7 = E0 (H) Description Playback at half (normal) speed to Playback at normal (double) speed R= 256 - n 32 R: Relative velocity at normal speed = 1 n: VP0 to 7 setting value Notes) 1) Values in parentheses are for when DSPB is 1. 2) Values when the crystal is 16.9344MHz and XTSL is low or when the crystal is 33.8688MHz and XTSL is high. 3) The VP0 to 7 setting values are valid in CAV-W mode. 2 R - Relative velocity [times] 1.5 P DS B= 1 1 DSP 0.5 B=0 F0 VP0 to 7 setting value [HEX] E0 Fig. 2-1. - 42 - CXD2548R $EX commands Command CLV mode Data 1 D23 CM3 D22 CM2 D21 CM1 D20 D19 Data 2 D18 D17 D16 D15 Data 3 D14 D13 D12 CM0 EPWM SPDC ICAP SFSL VC2C HIFC LPWR VPON Command bit CM3 0 1 1 CM2 0 0 0 CM1 0 0 1 CM0 0 0 0 Mode STOP KICK BRAKE Spindle stop mode.1 Description Spindle forward rotation mode.1 Spindle reverse rotation mode. Valid only when LPWR = 0 in any modes.1 Rough servo mode. When the RF-PLL circuit isn't locked, this mode is used to pull the disc rotations within the RFPLL capture range. PLL servo mode. Automatic CLVS/CLVP switching mode. Used for normal playback. 1 1 0 1 1 1 1 1 1 0 1 0 CLVS CLVP CLVA 1 See Timing Charts 1-6 to 1-12. Command bit EPWM SPDC 0 0 0 1 0 0 1 0 ICAP 0 0 1 1 SFSL 0 0 0 0 VC2C 0 1 0 0 HIFC 0 1 1 1 LPWR VPON 0 0 0 0 0 0 1 1 Mode CLV-N CLV-W CAV-W CAV-W Description Crystal reference CLV servo. Used for playback in CLV-W mode.2 Spindle control with VP0 to 7. Spindle control with the external PWM. 2 Figs. 3-1 and 3-2 show the control flow with the microcomputer software in CLV-W mode. - 43 - CXD2548R Command SPD mode Data 4 D11 D10 D9 D8 0 Gain Gain FCSW CAV1 CAV0 Gain CAV1 0 0 1 1 Gain CAV0 0 1 0 1 Gain 0dB -6dB -12dB -18dB * This sets the gain when controlling the spindle with the phase comparator in CAV-W mode. Command bit FCSW = 0 FCSW = 1 Processing The VPCO2 pin is not used and it is Hi-Z. The VPCO2 pin is used and the pin signal is the same as VPCO1. - 44 - CXD2548R Mode DCLV PWM MD LPWR Command KICK Timing chart 2-2 (a) 2-2 (b) 2-2 (c) 2-3 (a) 2-3 (b) 2-3 (c) 2-4 (a) 2-4 (b) 2-4 (c) 2-5 (a) 2-5 (b) 2-5 (c) 2-6 (a) 2-6 (b) 2-6 (c) 2-7 (a) 2-7 (b) 2-7 (c) 0 CLV-N 1 0 BRAKE STOP KICK 0 BRAKE STOP KICK 0 CLV-W 0 1 BRAKE STOP KICK BRAKE STOP KICK 0 CAV-W 0 1 BRAKE STOP KICK BRAKE STOP Mode CLV-N DCLV PWM MD 0 1 0 LPWR 0 0 0 1 0 Timing chart 2-8 2-9 2-10 2-11 2-12 (EPWM = 0) 2-13 (EPWM = 0) 2-14 (EPWM = 1) 2-15 (EPWM = 1) CLV-W CAV-W 0 1 0 1 Note) CLV-W and CAV-W modes support control only by the ternary output of the MDP pin. Therefore, set DCLV PWM MD to 0 in CLV-W and CAV-W modes. - 45 - CXD2548R Timing Chart 2-2 CLV-N mode DCLV PWM MD = LPWR = 0 KICK BRAKE STOP MDS Z MDS Z MDS Z MDP H Z Z MDP L MDP Z H MON MON H MON L (a) KICK (b) BRAKE (c) STOP Timing Chart 2-3 CLV-N mode DCLV PWM MD = 1, LPWR = 0 KICK H BRAKE STOP MDS MDS L MDS MDP H MDP L H MDP L L MON H MON H MON L (a) KICK (b) BRAKE (c) STOP Timing Chart 2-4 CLV-W mode (when following the spindle rotational velocity) DCLV PWM MD = LPWR = 0 KICK BRAKE STOP MDS Z MDS Z MDS Z MDP H Z Z MDP L MDP Z MON H MON H MON L (a) KICK (b) BRAKE (c) STOP - 46 - CXD2548R Timing Chart 2-5 CLV-W mode (when following the spindle rotational velocity) DCLV PWM MD = 0, LPWR = 1 KICK BRAKE STOP MDS Z MDS Z MDS Z MDP H Z MDP Z MDP Z MON H MON H MON L (a) KICK (b) BRAKE (c) STOP Timing Chart 2-6 CAV-W mode DCLV PWM MD = LPWR = 0 KICK BRAKE STOP MDS Z MDS Z MDS Z MDP H MDP L MDP Z MON H MON H MON H (a) KICK (b) BRAKE (c) STOP Timing Chart 2-7 CAV-W mode DCLV PWM MD = 0, LPWR = 1 KICK BRAKE STOP MDS Z MDS Z MDS Z MDP H MDP Z MDP Z MON H MON H MON H (a) KICK (b) BRAKE (c) STOP - 47 - CXD2548R Timing Chart 2-8 CLV-N mode DCLV PWM MD = LPWR = 0 MDS Z n * 236 (ns) n = 0 to 31 Acceleration MDP 132kHz 7.6s Deceleration Z Timing Chart 2-9 CLV-N mode DCLV PWM MD = 1, LPWR = 0 MDS Acceleration MDP 132kHz 7.6s Deceleration n * 236 (ns) n = 0 to 31 Timing Chart 2-10 CLV-W mode DCLV PWM MD = LPWR = 0 MDS Z Acceleration MDP Z Deceleration 264kHz 3.8s Timing Chart 2-11 CLV-W mode DCLV PWM MD = 0, LPWR = 1 MDS Z Acceleration MDP Z 264kHz 3.8s The BRAKE pulse is masked when LPWR = 1. - 48 - CXD2548R Timing Chart 2-12 CAV-W mode EPWM = DCLV PWM MD = LPWR = 0 Acceleration MDP Z Deceleration 264kHz 3.8s Timing Chart 2-13 CAV-W mode EPWM = 1, DCLV PWM MD = 0, LPWR = 1 Acceleration MDP Z 264kHz 3.8s The BRAKE pulse is masked when LPWR = 1. Timing Chart 2-14 CAV-W mode EPWM = 1, DCLV PWM MD = LPWR = 0 H PWMI L H MDP L Acceleration Deceleration Timing Chart 2-15 CAV-W mode EPWM = 1, DCLV PWM MD = 0, LPWR = 1 H PWMI L H MDP Z Acceleration The BRAKE pulse is masked when LPWR = 1. Note) CLV-W and CAV-W modes support control only by the ternary output of the MDP pin. Therefore, set DCLV PWM MD to 0 in CLV-W and CAV-W modes. - 49 - CXD2548R 2-2. Subcode Interface There are two methods for reading out a subcode externally. The 8-bit subcodes P to W can be read out from SBSO by inputting EXCK to the CXD2584R. Sub Q can be read out after checking CRC of the 80 bits in the subcode frame. Sub Q can be read out from the SQSO pin by inputting 80 clock pulses to the SQCK pin when SCOR comes correctly and CRCF is high. P to W Subcode Readout Data can be read out by inputting EXCK immediately after WFCK falls. (See Timing Chart 2-16.) 80-bit Sub Q Readout Fig. 2-2 shows the peripheral block of the 80-bit Sub Q register. * First, Sub Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check circuit. * 96-bit Sub Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, 80 bits are loaded into the parallel/serial register. When SQSO goes high 400s (monostable multivibrator time constant) or more after subcode readout, the CPU determines that new data (which passed the CRC check) has been loaded. * When the 80-bit data is loaded, the order of the MSB and LSB is inverted within each byte. As a result, although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first. * Once the 80-bit data load is confirmed, SQCK is input so that the data can be read. The SQCK input is detected, and the retriggerable monostable multivibrator is reset while the input is low. * The retriggerable monostable multivibrator has a time constant from 270 to 400s. When the duration when SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval, the serial/parallel register is not loaded into the parallel/serial register. * While the monostable multivibrator is being reset, data cannot be loaded in the 80-bit parallel/serial register. In other words, while reading out with a clock cycle shorter than this time constant, the register will not be rewritten by CRCOK and others. * See Timing Chart 2-17. * The high and low intervals for SQCK should be between 750ns and 120s. - 50 - CXD2548R Timing Chart 2-16 Internal PLL clock 4.3218 MHz WFCK SCOR EXCK 400ns max SBSO S0 * S1 Q R WFCK SCOR EXCK SBSO S0*S1 Q R S T U V W S0*S1 P1 QR S T U VW P1 P2 P3 Same Same Sub Code P.Q.R.S.T.U.V.W Read Timing - 51 - Fig. 2-2 Block Diagram (AFRAM) (ASEC) (AMIN) ADDRS CTRL SUBQ 80bit S/P Register SIN ABCDEFGH 8 8 8 8 8 8 Order Inversion 8 8 8 HGFEDCBA 80bit S/P Register SO LD LD LD LD LD SUBQ CRCC Mono/Multi LD LD SHIFT LD SI - 52 - SHIFT SQCK CRCF SQSO Mix CXD2548R Timing Chart 2-17 1 91 95 96 97 98 1 3 2 92 93 94 2 3 WFCK Order Inversion Determined by mode L 80 Clock CRCF2 SCOR SQSO CRCF1 SQCK Registere load forbidder - 53 - 750ns to 120s 270 to 400s when SQCK = high. ADR0 ADR1 ADR2 ADR3 CTL0 300ns max Mono/multi (Internal) SQCK SQSO CRCF CTL1 CTL2 CTL3 CXD2548R CXD2548R Timing Chart 2-18 Measurement interval (approximately 3.8s) Reference window (132.2kHz) Measurement pulse (VCK1/2) Measurement counter Load VF0 to 7 m The relative velocity of the disc can be obtained with the following equation. R= m+1 (R: Relative velocity, m: Measurement results) 32 VF0 to 7 is the result obtained by counting VCKI/2 pulses while the reference signal (132.2kHz) generated from the crystal (384Fs) is high. This count is 31 when the disc is rotating at normal speed and 63 when it is rotating at double speed (when DSPB is low). - 54 - CXD2548R [3] Description of Other CD Signal Processing and DAC System Functions 3-1. Description of DSP Operating Modes This LSI has three basic operating modes using a combination of spindle control and the PLL. The operations for each mode are described below. (a) CLV-N Mode This mode is compatible with the CXD2507AQ, and operation is the same as for the conventional control. The PLL capture range is 150kHz. (b) CLV-W Mode This is the wide capture range mode. This mode allows PLL to follow the rotational velocity of the disc. This rotational following control has two types: using the built-in VCO2 or providing an external VCO. The spindle is the same CLV servo as for the conventional series. Operation using the built-in VCO2 is described below. (When using an external VCO, input the signal from the VPCO1 pin to the low-pass filter, use the output from the low-pass filter as the control voltage for the external VCO, and input the oscillation from the VCO to the VCKI pin.) While starting to rotate a disc and/or speeding up to the lock range from the condition that a disc stops, CAV-W mode should be used. Concretely saying, firstly send $E665 to set CAV-W mode and kick a disc, secondly send $E60C to set CLV-W mode if ALOCK is high, which can be read out serially from the SQSO pin. CLV-W mode can be used while ALOCK is high. The microcomputer monitors the serial data output, and must return the operation to the speed adjusting state (CAV-W mode) when ALOCK becomes low. The control flow according to the microcomputer software in CLV-W mode is shown in Fig. 3-2. In CLV-W mode (normal), low power consumption is achieved by setting LPWR to high. Control was formerly performed by applying acceleration and deceleration pulses to the spindle motor. However, when LPWR is set to high, deceleration pulses are not output, thereby achieving low power consumption mode. CLV-W mode supports control only by the ternary output of the MDP pin. Therefore, when using CLV-W mode, set DCLV PWM MD to low. Note) The capture range for this mode is theoretically up to the signal processing limit. (c) CAV-W Mode This is CAV mode. In this mode the external clock is fixed and it is possible to control spindle to variable rotational velocity. The rotational velocity is determined by the VP0 to 7 setting values or the external PWM. When controlling the spindle with VP0 to 7, setting CAV-W mode with $E665 command and controlling VP0 to 7 with the $DX commands allows the rotational velocity to be varied from low speed to double speed. (See "$DX Commands".) Also, when controlling the spindle with the external PWM, the PWMI pin is binary input which becomes KICK during high intervals and BRAKE during low intervals. The microcomputer can know the rotational velocity using V16M. And the reference for the velocity measurement is a signal of 132.3kHz obtained by 1/128 of the crystal (384 Fs). The velocity is obtained by counting V16M/2 pulses while the reference is high, and the result is output from the new CPU interface as 8 bits (VP0 to 7). These measurement results are 31 when the disc is rotating at normal speed or 63 when it is rotating at double speed. These values match those of the 256 - n for control with VP0 to 7. In CAV-W mode, the spindle is set to the desired rotational velocity and the operation speed for the entire system follows this rotational velocity. Therefore, the cycles for the Fs system clock, PCM data and all other output signals from this LSI change according to the rotational velocity of the disc (excluding the servo output block). Note) The capture range for this mode is theoretically up to the signal processing limit. - 55 - CXD2548R CAV-W Rotational velocity CLVS Target velocity CLV-W CLVP Operation mode Spindle mode KICK Time LOCK ALOCK Fig. 3-1. Disc Stop to Regular Playback in CLV-W Mode CLV-W Mode CLV-W MODE START KICK $E800 Mute OFF $A000 CAV-W $E665 (CLVA) NO ALOCK = H ? YES CLV-W $E60C (CLVA) (WFCK PLL) YES ALOCK = L ? NO Fig. 3-2. CLV-W Mode Flow Chart - 56 - CXD2548R 3-2. Frame Sync Protection * In normal-speed playback, a frame sync is recorded approximately every 136s (7.35kHz). This signal is used as a reference to recognize the data within a frame. Conversely, if the frame sync cannot be recognized, the data is processed as error data because the data cannot be recognized. As a result, recognizing the frame sync properly is extremely important for improving playability. * In the CXD2548R, window protection and forward protection/backward protection have been adopted for frame sync protection. These functions achieve very powerful frame sync protection. There are two window widths: one for cases where a rotational disturbance affects the player and the other for cases where there is no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is fixed to 13, and the backward protection counter to 3. Concretely, when the frame sync is being played back normally and then cannot be detected due to scratches, a maximum of 13 frames are inserted. If frame sync cannot be detected for 13 frames or more, the window opens to resynchronize the frame sync. In addition, immediately after the window opens and the resynchronization is executed, if a proper frame sync cannot be detected within 3 frames, the window opens immediately. 3-3. Error Correction * In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the code is creased with 28-byte information and 4-byte C1 parity. For C2 correction, the code is created with 24-byte information and 4-byte C2 parity. Both C1 and C2 are Reed Solomon codes with a minimum distance of 5. * The CXD2548R's SEC strategy uses powerful frame sync protection and C1 and C2 error correction to achieve high playability. * The correction status can be monitored externally. See Table 3-1. * When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held or an average value interpolation was made for the data. MNT3 0 0 0 1 1 1 MNT1 0 0 1 0 0 1 MNT0 0 1 1 0 1 1 Description No C1 errors One C1 error corrected C1 correction impossible No C2 errors One C2 error corrected C2 correction impossible Table 3-1. - 57 - CXD2548R Timing Chart 3-1 Normal-speed PB 400 to 500ns RFCK t = Dependent on error condition MNT3 C1 correction C2 correction MNT1 MNT0 Strobe Strobe 3-4. DA Interface * The CXD2548R's DA interface is as follows. This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is high, the data is for the left channel. - 58 - Timing Chart 3-2 48bit slot Normal-Speed Playback LRCK (44.1k) 6 7 8 9 10 11 12 24 1 2 3 4 5 BCK (2.12M) WDCK PCMD L14 L13 L12 L11 L10 L9 L8 L7 L6 R0 Lch MSB (15) L5 L4 L3 L2 L1 L0 RMSB - 59 - 24 Rch MSB L0 48bit slot Double-Speed Playback LRCK (88.2k) 1 2 BCK (4.23M) WDCK PCMD Lch MSB (15) R0 CXD2548R CXD2548R 4-5. Digital Out There are three Digital Out: the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. The CXD2548R supports type 2 form 1. Sub Q data which are matched twice in succession after a CRC check are input to the first four bits (bits 0 to 3) of the channel status. Digital Out C bit 0 0 ID0 16 0 1 2 3 4 0 5 0 6 0 7 0 8 1 9 0 10 0 11 0 12 0 13 0 14 0 15 0 From sub Q ID1 COPY Emph 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0 32 48 0 176 Bits 0 to 3 Sub Q control bits that matched twice with CRCOK Bit 29 CAV-W: 1 Crystal: 0 Table 3-2. 3-6. Servo Auto Sequence This function performs a series of controls, including auto focus and track jumps. When the auto sequence command is received from the CPU, auto focus, 1-track jump, 2N-track jump and N-track move are executed automatically. Servo is used in an exclusive manner during the auto sequence execution (when XBUSY = low), so that commands from the CPU are not transferred to the servo, but can be sent to the CXD2548R. Connect the CPU and RF as shown in Fig. 3-3. When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of 100s after that point. This is to prevent the transfer of erroneous data to the servo when XBUSY changes from low to high by the monostable multivibrator, which is reset by CLOK being low (when XBUSY is low). - 60 - CXD2548R (a) Auto focus ($47) Focus search-up is performed, FOK and FZC are checked, and the focus servo is turned on. If $47 is received from the CPU, the focus servo is turned on according to Fig. 3-4. The auto focus starts with focus search-up, and note that the pickup should be lowered beforehand (focus search down). In addition, blind E of register 5 is used to eliminate FZC chattering. Concretely, the focus servo is turned on at the falling edge of FZC after FZC has been continuously high for a longer time than E. CXD2548R connection diagram when using auto sequence (example) RF FOK FOK DATA CXD2548R CLOK XLAT SENS Micro-computer Fig. 3-3 Auto focus Focus search up FOK=H YES NO (Check whether FZC is continuously high for the period of time E set with register 5.) FZC = H YES NO FZC = L YES Focus servo ON NO END Fig. 3-4-(a). Auto Focus Flow Chart - 61 - CXD2548R $47latch XLT FOK SENS (FZC) BUSY Command for SSP $03 Blind E $08 Fig. 3-4-(b). Auto Focus Timing Chart (b) Track jump 1, 10 and 2N-track jumps are performed respectively. Always use this when the focus, tracking, and sled servos are on. Note that tracking gain-up and braking-on should be sent beforehand because they are not involved in this sequence. * 1-track jump When $48 ($49 for REV) is received from the CPU, a FWD (REV) 1-track jump is performed in accordance with Fig. 3-5. Set blind A and brake B with register 5. * 10-track jump When $4A ($4B for REV) is received from the CPU, a FWD (REV) 10-track jump is performed in accordance with Fig. 3-6. The principal difference from the 1-track jump is to kick the sled. In addition, after kicking the actuator, when 5 tracks have been counted through COUT, the brake is applied to the actuator. Then, when the actuator speed is found to have slowed up enough (determined by the COUT cycle becoming longer than the overflow C set with register 5), the tracking and sled servos are turned on. * 2N-track jump When $4C ($4D for REV) is received from the CPU, a FWD (REV) 2N-track jump is performed in accordance with Fig. 3-7. The track jump count N is set with register 7. Although N can be set to 216 tracks, note that the setting is actually limited by the actuator. COUT is used for counting the number of jumps. Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is that after the tracking servo is turned on, the sled continues to move only for "D", set with register 6. * N-track move When $4E ($4F for REV) is received from the CPU, a FWD (REV) N-track move is performed in accordance with Fig. 3-8. N can be set to 216 tracks. COUT is used for counting the number of jumps. The N-track move is executed only by moving the sled, and is therefore suited for moving across several thousand to several tenthousand tracks. - 62 - CXD2548R Track Track kick sled servo WAIT (Blind A) (REV kick for REV jump) COUT = NO YES Track REV kick WAIT (Brake B) Track sled servo ON (FWD kick for REV jump) END Fig. 3-5-(a). 1-Track Jump Flow Chart $48 (REV = $49) latch XLT COUT BUSY Blind A Command for SSP $28 ($2C) $2C ($28) Brake B $25 Fig. 3-5-(b). 1-Track Jump Timing Chart - 63 - CXD2548R 10 Track Track, sled FWD kick WAIT (Blind A) (Counts COUT x 5) COUT = 5 ? YES Track, REV kick NO C = Over-flow ? YES Track sled servo ON NO (Check whether the COUT cycle is longer than overflow C.) END Fig. 3-6-(a). 10-Track Jump Flow Chart $4A (REV = $4B) latch XLT COUT BUSY Blind A Command for SSP COUT 5 count Over-flow C $2A ($2F) $2E ($2B) $25 Fig. 3-6-(b). 10-Track Jump Timing Chart - 64 - CXD2548R 2N Track Track, sled FWD kick WAIT (Blind A) COUT (MIRR) = N NO YES Track REV kick Counts COUT till N < 16. Counts MIRR till N 16. C = Over-flow NO YES Track servo ON WAIT (Kick D) Sled servo ON END Fig. 3-7-(a). 2N-Track Jump Flow Chart $4C (REV = $4D) latch XLT COUT (MIRR) BUSY Blind A Command for SSP $2A ($2F) COUT (MIRR) N count $2E ($2B) Over-flow C $26 ($27) Kick D $25 Fig. 3-7-(b). 2N-Track Jump Timing Chart - 65 - CXD2548R N Track move Track servo OFF Sled FWD kick WAIT (Blind A) COUT (MIRR) = N NO YES Track, sled servo OFF Counts COUT till N < 16. Counts MIRR till N 16. END Fig. 3-8-(a). N-Track Move Flow Chart $4E (REV = $4F) latch XLT COUT (MIRR) BUSY Blind A Command for SSP $22 ($23) COUT (MIRR) N count $20 Fig. 3-8-(b). N-Track Move Timing Chart - 66 - CXD2548R 3-7. Asymmetry Compensation Fig. 3-9 shows the block diagram and circuit example. ASYO R1 RF R1 R2 R1 ASYI R1 BIAS R1 2 = R2 5 Fig. 3-9. Asymmetry Compensation Application Circuit - 67 - CXD2548R 3-8. Channel Clock Regeneration by the Digital PLL Circuit * The channel clock is necessary for demodulating the EFM signal regenerated by the optical system. Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to 11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a result, T, that is the channel clock, is necessary. In an actual player, a PLL is necessary to regenerate the channel clock because the fluctuation in the spindle rotation alters the width of the EFM signal pulses. The block diagram of this PLL is shown in Fig. 3-10. The CXD2548R has a built-in three-stage PLL. * The first-stage PLL is a wide-band PLL. When using the internal VCO2, an external LPF is necessary; when not using the internal VCO2, external LPF and VCO are necessary. The output of this first-stage PLL is used as a reference for all clocks within the LSI. * The second-stage PLL regenerates the high-frequency clock needed by the third-stage digital PLL. * The third-stage PLL is a digital PLL that regenerates the actual channel clock. * A new digital PLL has been provided for CLV-W mode to follow the rotational speed of the disc in addition to the conventional secondary loop. - 68 - CXD2548R Block Diagram 3-10 CLV-W CAV-W Spindle rotation information X'tal OSC 1/2 1/32 Selector VPCO1, 2 Phase comparator XTSL CLV-N 1/2 1/n CLV-W /CLV-N CAV-W Microcomputer control n = 1 to 256 (VP7 to 0) LPF VCOSEL2 1/K (KSL1, 0) VCO2 VCTL V16M 2/1 MUX VPON VCKI Phase comparator 1/M PCO 1/N FILI FILO 1/K (KSL3, 2) CLTV VCO1 Digital PLL RFPLL CXD2548R VCOSEL1 - 69 - CXD2548R 3-9. Digital CLV Fig. 3-11 shows the block diagram. Digital CLV outputs MDS error and MDP error with PWM, with sampling frequency increased up to 130Hz during normal-speed playback in CLVS, CLVP and other modes. In addition, the digital spindle servo gain is variable. Digital CLV CLVS U/D MDS Error MDP Error Measure Measure CLV P/S 2/1 MUX Over Sampling Filter-1 Gain MDP 1/2 MUX Gain MDS Over Sampling Filter-2 CLV P/S Noise Shape KICK, BRAKE, STOP Modulation PWMI DCLVMD, LPWR Mode Select MDS MDP CLVS U/D: MDS error: MDP error: PWMI: Up/down signal from CLVS servo Frequency error for CLVP servo Phase error for CLVP servo Spindle drive signal from the microcomputer Fig. 3-11. Block Diagram - 70 - CXD2548R 3-10. 1-bit DAC Block (a) DAC block input timing Timing Chart 3-3 shows the DAC block input timing chart. Audio data is not transferred from the CD signal processor block to the DAC block inside the CXD2548R. This is to allow data to be sent to the DAC block via the audio DSP, etc. When the data is input to the DAC block without using the audio DSP, the data must be connected outside the LSI. In this case, EMPH, LRCK, BCK and PCMD can be connected directly with EMPHI, LRCKI, BCKI and PCMDI. (b) Description of DAC block functions Zero data detection When the condition where the lower 4 bits of the input data are DC and the remaining upper bits are all "0" or all "1" has continued about for 300ms, zero data is detected. Zero data detection is performed independently for the left and right channels. Mute flag output The LMUT and RMUT pins go active when any one of the following conditions is met. The polarity can be selected with the ZDPL command of $9X. * When zero data is detected * When a high signal is input to the SYSM pin * When the SMUT command of $AX is set Attenuation operation Assuming attenuation data X1, X2 and X3 (X1 > X3 > X2), the corresponding audio outputs are Y1, Y2 and Y3 (Y1 > Y3 > Y2). First, X1 is sent, followed by X2. If X2 is sent before X1 reaches Y1 (A in the figure), X1 continues approaching Y2. Next, if X3 is sent before X1 reaches Y2 (B or C in the figure), X1 then approaches Y3 from the value (B or C in the figure) at that point. 0dB 3FF (H) A Y1 B Y3 C Y2 - 000 (H) 23.2 [ms] Soft mute When any one of the following conditions is met, soft mute results and the input data is attenuated to "0". * When attenuation data of 000 (high) is set * When "Soft mute" in the operation controls for serial control is high * When a high signal (= mute) is input to the input pin SYSM 0dB - 23.2 [ms] 23.2 [ms] t - 71 - Timing Chart 3-3 Normal-Speed Playback LRCKI (44.1k) 6 7 8 9 10 11 12 1 2 3 4 5 24 BCKI (2.12M) PCMDI R0 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 Lch MSB (15) L4 L3 L2 L1 L0 RMSB - 72 - 24 Rch MSB L0 Double-Speed Playback LRCKI (88.2k) 1 2 BCKI (4.23M) PCMDI Lch MSB (15) R0 CXD2548R DAC Block Input Timing CXD2548R 3-11. LPF Block The CXD2548R contains an initial-stage secondary active LPF with numerous resistors and capacitors and an operational amplifier with reference voltage. The resistors and capacitors are attached externally, allowing the cut-off frequency fc to be determined flexibly. The reference voltage (VC) is (AVDD - AVSS)/2. The LPF block application circuit is shown below. In this circuit, the cut-off frequency is fc 40kHz. The capacitance of the external capacitors when fc = 30kHz and 50kHz are noted below as a reference. * When fc 30kHz: C1 = 200pF, C2 = 910pF * When fc 50kHz: C1 = 120pF, C2 = 560pF LPF Block Application Circuit AOUT1 (2) 12k C2 680p AIN1 (2) Vc C1 150p 12k 12k Analog out LOUT1 (2) Fig. 3-12. LPF External Circuit - 73 - CXD2548R 3-12. Setting the Playback Speed for the CD-DSP and 1-bit DAC Blocks (in CLV-N mode) (a) CD-DSP block In the CXD2548R, the following playback modes can be selected through different combinations of the crystal, XTSL pin and the DSPB command of $9X. CD-DSP block playback speed X'tal 768Fs 768Fs 384Fs 384Fs 384Fs XTSL 1 1 0 0 1 DSPB 0 1 0 1 1 CD-DSP block playback speed 1x 2x 1x 2x 1 x1 Fs = 44.1kHz. 1 Low power consumption mode. The CD-DSP processing speed is halved, allowing power consumption to be reduced. (b) 1-bit DAC block The operation speed for the DAC block is determined by the crystal and the MCSL command of $9X regardless of the CD-DSP operating conditions noted above. This allows the playback modes for the DAC and CD-DSP blocks to be set independently. 1-bit DAC block playback speed X'tal 768Fs 768Fs 384Fs Fs = 44.1kHz. MCSL 1 0 0 DAC block playback speed 1x 2x 1x - 74 - CXD2548R [4] Description of Servo Signal Processing System Functions and Commands 4-1. General Description of the Servo Signal Processing System (Voltages are the values for a 5V power supply.) Focus servo Sampling rate: 88.2kHz Input range: 2.5V center 1.0V Output format: 7-bit PWM Others: Offset cancel Focus bias adjustment Focus search Gain-down function Defect countermeasure Auto gain control Tracking servo Sampling rate: Input range: Output format: Others: 88.2kHz 2.5V center 1.0V 7-bit PWM Offset cancel E:F balance adjustment Track jump Gain-up function Defect countermeasure Drive cancel Auto gain control Vibration countermeasure Sled servo Sampling rate: Input range: Output format: Others: 345Hz 2.5V center 1.0V 7-bit PWM Sled move FOK, MIRR, DFCT signals generation RF signal sampling rate: 1.4MHz Input range: 2.15V to 5.0V Others: RF zero level automatic measurement The signal input from the RFDC pin is multiplied by a factor of 0.7 and loaded into the A/D converter. - 75 - CXD2548R 4-2. Digital Servo Block Master Clock (MCK) The FSTI pin is the reference clock input pin. The internal master clock (MCK) is generated by dividing the frequency of the signal input to FSTI. The frequency division ratio is 1/2 or 1/4. Table 4-1 below shows the hypothetical case where the crystal clock generated from the digital signal processor block is 2/3 frequency-divided and input to the FSTI pin by externally connecting the FSTI pin and the FSTO pin. The XT4D and XT2D command settings can be made with D13 and D12 of $3F. (Default = 0) The digital servo block is designed with an MCK frequency of 5.6448MHz. Mode 1 2 3 4 X'tal 384Fs 384Fs 768Fs 768Fs FSTO 256Fs 256Fs 512Fs 512Fs FSTI 256Fs 256Fs 512Fs 512Fs XTSL 0 1 XT4D 0 0 1 0 XT2D 1 0 0 0 Frequency division ratio 1/2 1/2 1/4 1/4 MCK frequency 128Fs 128Fs 128Fs 128Fs Fs = 44.1kHz, : Don't care Table 4-1. 4-3. AVRG (Average) Measurement and Compensation The CXD2548R has a circuit that measures AVRG of RFDC, VC, FE, and TE and a circuit that compensates them to control servo effectively. AVRG measurement and compensation is necessary to initialize the CXD2548R, and is able to cancel the offset by performing each AVRG measurement before playback operation and using these results for compensation. The level applied to the VC, FE, RFDC and TE pins can be measured by setting D15 (VLCM), D13 (FLM), D11 (RFLM) and D4 (TCLM) of $38 respectively to 1. AVRG measurement consists of digitally measuring the level applied to each analog input pin by taking the average of 256 samples, and then loading these values into the AVRG register. AVRG measurement requires approximately 2.9ms to 5.8ms after the command is received. During AVRG measurement, if the upper 8 bits of the serial data are 38 (Hex), the completion of AVRG measurement operation can be confirmed through the SENS pin. (See Timing Chart 4-1.) XLAT 2.9 to 5.8ms SENS (= XAVEBSY) Max. 1s Completion of AVRG measurement Timing Chart 4-1. - 76 - CXD2548R - 77 - CXD2548R 4-4. E:F Balance Adjustment Function When the disc is rotated with the laser on, and with the FCS (focus) servo on via FCS Search (focus search), the traverse waveform appears in the TE signal due to disc eccentricity. In this condition, the low-frequency component can be extracted from the TE signal using the built-in TRK hold filter by setting D5 (TBLM) of $38 to 1. The extracted low-frequency component is loaded into the TRVSC register as a digital value, and the TRVSC register value is established when TBLM returns to 0. Next, setting D2 (TLC2) of $38 to 1 applies only the amount of compensation (subtraction) equal to the TRVSC register value to the values obtained from the TE and SE input pins, enabling the E:F balance offset to be adjusted. (See Fig. 4-2.) 4-5. FCS Bias (Focus Bias) Adjustment Function The FBIAS register value can be added to the FCS servo filter input by setting D14 (FBON) of $3A to 1. (See Fig. 4-2.) When the FBIAS register value is set to D11 = 0 and D10 = 1 by $34F, data can be written using the 9-bit value of D9 to D1 (D9: MSB). In addition, the RF jitter can be monitored by setting the SOCT and SLO commands of $B to 1. (See "DSP Block Timing Chart".) The FBIAS register can be used as a counter by setting D13 (FBSS) of $3A to 1. It operates as an up/down counter. The FBIAS register functions as an up counter when D12 (FBUP) of $3A = 1, and as a down counter when D12 (FBUP) of $3A = 0. The number of up and down steps can be changed by setting D11 and D10 (FBV1 and FBV0) of $3A. When using the FBIAS register as a counter, the counter stops when the value set beforehand in FBL9 to 1 of $34 matches the FCSBIAS value. Also, if the upper 8 bits of the command register are $3A at this time, the counter stop can be monitored through SENS. Here, the FBIAS setting values FB9 to 1 and the FBIAS LIMIT values FBL9 to 1 are assumed to be set in status A. For example, if command registers FBUP = 0, FBV1 = 0, FBV0 = 0 and FBSS = 1 are set from this status, down count starts from status A and approaches the set LIMIT value. When the LIMIT value is reached and the FBIAS value matches FBL9 to 1, the counter stops and the SENS pin goes to high. Note that the up/down counter changes with each sampling cycle of the focus servo filter. The number of steps by which the count value changes can be selected from 1, 2, 4 or 8 steps by FBV1 and FBV0. When converted to FE input, 1 step corresponds to approximately 3.9 [mV]. A:Register mode B:Counter mode C:Counter mode (when stopped) A FBIAS setting value (FB9 to 1) B C LIMIT value (FBL9 to 1) SENS pin Fig. 4-1. - 78 - RFDC from A/D RF AVRG register RFLC - To RF In register TE, SE from A/D - - - To TRK/SLD In register TLC0 VC AVRG register TE AVRG register TLC1 TRVSC register TLC2 - 79 - VCLC - FE AVRG register FLC1 - FBIAS register + FBON To FCS In register FLC0 - To FZC register CXD2548R FE from A/D Fig. 4-2. CXD2548R 4-6. AGCNTL (Auto Gain Control) Function The AGCNTL function automatically adjusts the filter internal gain in order to obtain the appropriate gain with the servo loop. AGCNTL not only copes with the sensitivity variation of the actuator and photo diode, etc., but also obtains the optimal gain for each disc. The AGCNTL command is sent when each servo is turned on. During AGCNTL operation, if the upper 8 bits of the serial data are 38 (Hex), the completion of AGCNTL operation can be confirmed through the SENS pin. (See Timing Chart 4-2 and "Description of SENS Signals".) Setting D9 and D8 of $38 to 1 set FCS (focus) and TRK (tracking) respectively to AGCNTL operation. Note) During AGCNTL operation, each servo filter gain must be normal, and the anti-shock circuit (described hereafter) must be disabled. XLAT Max. 11.4s SENS (= AGOK) AGCNTL completion Timing Chart 4-2. Coefficient K13 changes for AGF (focus AGCNTL) and coefficients K23 and K07 change for AGT (tracking AGCNTL) due to AGCNTL. These coefficients change from 01 to 7F (Hex), and they must also be set within this range when written externally. After AGCNTL operation has completed, these coefficient values can be confirmed by reading them out from the SENS pin with the serial readout function (described hereafter). AGCNTL related setting The following settings can be changed with $35, $36 and $37. FG6 to FG0; AGF convergence gain setting, effective setting range: 00 to 57 (Hex) TG6 to TG0; AGT convergence gain setting, effective setting range: 00 to 57 (Hex) AGS; Self-stop on/off AGJ; Convergence completion judgment time AGGF; Internally generated sine wave amplitude (AGF) AGGT; Internally generated sine wave amplitude (AGT) AGV1; AGCNTL sensitivity 1 (during high sensitivity adjustment) AGV2; AGCNTL sensitivity 2 (during low sensitivity adjustment) AGHS; High sensitivity adjustment on/off AGHT; High sensitivity adjustment time Note) Converging servo loop gain values can be changed with the FG6 to 0 and TG6 to 0 setting values. In addition, these setting values must be within the effective setting range. The default settings aim for 0 dB at 1kHz. However, since convergence values vary according to the characteristics of each constituent element of the servo loop, FG and TG values should be set as necessary. - 80 - CXD2548R AGCNTL and default operation have two stages. In the first stage, high sensitivity adjustment is performed for a certain period of time (select 256/128ms with AGHT), and the AGCNTL coefficient approaches the appropriate value roughly. The sensitivity at this time can be selected from two types with AGV1. In the second stage, the AGCNTL coefficient approaches the appropriate value finely with relatively low sensitivity. The sensitivity for the second stage can be selected from two types with AGV2. In the second stage of default operation, when the AGCNTL coefficient reaches the appropriate value and stops changing, the CXD2548R confirms that the AGCNTL coefficient has not changed for a certain period of time (select 63/31ms with AGHJ), and then completes AGCNTL operation. (Self-stop mode) This self-stop mode can be canceled by setting AGS to 0. In addition, the first stage is omitted for AGCNTL operation when AGHS is set to 0. An example of AGCNTL coefficient transitions during AGCNTL operation and the relationship between the various settings are shown in Fig. 4-3. Initial value Slope AGV1 AGCNTL coefficient value Slope AGV2 Convergence value AGHT AGCNTL Start SENS AGJ AGCNTL completion Fig. 4-3. - 81 - CXD2548R 4-7. FCS Servo and FCS Search (Focus Search) The FCS servo is controlled by the 8-bit serial command $0X. (See Table 4-2.) Register name Command D23 to D20 D19 to D16 10 11 0 FOCUS CONTROL 0000 00 01 010 011 FOCUS SERVO ON (FOCUS GAIN NORMAL) FOCUS SERVO ON (FOCUS GAIN DOWN) FOCUS SERVO OFF, 0V OUT FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT FOCUS SEARCH VOLTAGE DOWN FOCUS SEARCH VOLTAGE UP : Don't care Table 4-2. FCS Search FCS search is required in the course of turning on the FCS servo. Fig. 4-4 shows the signals for sending commands $00 $02 $03 and performing only FCS search. Fig. 4-5 shows the signals for sending $08 (FCS on) after that. $00 $02 $03 $00 $02 $03 $08 0 FCSDRV FCSDRV RF FOK FZC comparator level FE 0 RF FOK FE 0 FZC FZC Fig. 4-4. Fig. 4-5. - 82 - CXD2548R 4-8. TRK (Tracking) and SLD (Sled) Servo Control TRK and SLD servo is controlled by the 8-bit command $2X. (See Table 4-3.) When the upper 4 bits of the serial data are 2 (Hex), TZG is output from the SENS pin. Register name Command D23 to D20 D19 to D16 00 01 10 2 TRACKING MODE 00 10 11 00 01 10 11 TRACKING SERVO OFF TRACKING SERVO ON FORWARD TRACK JUMP REVERSE TRACK JUMP SLED SERVO OFF SLED SERVO ON FORWARD SLED MOVE REVERSE SLED MOVE : Don't care Table 4-3. TRK Servo The TRK JUMP (track jump) height can be set with 6 bits (D13 to D8) of $36. In addition, when the TRK servo is on and D17 of $1 is set to 1, the TRK servo filter assumes gain-up status. The filter also assumes gain-up status when vibration detection is performed with the LOCK signal low and the anti-shock circuit (described hereafter) enabled. The gain-up filter used when TRK has assumed gain-up status has two types of structures which can be selected by setting D16 of $1. (See Table 4-5.) SLD Servo The SLD MOV (sled move) output, composed of a basic value from 6 bits (D13 to D8) of $37, is determined by multiplying this value by 1 x, 2 x, 3 x, or 4 x magnification set using D17 and D16 when D19 = D18 = 0 is set with $3. (See Table 4-4.) SLD MOV must be performed continuously for 50s or more. In addition, if the LOCK input signal goes low when the SLD servo is on, the SLD servo turns off. Note) When the LOCK signal is low, the TRK servo is set to gain-up status and the SLD servo is turned off by the default. These operations are disabled by setting D6 (LKSW) of $38 to 1. Register name Command D23 to D20 D19 to D16 0000 3 SELECT 0011 0001 0010 0011 SLED KICK LEVEL (basic value x 1) SLED KICK LEVEL (basic value x 2) SLED KICK LEVEL (basic value x 3) SLED KICK LEVEL (basic value x 4) Table 4-4. - 83 - CXD2548R 4-9. MIRR and DFCT Signal Generation The RF signal obtained from the RFDC pin is sampled at approximately 1.4MHz and loaded. The MIRR and DFCT signals are generated from this RF signal. MIRR Signal Generation The loaded RF signal is applied to peak hold and bottom hold circuits. An envelope is generated from the waveforms generated in these circuits, and the MIRR comparator level is generated from the average of these envelope waveforms. The MIRR signal is generated by comparing this MIRR comparator level with the waveform generated by subtracting the bottom hold value from the peak hold value. (See Fig. 4-6.) RF Peak Hold Bottom Hold Peak Hold -Bottom Hold MIRR Comp (Mirror comparator level) H MIRR L Fig. 4-6. DFCT Signal Generation The loaded RF signal is input to two peak hold circuits with different time constants, and the DFCT signal is generated by comparing the difference between these two peak hold waveforms with the DFCT comparator level. (See Fig. 4-7.) The DFCT comparator level can be selected from four values using D13 and D12 of $3B. RF Peak Hold1 Peak Hold2 Peak Hold2 -Peak Hold1 SDF (Defect comparator level) H DFCT L Fig. 4-7. - 84 - CXD2548R 4-10. DFCT Countermeasure Circuit The DFCT countermeasure circuit performs operations to maintain the directionality of the servo so that the servo does not become easily dislocated due to scratches or defects on discs. Specifically, these operations are achieved by performing scratch and defect detection with the DFCT signal generation circuit, and when DFCT goes high, applying the low frequency component of the error signal before DFCT went high to the FCS and TRK servo filter inputs. (See Fig. 4-8.) In addition, these operations are activated by the default. They can be disabled by setting D7 (DFSW) of $38 to 1. Hold Filter Error signal Input register DFCT Hold register EN Servo Filter Fig. 4-8. 4-11. Anti-Shock Circuit When vibrations are produced in the CD player, this circuit forces the TRK filter to assume gain-up status so that the servo does not become easily dislocated. This circuit is for systems which require vibration countermeasures. Concretely, vibrations are detected using an internal anti-shock filter and comparator circuit, and the gain is increased. (See Fig. 4-9.) The comparator level is fixed to 1/16 of the maximum comparator input amplitude. However, the comparator level is practically variable by adjusting the anti-shock filter output coefficient K35. This function can be turned on and off by D19 of $1 when the brake circuit (described hereafter) is off. (See Table 4-5.) This circuit can also support an external vibration detection circuit, and can set the TRK servo filter to gain-up status by inputting high level to the ATSK pin. When the serial data is $1, vibration detection can be monitored from the SENS pin. ATSK TE Anti Shock Filter Comparator SENS TRK Gain Up Filter TRK Gain Normal Filter TRK PWM Gen Fig. 4-9. - 85 - CXD2548R 4-12. Brake Circuit Immediately after a long distance track jump it tends to be hard for the actuator to settle and for the servo to turn on. The brake circuit prevents these phenomenon. In principle, this circuit cuts unnecessary portions of the tracking drive and applies the brake by utilizing the 180 offset in the RF envelope and tracking error phase relationship which occurs when the actuator traverses the track in the radial direction from the inner track to the outer track and vice versa. (See Figs. 4-10 and 4-11.) Concretely, this operation is achieved by masking the tracking drive using the TRKCNCL signal generated by loading the MIRR signal at the edge of the TZC (Tracking Zero Cross) signal. The brake circuit can be turned on and off by D18 of $1. (See Fig. 4-5.) Inner track Outer track FWD REV Servo ON JMP JMP TRK DRV TRK DRV Outer track Inner track REV FWD Servo ON JMP JMP RF Trace MIRR TE TZC Edge TRKCNCL TRK DRV SENS TZC out 0 0 RF Trace MIRR TE TZC Edge TRKCNCL TRK DRV SENS TZC out 0 0 Fig. 4-10. Fig. 4-11. Register name Command D23 to D20 D19 to D16 10 0 1 1 TRACKING CONTROL 0001 0 0 1 1 0 ANTI SHOCK ON ANTI SHOCK OFF BRAKE ON BRAKE OFF TRACKING GAIN NORMAL TRACKING GAIN UP TRACKING GAIN UP FILTER SELECT 1 TRACKING GAIN UP FILTER SELECT 2 : Don't care Fig. 4-5. - 86 - CXD2548R 4-13. COUT Signal The COUT signal is output to count the number of tracks during traverse, etc. It is basically generated by loading the MIRR signal at both edges of the TZC signal. However, the used TZC signal can be selected and there are two types of output methods according to the COUT signal application. For 1-track jumps, etc. Fast phase COUT signal generation with a fast phase TZC signal. For High-speed traverse Reliable COUT signal generation with a delayed phase TZC signal. This is because some time is required to generate the MIRR signal, and it is necessary to delay the TZC signal in accordance with the MIRR signal delay during high-speed traverse. The COUT signal output method is switched with D16 when D19 = D18 = 1 and D17 = 0 are set with $3. (When D16 = 1, for delayed phase and high-speed traverse.) In addition, the TZC signal delay can be selected from two values with D14 of $36. 4-14. Serial Readout Circuit The following measurement and adjustment results can be read out from the SENS pin by inputting the readout clock to the SCLK pin by $39. (See Fig. 4-12, Table 4-6 and "Description of SENS Signals".) Specified commands $390C VC AVRG measurement result $3908 FE AVRG measurement result $3904 TE AVRG measurement result $391F RF AVRG measurement result $3953 FCS AGCNTL coefficient result $3963 TRK AGCNTL coefficient result $391C TRVSC adjustment result $391D FBIAS register value XLAT tDLS tSPW SCLK 1/fSCLK Serial Read Out Data (SENS) *** MSB *** LSB Fig. 4-12. Item SCLK frequency SCLK pulse width Delay time Symbol fSCLK Min. Typ. Max. 1 500 15 Table 4-6. During readout, the upper 8 bits of the serial data must be 39 (Hex). - 87 - Unit MHz ns s tSPW tDLS CXD2548R 4-15. Writing the Coefficient RAM The coefficient RAM can be rewritten by $34. All coefficients have default values in the built-in ROM, and transfer from the ROM to the RAM is completed approximately 40s after the XRST pin rises. (The coefficient RAM cannot be rewritten during this period.) After that, the characteristics of each built-in filter can be finely adjusted by rewriting the data for each address of the coefficient RAM. The coefficient rewrite command is comprised of 24 bits, with D14 to D8 of $34 as the address (D15 = 0) and D7 to D0 as data. 4-16. PWM Output FCS, TRK and SLD outputs are output as PWM waveforms. In particular, FCS and TRK permit accurate drive by using a double oversampling noise shaper. Timing Chart 4-3 and Fig. 4-13 show examples of output waveforms and drive circuits. MCK (5.6448MHz) Output value +A SLD 64tMCK 64tMCK 64tMCK Output value -A Output value 0 SFDR AtMCK SRDR AtMCK FCS/TRK 32tMCK 32tMCK 32tMCK 32tMCK 32tMCK 32tMCK FFDR/ TFDR A tMCK 2 A tMCK 2 FRDR/ TRDR A tMCK 2 A tMCK 2 tMCK = 1 180ns 5.6448MHz Timing Chart 4-3. - 88 - CXD2548R Example of Drive Circuit VCC 22k 22k RDR FDR 22k 22k DRV VEE Fig. 4-13. Operational Amplifier Drive Circuit - 89 - CXD2548R 4-17. Servo Status Changes Produced by the LOCK Signal When the LOCK signal becomes low, the TRK servo assumes the gain-up status and the SLD servo turns off in order to prevent SLD free-running. Setting D6 (LKSW) of $38 to 1 deactivates this function. In other words, neither the TRK servo nor the SLD servo change even when the LOCK signal becomes low. This enables microcomputer control. 4-18. Description of Commands and Data Sets The following description contains portions which convert internal voltages into the values when they are output externally and describe them as input conversion or output conversion. Input conversion converts these voltages into the voltages entering input pins before A/D conversion. Output conversion converts PWM output values into analog voltage values. Both types of conversion are calculated at VDD = 5.0V. If this voltage changes, the conversion values also change proportionally. (Voltage conversion = VDDX/5; VDDX: used supply voltage) - 90 - CXD2548R $34 D15 0 D14 KA6 D13 KA5 D12 KA4 D11 KA3 D10 KA2 D9 KA1 D8 KA0 D7 KD7 D6 KD6 D5 KD5 D4 KD4 D3 KD3 D2 KD2 D1 KD1 D0 KD0 When D15 = 0 KA6 to KA0: Coefficient address KD7 to KD0: Coefficient data D15 1 D14 1 D13 1 D12 1 D11 1 D10 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 -- FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1 When D15 = D14 = D13 = D12 = D11 = 1 ($34F) D10 = 0 FBIAS LIMIT register write FBL9 to FBL1: Data; data compared with FB9 to 1, FBL9 = MSB. When using the FBIAS register in counter mode, counter operation stops when the value of FB9 to 1 matches with FBL9 to 1. D15 1 D14 1 D13 1 D12 1 D11 0 D10 1 D9 FB9 D8 FB8 D7 FB7 D6 FB6 D5 FB5 D4 FB4 D3 FB3 D2 FB2 D1 FB1 D0 -- When D15 = D14 = D13 = D12 = 1. ($34F) D11 = 0, D10 = 1 FBIAS register write FB9 to FB1: Data; FB9 is MSB two's complement data. For FE input conversion, FB9 to FB1 = 011111111 corresponds to approximately +1V and FB9 to FB1 = 100000000 to -1V respectively. (when the supply voltage = 5V) D15 1 D14 1 D13 1 D12 1 D11 0 D10 0 D9 TV9 D8 TV8 D7 TV7 D6 TV6 D5 TV5 D4 TV4 D3 TV3 D2 TV2 D1 TV1 D0 TV0 When D15 = D14 = D13 = D12 = 1. ($34F) D11 = 0, D10 = 0 TRVSC register write TV9 to TV0: Data; TV9 is MSB two's complement data. For TE input conversion, TV9 to TV0 = 0011111111 corresponds to approximately +1V and TV9 to TV0 = 1100000000 to -1V respectively. (when the supply voltage = 5V) Note) * When the TRVSC register is read out, the data length is 9 bits. At this time, data corresponding to each bit of TV8 to TV0 during external write are read out. * When reading out internally measured values and then writing these values externally, set TV9 the same as TV8. - 91 - CXD2548R $35 D15 FT1 D14 FT0 D13 FS5 D12 FS4 D11 FS3 D10 FS2 D9 FS1 D8 FS0 D7 FTZ D6 FG6 D5 FG5 D4 FG4 D3 FG3 D2 FG2 D1 FG1 D0 FG0 FT1, FT0, FTZ: Focus search-up speed Default value: 010 (3.36V/s) Focus drive output conversion FT1 0 0 1 1 0 0 1 1 FS5 to FS0: FT0 0 1 0 1 0 1 0 1 FTZ 0 0 0 0 1 1 1 1 Focus search speed 6.73V/s 3.36 2.24 1.68 8.97 5.38 4.49 3.85 Focus search limit voltage Default value: 011000 (1.875V) Focus drive output conversion FG6 to FG0: AGF convergence gain setting value Default value: 0101101 $36 D15 0 DTZC: D14 D13 D12 TJ4 D11 TJ3 D10 TJ2 D9 TJ1 D8 D7 D6 D5 TG5 D4 TG4 D3 TG3 D2 TG2 D1 TG1 D0 TG0 DTZC TJ5 TJ0 SFJP TG6 DTZC delay (8.5/4.25s) Default value: 0 (4.25s) TJ5 to TJ0: Track jump voltage Default value: 001110 ( 1.09V) Tracking drive output conversion SFJP: Surf jump mode on/off TRK PWM output is made by adding the tracking filter output and TJReg (TJ5 to 0), by setting D7 to 1 (on). TG6 to TG0: AGT convergence gain setting value Default value: 0101110 - 92 - CXD2548R $37 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT FZSH, FZSL: FZC (Focus Zero Cross) slice level Default value: 01 (250mV); FE input conversion FZSH 0 0 1 1 FZSL 0 1 0 1 Slice level +500mV +250 +125 +62.5 SM5 to SM0: Sled move voltage Default value: 010000 ( 1.25V) Sled drive output conversion AGS: AGCNTL self-stop on/off Default value: 1 (on) AGJ: AGCNTL convergence completion judgment time during low sensitivity adjustment (31/63ms) Default value: 0 (63ms) AGGF: Focus AGCNTL internally generated sine wave amplitude (small/large) Default value: 1 (large) AGGT: Tracking AGCNTL internally generated sine wave amplitude (small/large) Default value: 1 (large) FE/TE input conversion AGGF AGGT AGV1: AGV2: AGHS: AGHT: 0 (small) 1 (large) 0 (small) 1 (large) 63mV 125 125mV 250 AGCNTL convergence sensitivity during high sensitivity adjustment; high/low Default value: 1 (high) AGCNTL convergence sensitivity during low sensitivity adjustment; high/low Default value: 0 (low) AGCNTL high sensitivity adjustment on/off Default value: 1 (on) AGCNTL high sensitivity adjustment time (128/256ms) Default value: 0 (256ms) - 93 - CXD2548R $38 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0 VCLM: VCLC: FLM: FLC0: RFLM: RFLC: AGF: AGT: DFSW: LKSW: TBLM: TCLM: FLC1: TLC2: TLC1: TLC0: VC level measurement (on/off) VC level compensation for FCS In register (on/off) Focus zero level measurement (on/off) Focus zero level compensation for FZC register (on/off) RF zero level measurement (on/off) RF zero level compensation (on/off) Focus auto gain adjustment (on/off) Tracking auto gain adjustment (on/off) Defect disable switch (on/off) Setting this switch to 1 (on) disables the defect countermeasure circuit. Lock switch (on/off) Setting this switch to 1 disables the sled free-running prevention circuit. Traverse center measurement (on/off) Tracking zero level measurement (on/off) Focus zero level compensation for FCS In register (on/off) Traverse center compensation (on/off) Tracking zero level compensation (on/off) VC level compensation for TRK/SLD In register (on/off) Note) Commands marked with are accepted every 2.9ms. All commands are on when set to 1. - 94 - CXD2548R $39 D15 D14 D13 SD5 D12 SD4 D11 SD3 D10 SD2 D9 SD1 D8 SD0 DAC SD6 DAC: Serial data readout DAC mode (on/off) SD6 to SD0: Serial readout data select SD6 1 0 SD5 Readout data Readout data length 8 bit 16 bit Coefficient RAM data for address = SD5 to SD0 1 Data RAM data for address = SD4 to SD0 SD4 SD3 to SD0 1 1 1 1 0 0 1 1 0 0 0 0 0 1 1 1 1 0 0 1 0 1 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 0 1 0 1 0 1 0 1 0 RF AVRG register RFDC input signal FBIAS register TRVSC register RFDC envelope (bottom) RFDC envelope (peak) VC AVRG register FE AVRG register TE AVRG register FE input signal TE input signal SE input signal VC input signal 1 0 0 8 bit 8 bit 9 bit 9 bit 8 bit 8 bit 9 bit 9 bit 9 bit 8 bit 8 bit 8 bit 8 bit : Don't care 0 Note) Coefficients K40 to K4F cannot be read out. See the description for SRO1 of $3F concerning readout methods for the above data. - 95 - CXD2548R $3A D15 0 FBON: D14 D13 D12 D11 D10 D9 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 FBON FBSS FBUP FBV1 FBV0 TJD0 FPS1 FPS0 TPS1 TPS0 CEIT SJHD INBK MTI0 FBIAS (focus bias) register addition (on/off) The FBIAS register value is added to the signal loaded into the FCS In register by setting D14 to 1 (on). FBSS: FBIAS (focus bias) register/counter switching The FCS BIAS register can be used as a counter by setting D13 to 1 (on). FBUP: FBIAS (focus bias) counter up/down operation switching This performs counter up/down control when FBSS = 1. The FBIAS register functions as a down counter with D12 set to 0, and as an up counter when set to 1. FBV1, FBV0: FBIAS (focus bias) counter voltage switching FCS BIAS count-up steps is decided by these bits. FBV1 0 0 1 1 TJD0: FBV0 0 1 0 1 Number of steps 1 2 4 8 The counter changes once for each sampling cycle of the focus servo filter. When MCK is 128Fs, the sampling frequency is 88.2kHz. When converted to FE input, 1 step is approximately 3.9 [mV]. This sets the tracking servo filter data RAM to 0 when switched from track jump to servo on only when SFJP = 1 (during surf jump operation). FPS1, FPS0: Gain setting when transferring data from the focus filter to the PWM block. TPS1, TPS0: Gain setting when transferring data from the tracking filter to the PWM block. This is effective for increasing the overall gain in order to widen the servo band. Operation when FPS1, FPS0 (TPS1, TPS0) = 00 is the same as usual (7-bit shift). However, 6dB, 12dB and 18dB can be selected independently for focus (tracking) by setting the relative gain to 0dB when FPS1, FPS0 (TPS1, TPS0) = 00. FPS1 0 0 1 1 CEIT: SJHD: INBK: FPS0 0 1 0 1 Relative gain 0dB +6dB +12dB +18dB TPS1 0 0 1 1 TPS0 0 1 0 1 Relative gain 0dB +6dB +12dB +18dB MT10: The CE pin input takes over the TE pin input by setting D3 to 1 (on). This means that the registers and filters for TE input are used for CE input. This holds the tracking filter output at the value when surf jump starts during surf jump. When D2 is 0 (off), the brake circuit masks the tracking filter output signal with TRKCNCL which is generated by taking the MIRR signal at the TZC edge. When D2 is set to 1 (on), the tracking filter input is masked instead of the output. The tracking filter input is masked when the MIRR signal is high by setting D1 to 1 (on). - 96 - CXD2548R $3B D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 0 D1 0 D0 0 SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 RINT SFOX, SFO2, SFO1: FOK slice level Default value: 011 (313mV) RFDC input conversion SFOX 0 0 0 0 1 1 1 1 SFO2 0 0 1 1 0 0 1 1 SFO1 0 1 0 1 0 1 0 1 Slice level 179mV 223 268 313 357 446 536 625 - 97 - CXD2548R SDF2, SDF1: DFCT slice level Default value: 10 (179mV) RFDC input conversion SDF2 0 0 1 1 SDF1 0 1 0 1 Slice level 89mV 134 179 224 MAX2, MAX1: DFCT maximum time Default value: 00 (no timer limit) MAX2 0 0 1 1 BTF: MAX1 0 1 0 1 DFCT maximum time No timer limit 2.00ms 2.36 2.72 Bottom hold double-speed count-up mode for MIRR signal generation On/off (default: off) On when set to 1. D2V2, D2V1: Peak hold 2 for DFCT signal generation Count-down speed setting Default value: 01 (0.492V/ms, 44.1kHz) [V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the operating frequency of the internal counter. D2V2 0 0 1 1 D2V1 0 1 0 1 Count-down speed [V/ms] 0.246 0.492 0.984 1.969 [kHz] 22.05 44.1 88.2 176.4 D1V2, D1V1: Peak hold 1 for DFCT signal generation Count-down speed setting Default value: 01 (3.938V/ms, 352.8kHz) [V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the operating frequency of the internal counter. D1V2 0 0 1 1 RINT: D1V1 0 1 0 1 Count-down speed [V/ms] 1.969 3.938 7.875 15.75 [kHz] 176.4 352.8 705.6 1411.2 This initializes the initial-stage registers of the circuits which generate MIRR, DFCT and FOK. - 98 - CXD2548R $3E D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 0 D3 0 D2 0 D1 D0 F1NM F1DM F3NM F3DM T1NM T1UM T3NM T3UM DFIS TLCD RFLP MIRI XT1D F1NM, F1DM: Quasi double accuracy setting for FCS servo filter first-stage On when set to 1; default = 0. F1NM: Gain normal F1DM: Gain down T1NM, T1UM: Quasi double accuracy setting for TRK servo filter first-stage On when set to 1; default = 0. T1NM: Gain normal T1UM: Gain up F3NM, F3DM: Quasi double accuracy setting for FCS servo filter third-stage On when set to 1; default = 0. Generally, the advance amount of the phase becomes large by partially setting the FCS servo third-stage filter which is used as the phase compensation filter to double accuracy. F3NM: Gain normal F3DM: Gain down T3NM, T3UM: Quasi double accuracy setting for TRK servo filter third-stage On when set to 1; default = 0. Generally, the advance amount of the phase becomes large by partially setting the TRK servo third-stage filter which is used as the phase compensation filter to double accuracy. T3NM: Gain normal T3UM: Gain up Note) Filter first- and third-stage quasi double accuracy settings can be set individually. See "FILTER Composition" at the end of this specification concerning quasi double-accuracy. DFIS: FCS hold filter input extraction node selection 0: M05 (Data RAM address 05); default 1: M04 (data RAM address 04) This command masks the TLC2 command set by D2 of $38 only when FOK is low. On when set to 1; default = 0 This command passes the signal obtained from the RFDC pin through the LPF (low-pass filter) before the built-in A/D converter. 0: LPF off; default 1: LPF on MIRR input switching. The MIRR signal can be input from an external source. When D1 is 0, the MIRR signal is used internally as usual. When D1 = 1, the MIRR signal can be input from an external source through the MIRR pin. The clock input from FSTI can be used as the master clock for the servo block regardless of the XTSL pin, XT2D and XT4D by setting D0 to 1. TLCD: RFLP: MIRI: XT1D: - 99 - CXD2548R $3F D15 0 AGG4: D14 D13 D12 D11 0 D10 D9 D8 D7 0 D6 ASFG D5 0 D4 D3 D2 D1 D0 AGG4 XT4D XT2D DRR2 DRR1 DRR0 LPAS SRO1 SRO0 AGHF COT2 This varies the amplitude of the internally generated sine wave using the AGGF and AGGT commands during AGC. When AGG4 = 0, the default is used. When AGG4 = 1, the setting is as shown in the table below. AGGF (MSB) 0 0 1 1 AGGT (LSB) 0 1 0 1 TE/FE input conversion 31 [mV] 63 [mV] 125 [mV] 250 [mV] These settings are the same as for both focus auto gain control and tracking auto gain control. XT4D, XT2D: MCK (digital servo master clock) frequency division setting This command forcibly sets the frequency division ratio to 1/2 or 1/4 when MCK is generated from the signal input to the FSTI pin. XT4D 0 0 1 XT2D 0 1 0 Frequency division ratio According to XTSL (default) 1/2 1/4 DRR2 to DRR0: Partially clears the Data RAM values (0 write). The following values are cleared when set to 1 (on) respectively; default = 0 DRR2: M08, M09, M0A DRR1: M00, M01, M02 DRR0: M00, M01, M02 only when LOCK = low Note) Set DRR1 and DRR0 for 50s or more. ASFG: When vibration detection is performed during anti-shock circuit operation, FCS servo filter is forcibly set to gain normal status. On when set to 1; default = 0 LPAS: Built-in analog buffer low-current consumption mode This mode reduces the total analog buffer current consumption for the VC, TE, SE and FE input by using a single operational amplifier. On when set to 1; default = 0 Note) When using this mode, firstly check whether each error signal is properly A/D converted using the SRO1 and SRO0 commands of $3F. SRO1, SRO0: These commands are used to output various data continuously externally which have been specified with the $39 command. (However, D15 (DAC) of $39 must be set to 1.) Digital output (SOCK, XOLT and SOUT) can be obtained from three specified pins by setting these commands to 1 respectively. The default is 0, 0. The output pins for each case are shown below. SRO1 = 1 SOCK XOLT SOUT XUGF GFS GTOP (See "Description of Data Readout" on the following page.) AGHF: COT2: This halves the frequency of the internally generated sine wave during AGC. The STZC signal is output from COUT by setting D0 to 1. (STZC: TZC signal generated by sampling the TE signal at 700kHz) - 100 - CXD2548R Description of Data Readout SOCK (5.6448MHz) XOLT (88.2kHz) *** *** *** *** SOUT MSB *** LSB MSB *** LSB 16-bit register for serial/parallel conversion SOUT LSB 16-bit register for latch LSB To the 7-segment LED * * * * * To the 7-segment LED * MSB SOCK CLK CLK MSB Data is connected to the 7-segment LED by 4-bits at time. This enables Hex display using four 7-segment LEDs. XOLT SOUT Serial data input D/A SOCK XOLT Clock input Latch enable input Analog output Offset adjustment, gain adjustment To an oscilloscope, etc. Waveforms can be monitored with an oscilloscope using a serial input-type D/A converter as shown above. - 101 - CXD2548R 4-19. List of Servo Filter Coefficients - 102 - CXD2548R Fix indicates that normal preset values should be used. - 103 - CXD2548R 4-20. FILTER Composition The internal filter composition is shown below. K and M indicate coefficient RAM and Data RAM address values respectively. FCS Servo Gain Normal fs = 88.2kHz FCS Hold Reg 2 FCS In Reg Sin ROM 2-1 DFCT K06 AGFON K06 K0F M03 Z-1 K08 K09 M04 Z-1 K0A 2-7 K0B 2-7 K0D K0C M05 Z-1 K0E FCS Hold Reg 1 M06 Z-1 K10 K11 FCS AUTO Gain M07 K13 27 FCS PWM FCS SRCH Note) Set the MSB bit of the K0B and K0D coefficients to 0. FCS Servo Gain Down fs = 88.2kHz FCS Hold Reg 2 FCS In Reg 2-1 DFCT K06 K2B M03 Z-1 K24 K25 M04 Z-1 K26 2-7 K27 2-7 K29 K28 M05 Z-1 K2A FCS Hold Reg 1 M06 Z-1 K2C K2D FCS AUTO Gain M07 K13 27 FCS PWM FCS SRCH Note) Set the MSB bit of the K27 and K29 coefficients to 0. - 104 - CXD2548R TRK Servo Gain Normal fs = 88.2kHz TRK Hold Reg TRK In Reg Sin ROM 2-1 DFCT K19 AGTON K19 TRK AUTO Gain M0B Z-1 K1A K1B M0C Z-1 K1C 2-7 K1D 2-7 K1F TRK JMP K1E M0D Z-1 K20 K21 M0E Z-1 K22 M0F K23 27 TRK PWM Note) Set the MSB bit of the K1D and K1F coefficients to 0. TRK Servo Gain Up 1 fs = 88.2kHz TRK Hold Reg TRK In Reg 2-1 DFCT K19 TRK AUTO Gain M0B Z-1 K1A K1B M0C Z-1 K3C K3D M0E Z-1 TRK JMP K3E M0F 27 K23 TRK PWM - 105 - CXD2548R TRK Servo Gain Up 2 fs = 88.2kHz TRK Hold Reg TRK In Reg 2-1 DFCT K19 TRK AUTO Gain M0B Z-1 K36 K37 M0C Z-1 K38 2-7 K39 2-7 K3B TRK JMP K3A M0D Z-1 K3C M0E Z-1 K3D K3E M0F K23 27 TRK PWM Note) Set the MSB bit of the K39 and K3B coefficients to 0. SLD Servo fs = 345Hz TRK AUTO Gain SLD In Reg 2-1 K00 M00 Z-1 K01 2-7 K02 2-7 K04 K03 M01 Z-1 SLD MOV K05 M02 27 K07 SLD PWM Note) Set the MSB bit of the K02 and K04 coefficients to 0. HPTZC/Auto Gain fs = 88.2kHz FCS In Reg TRK In Reg Sin ROM 2-1 AGFON 2-1 AGTON AGFON M08 Z-1 K14 K15 M09 Z-1 Slice TZC Reg M0A Z-1 K17 AUTO Gain Reg Slice - 106 - CXD2548R Anti Shock fs = 88.2kHz TRK In Reg 2-1 K12 M08 Z-1 M09 Z-1 K31 K16 2-7 M0A Z-1 K33 K35 Comp Anti Shock Reg K34 Note) Set the MSB bit of the K34 coefficient to 0. The comparator level is 1/16 the maximum amplitude of the comparator input. AVRG fs = 88.2kHz 2-1 VC, TE, FE, RFDC 2-7 M08 Z-1 AVRG Reg TRK Hold fs = 345Hz 2-1 K40 SLD In Reg M18 Z-1 K41 2-7 K42 2-7 M19 Z-1 K43 K45 TRK Hold Reg K44 Note) Set the MSB bit of the K42 and K44 coefficients to 0. FCS Hold fs = 345Hz FCS Hold Reg 1 K48 M10 Z-1 K49 2-7 K4A 2-7 M11 Z-1 K4B K4D FCS Hold Reg 2 K4C Note) Set the MSB bit of the K4A and K4C coefficients to 0. - 107 - CXD2548R FCS Servo Gain Normal; fs = 88.2kHz, during quasi double accuracy (Ex.: $3EAXX0) FCS Hold Reg 2 FCS In Reg Sin ROM 2-1 AGFON K06 DFCT K06 K0F M03 Z-1 81H 2-7 K08 2-7 K09 K0B 7FH K0A 2-7 2-7 K0D K0E K0C M04 Z-1 M05 Z-1 80H FCS Hold Reg 1 M06 Z-1 K10 2-7 K11 FCS AUTO Gain M07 K13 27 FCS PWM FCS SRCH 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy. Note) Set the MSB bit of the K0B and K0D coefficients during normal operation, and of the K08, K09 and K0E coefficients during quasi double accuracy to 0. FCS Servo Gain Down; fs = 88.2kHz, during quasi double accuracy (Ex.: $3E5XX0) FCS Hold Reg 2 FCS In Reg 2-1 DFCT K06 K2B M03 Z-1 81H 2-7 K24 2-7 K25 K27 7FH K26 2-7 2-7 K29 K2A K28 80H M04 Z-1 M05 Z-1 FCS Hold Reg 1 M06 Z-1 K2C 2-7 K2D FCS AUTO Gain M07 K13 27 FCS PWM FCS SRCH 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy. Note) Set the MSB bit of the K27 and K29 coefficients during normal operation, and of the K24, K25 and K2A coefficients during quasi double accuracy to 0. - 108 - CXD2548R TRK Servo Gain Normal; fs = 88.2kHz, during quasi double accuracy (Ex.: $3EXAX0) TRK Hold Reg TRK In Reg Sin ROM 2-1 AGTON K19 DFCT K19 TRK AUTO Gain M0B Z-1 81H 2-7 K1A 2-7 K1B K1D 7FH K1C 2-7 2-7 K1F K20 TRK JMP K1E M0C Z-1 M0D Z-1 80H 2-7 K21 27 TRK PWM M0E Z-1 K22 M0F K23 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy. Note) Set the MSB bit of the K1D and K1F coefficients during normal operation, and of the K1A, K1B and K20 coefficients during quasi double accuracy to 0. TRK Servo Gain up 1; fs = 88.2kHz, during quasi double accuracy (Ex.: $3EX5X0) TRK Hold Reg TRK In Reg 2-1 DFCT K19 TRK AUTO Gain M0B Z-1 81H 2-7 K1A 2-7 K1B K3C 7FH M0C Z-1 80H 2-7 K3D M0E Z-1 TRK JMP K3E M0F 27 K23 TRK PWM 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy. Note) Set the MSB bit of the K1A, K1B and K3C coefficients during quasi double accuracy to 0. - 109 - CXD2548R TRK Servo Gain up 2; fs = 88.2kHz, during quasi double accuracy (Ex.: $3EX5X0) TRK Hold Reg TRK In Reg 2-1 DFCT K19 TRK AUTO Gain M0B Z-1 81H 2-7 K36 2-7 K37 K39 7FH K38 2-7 2-7 K3B K3C TRK JMP K3A M0C Z-1 M0D Z-1 80H 2-7 K3D 27 TRK PWM M0E Z-1 K3E M0F K23 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy. Note) Set the MSB bit of the K39 and K3B coefficients during normal operation, and the K36, K37 and K3C coefficients during quasi double accuracy to 0. - 110 - CXD2548R 4-21. TRACKING and FOCUS Frequency Response TRACKING frequency response 40 NORMAL GAIN UP 30 90 20 G 0 10 -90 0 180 -10 2.1 10 100 f - Frequency [Hz] 1K -180 20K FOCUS frequency response 40 NORMAL GAIN DOWN 30 90 20 180 G 0 10 -90 0 -10 2.1 10 100 f - Frequency [Hz] 1K -180 20K - 111 - - Phase [degree] G - Gain [dB] - Phase [degree] G - Gain [dB] [5] Application Circuit 5-1. Application Circuit VC LOCK COUT +5V SSTP SLED SPDL GND 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 C4M Driver Circuit ADIO C4M MDS FSTI MDP VDD2 VSS2 XTSL TES3 TEST SSTP FSTO LOCK FFDR TRDR TFDR FRDR SFDR TES2 IGEN ADIO RFC COUT SRDR WDCK 86 VDD3 FE 55 VC 54 ASYO 53 ASYI 52 BIAS 51 RFAC 50 AVDD4 49 CLTV 48 AVSS4 47 FILI 46 FILO 45 PCO 44 VCTL 43 V16M 42 VCKI 41 VPCO2 40 VPCO1 39 VDD1 38 FOK 37 DFCT 36 MIRR 35 ATSK 34 DOUT 33 VSS1 32 MNT3 31 DOUT DFCT MIRR V16M VC 87 88 LRCKI 89 PCMD 90 91 BCK 92 BCKI 93 EMPH 94 EMPHI 95 VSS3 96 AVSS1 97 AVDD1 98 AOUT1 99 AIN1 100 LOUT1 101 AVSS1 102 XVDD 103 XTAI 104 XTAO 105 XVSS 106 AVSS2 107 LOUT2 108 AIN2 109 AOUT2 110 AVDD2 111 AVSS2 PCMDI LRCK 85 WDCK AVDD3 AVSS3 RFDC CE TE SE 56 FG TD TG FD LDON VCC GND RFO FZC FE TE CE VC RMUT1 SQCK CLOK SYSM EXCK XLAT SPOA SBSO DATA XLON VDD0 SCLK PWMI XPCK GFS RFCK CKOUT SENS ACDT XUGF LMUT2 SQSO XRST GTOP 1 2 3 7 4 8 5 6 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 WFCK EXCK SBSO XLON RFCK WFCK GTOP XUGF RMUT1 LMUT2 XPLCK C2PO C2PO CKOUT MUTE SQCK SQSO SENS SCLK DATA XLAT CLOK XRST PWMI GFS SCOR FOK LDON VDD GND XRAOF XROF SCORM - 112 - 112 VSS0 MNT1 30 NT0 29 MNT3 MNT1 MNT0 GND CXD2548R Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. CXD2548R Package Outline Unit: mm 112PIN LQFP(PLASTIC) 22.0 0.2 20.0 0.1 84 85 57 56 1.7MAX 1.4 0.1 S 0.1 S B A 112 1 28 0.65 0.32 0.05 0.13 M S 29 0.1 0.05 0.6 0.15 0.32 0.05 0 -- 10 DETAIL A (0.5) DETAIL B (0.125) 0.25 (0.3) 0.145 0.03 (21.0) PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-112P-L01 LQFP112-P-2020 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER ALLOY 1.3g - 113 - |
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