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 N-CHANNEL 60V - 0.020 - 40A DPAK Zener-Protected STripFETTM II POWER MOSFET
TYPE STD40NF06LZ
s s s s s
STD40NF06LZ
VDSS 60 V
RDS(on) < 25 m
ID 40 A
s
TYPICAL RDS(on) = 0.020 100% AVALANCHE TESTED LOW GATE CHARGE LOGIC LEVEL GATE DRIVE SURFACE-MOUNTING DPAK (TO-252) POWER PACKAGE IN TAPE & REEL (SUFFIX "T4") BUILT-IN ZENER DIODES TO IMPROVE ESD PROTECTION UP TO 2kV
3 1
DPAK TO-252 (Suffix "T4")
DESCRIPTION This Power MOSFET is the latest development of STMicroelectronis unique "Single Feature SizeTM" strip-based process. The resulting transistor shows extremely high packing density for low onresistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. APPLICATIONS s SINGLE-ENDED SMPS IN MONITOTS, COMPUTER AND INDUSTRIAL APPLICATION s WELDING EQUIPMENT s AUTOMOTIVE ABSOLUTE MAXIMUM RATINGS
Symbol VDS VDGR VGS ID ID IDM(*) Ptot VESD(G-S) dv/dt(1) EAS(2) Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuous) at TC = 25C Drain Current (continuous) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Derating Factor Gate-source ESD(HBM-C=100pF, R=15k) Peak Diode Recovery voltage slope Single Pulse Avalanche Energy Storage Temperature Max. Operating Junction Temperature
INTERNAL SCHEMATIC DIAGRAM
Value 60 60 16 40 28 160 100 0.67 2.5 9 450 -55 to 175
(1)ISD 40A, di/dt 100A/s, VDD V(BR)DSS, Tj T JMAX. (2) Starting Tj = 25 oC ID = 20A VDD = 45V
Unit V V V A A A W W/C kV V/ns mJ C
(*) Pulse width limited by safe operating area. October 2002
.
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STD40NF06LZ
THERMAL DATA
Rthj-case Rthj-PCB Tl Thermal Resistance Junction-case Thermal Resistance Junction-PCB (#) Maximum Lead Temperature For Soldering Purpose Max Max 1.5 50 300 C/W C/W C
(#) When Mounted on 1 inch2 FR-4 board, 2 oz Cu.
ELECTRICAL CHARACTERISTICS (Tcase = 25 C unless otherwise specified) OFF
Symbol V(BR)DSS IDSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 A, VGS = 0 VDS = Max Rating VDS = Max Rating TC = 125C VGS = 16 V Min. 60 1 50 10 Typ. Max. Unit V A A A
IGSS
ON (*)
Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS VGS = 5 V VGS = 10 V ID = 250 A ID = 20 A D = 20 A Min. 1 0.030 0.025 Typ. Max. Unit V
DYNAMIC
Symbol gfs (*) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS = 15 V ID = 20 A Min. Typ. 25 1360 302 115 Max. Unit S pF pF pF
VDS = 25V, f = 1 MHz, VGS = 0
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STD40NF06LZ
ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON
Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions ID = 20 A VDD = 30 V RG = 4.7 VGS = 4.5 V (Resistive Load, Figure 3) VDD =48 V ID =40 A VGS=10V Min. Typ. 17 75 54 11 12 Max. Unit ns ns nC nC nC
SWITCHING OFF
Symbol td(off) tf Parameter Turn-off Delay Time Fall Time Test Conditions ID = 20 A VDD = 30V RG = 4.7, VGS = 4.5 V (Resistive Load, Figure 3) Min. Typ. 38 23 Max. Unit ns ns
SOURCE DRAIN DIODE
Symbol ISD ISDM (*) VSD (*) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 40A VGS = 0 66 142 4.3 Test Conditions Min. Typ. Max. 40 160 1.6 Unit A A V ns nC A
di/dt = 100A/s ISD = 40 A VDD = 30 V Tj = 150C (see test circuit, Figure 5)
(*)Pulsed: Pulse duration = 300 s, duty cycle 1.5 % (*)Pulse width limited by safe operating area.
Safe Operating Area
Thermal Impedance
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Output Characteristics Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
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STD40NF06LZ
Normalized Gate Threshold Voltage vs Temperature Normalized on Resistance vs Temperature
Source-drain Diode Forward Characteristics
Normalized Breakdown Voltage vs Temperature.
.
.
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STD40NF06LZ
Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times
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STD40NF06LZ
TO-252 (DPAK) MECHANICAL DATA
mm MIN. A A1 A2 B B2 C C2 D E G H L2 L4 0.6 2.2 0.9 0.03 0.64 5.2 0.45 0.48 6 6.4 4.4 9.35 0.8 1 0.023 TYP. MAX. 2.4 1.1 0.23 0.9 5.4 0.6 0.6 6.2 6.6 4.6 10.1 MIN. 0.086 0.035 0.001 0.025 0.204 0.017 0.019 0.236 0.252 0.173 0.368 0.031 0.039 inch TYP. MAX. 0.094 0.043 0.009 0.035 0.212 0.023 0.023 0.244 0.260 0.181 0.397
DIM.
H
A
C2
C
DETAIL "A"
A1
L2
D DETAIL "A"
B
=
=
3
B2
=
=
G
E
2
L4
1
=
=
A2
0068772-B
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STD40NF06LZ
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics (R) 2001 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
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