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FEATURES Single +5 V Supply Receive Channel Differential or Single-Ended Analog Inputs Auxiliary Set of Analog I & Q Inputs Two Sigma-Delta A/D Converters Choice of Two Digital FIR Filters Root-Raised-Cosine Rx Filters, = 0.35 Brick Wall FIR Rx Filters On-Chip or User Rx Offset Calibration ADC Sampling Vernier Three Auxiliary DACs On-Chip Voltage Reference Low Active Power Dissipation, Typical 45 mW Low Sleep Mode Power Dissipation, <50 W 28-Pin SSOP APPLICATIONS American TIA Digital Cellular Telephony American Analog Cellular Telephony Digital Baseband Receivers GENERAL DESCRIPTION The AD7013 is a complete low power, CMOS, TIA IS-54 baseband receive port with single +5 V power supply. The part is
CMOS TIA IS-54 Baseband Receive Port AD7013
designed to perform the baseband conversion of I and Q waveforms in accordance with the American (TIA IS-54) Digital Cellular Telephone system. The receive path consists of two high performance sigma-delta ADCs, each followed by a FIR digital filter. A primary and auxiliary set of IQ differential analog inputs are provided, where either can be selected as inputs to the sigma-delta ADCs. Also, a choice of two frequency responses are available for the receive FIR filters; a Root-Raised-Cosine filter for digital mode or a brick wall response for analog mode. Differential analog inputs are provided for both I and Q channels. On-chip calibration logic is also provided to remove either on-chip offsets or remove system offsets. A 16-bit serial interface is provided, interfacing easily to most DSPs. The receive path also provides a means to vary the sampling instant, giving a resolution to 1/32 of a symbol interval. The auxiliary section provides two 8-bit DACs and one 10-bit DAC for functions such as automatic gain control (AGC), automatic frequency control (AFC) and power amplifier control. As it is a necessity for all digital mobile systems to use the lowest possible power, the device has receive and auxiliary power down options. The AD7013 is housed in a space efficient 28-pin SSOP (Shrink Small Outline Package).
FUNCTIONAL BLOCK DIAGRAM
MCLK DGND VDD AUX DAC1 AUX DAC2 AUX DAC3 FS ADJUST VAA AGND
DxCLK DATA IN FRAME IN MODE1 FRAME OUT SERIAL INTERFACE
10-BIT AUX DAC
8-BIT AUX DAC
8-BIT AUX DAC
FULL-SCALE ADJUST AGND AGND
LATCH
LATCH
LATCH
AD7013
1.23V REFERENCE ANALOG MODE FIR DIGITAL FILTER ROOT RAISED COSINE FIR DIGITAL FILTER BYPASS IRx - MODULATOR SWITCHED CAP FILTER IRx MUX AUX IRx AUX IRx QRx OFFSET ADJUST ANALOG MODE FIR DIGITAL FILTER ROOT RAISED COSINE FIR DIGITAL FILTER - MODULATOR SWITCHED CAP FILTER QRx MUX AUX QRx AUX QRx
Rx CLK RECEIVE CHANNEL SERIAL INTERFACE
OFFSET ADJUST
Rx DATA Rx FRAME
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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AD7013-SPECIFICATIONS
Parameter RECEIVE SECTION ADC SPECIFICATION Number of Input Channels 4
1
(VAA = VDD = +5 V 10%; AGND = DGND = 0 V; fMCLK = 6.2208 MHz; TA = TMIN to TMAX, unless otherwise noted)
Units Test Conditions/Comments
AD7013A
(IRx-IRx) and QRx-QRx); CR12 = 0 (AUX IRx-AUX IRx) and (AUX QRx-AUX QRx); CR12 = 1 Bits Volts p-p Volts Volts Volts min/max Volts min/max % mV mV
Number of ADC Channels Resolution ADC Signal Range Differential Signal Range Single-Ended Signal Range VBIAS Input Range Accuracy Accuracy Bias Offset Error
2 15 2.6 VBIAS 0.65 VBIAS 1.3 0.65 to (VAA-0.65) 1.3 to (VAA-1.3) 7.5 7.5 55
Measured Using an Input Sine Wave of 3 kHz For Both Noninverting and Inverting Analog Inputs For Noninverting Analog Inputs; Inverting Analog Inputs = VBIAS Differential Single-Ended
Autocalibration; VBIAS = min/max User Calibration; I & Q Offset Adjust Registers Equal to Zero Measured Using an Input Sine Wave of 3 kHz with Both Noninverting and Inverting Inputs Tied Together Digital Mode Filter; CR11 = 0 Analog Mode Filter; CR11 = 1 Digital Mode Filter; CR11 = 0 Analog Mode Filter; CR11 = 1 MCLK = 6.2208 MHz/5.12 MHz; MCLK/4 MCLK = 6.2208 MHz/5.12 MHz; 4 x Sampling of the Symbol Rate, MCLK/64 MCLK = 6.2208 MHz/5.12 MHz; 2 x Sampling of the Symbol Rate, MCLK/128 MCLK = 6.2208 MHz
Dynamic Specifications CMRR
-40
dB typ
Dynamic Range SNR2
Input Sampling Rate Output Word Rate
70 65 65 68 60 63 1.5552/1.28 97.2/80 48.6/40
dB typ dB typ dB min dB typ dB min dB typ MHz kHz kHz
RECEIVE DIGITAL FILTERS Digital Mode Root-Raised-Cosine Settling Time Absolute Group Delay Frequency Response 0-7.8975 kHz 11.9 kHz 16.4025 kHz > 30 kHz Analog Mode Brick Wall Filter Settling Time Absolute Group Delay Frequency Response 0-8 kHz 11.4 kHz 15 kHz >17 kHz
= 0.35 329.2 164.6 0.05 -3.0 -19 -66
s s dB max dB dB dB max MCLK = 5.12 MHz
400 200 0 to -0.5 -3.0 -24 -68
s s dB max dB dB dB max
TIA IS-54 RECEIVE SPECIFICATIONS Error Vector Magnitude 3 Error Offset Magnitude3
2 1
% rms typ % rms typ
Measured Using a Full-Scale Input
-2-
REV. A
AD7013
Parameter AUXILIARY SECTION Resolution DC Accuracy Integral Differential Zero Code Leakage Gain Error Output Full-Scale Current Output Impedance4 Output Voltage Compliance Coding Power Down Option REFERENCE SPECIFICATIONS VREF Reference Accuracy Reference Impedance LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage POWER SUPPLIES VDD IDD5 All Sections Active AUX DAC1 AUX DAC2 AUX DAC3 10 8 8 3 -1.5/+4 500 7.5 566 1 1 500 7.5 280 2 2.6 Binary Yes 1.23 5 20 1 1 500 7.5 280 Bits LSBs max LSBs max nA max % max A M typ Volts max AD7013A Units Test Conditions/Comments
AUX DAC2 & AUX DAC3 Guaranteed Monotonic
RSET = 18 k
Volts typ % max k typ
VDD-0.9 0.9 10 10
V min V max A max pF max |IOUT| 40 A |IOUT| 1.6 mA
VDD-0.4 0.4
V min V max
4.5/5.5 10.5 9 8.6
VMIN/VMAX mA max mA typ mA max CR14 = CR15 = CR16 = CR17 = 1 MCLK = 6.2208 MHz; 80 pF Load on DxCLK CR14 = 1; CR15 = CR16 = CR17 = 0 MCLK = 6.2208 MHz; 80 pF Load on DxCLK CR14 = 0; CR15 = CR16 = CR17 = 1; MCLK Inactive, MCLK = 0 V CR14 = CR15 = CR16 = 0; CR17 = 1; MCLK Inactive, MCLK = 0 V CR14 = CR15 = CR16 = CR17 = 0 MCLK = 6.2208 MHz; 80 pF Load on DxCLK MCLK =100 kHz; 80 pF Load on DxCLK MCLK Inactive, MCLK = 0 V
ADCs Active Only
AUX DACs Active Only 10-Bit AUX DAC Active All Sections Powered Down6
2.2 1.6 2
mA max mA max mA max
30 10
A typ A max
NOTES 1 Operating temperature ranges as follows: A version: -40C to +85C. 2 SNR calculation includes noise and distortion components. 3 See Terminology. 4 Sampled tested only. 5 Measured while the digital inputs are static and equal to 0 V or V DD. 6 With all sections powered down, I DD is proportional to the capacitive load on DxCLK. For example, I DD is typically 1.7 mA with 80 pF load and 600 A with 10 pF load. Specifications subject to change without notice.
REV. A
-3-
AD7013
TERMINOLOGY Sampling Rate This is the rate at which the modulators on the receive channels sample the analog input. Output Rate This is the rate at which data words are made available at the RxDATA pin. Integral Nonlinearity This is the maximum deviation from a straight line passing through the endpoints of the DAC or ADC transfer function. Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the DAC or ADC. Dynamic Range Dynamic Range is the ratio of the maximum rms input signal to the rms noise of the converter, expressed logarithmically, in decibels (dB = 20 log10 [ratio]). Signal to (Noise + Distortion) Ratio This is the measured ratio of signal to (noise + distortion) at the output of the receive channel. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f S/2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for a sine wave is given by: Signal to (Noise + Distortion) = (6.02N + 1.76) dB Settling Time This is the digital filter settling time in the AD7013 receive section. Bias Offset Error This is the amount of offset in the receive channel ADC when the differential inputs are tied together. Receive Error Vector Magnitude This is a measure of the rms signal error vector introduced by the receive Root-Raised Cosine digital filter. This is measured by applying an ideal transmit signal (i.e., an ideal /4 DQPSK modulator and an ideal transmit Root-Raised Cosine filter) to the receive channel and measuring the resulting rms error vector. Offset Vector Magnitude This is a measure of the offset vector introduced by the AD7013 as illustrated in the figure below. The offset vector is calculated so as to minimize the rms error vector for each of the constellation points.
Q ERROR VECTOR
ABSOLUTE MAXIMUM RATINGS 1
(TA = +25C unless otherwise noted)
VAA, VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +0.3 V Digital I/O Voltage to DGND . . . . . . . . . . . -0.3 V to VDD +0.3 V Analog I/O Voltage to AGND . . . . . . . . . . . -0.3 V to VDD +0.3 V Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . . . . -65C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . +150C SSOP JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . +122C/W Lead Temperature Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220C
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions extended periods may affect device reliability.
PIN CONFIGURATION
VAA IRx AUX IRx IRx AUX IRx QRx AUX QRx QRx AUX QRx AGND MODE1 Rx FRAME Rx DATA Rx CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 BYPASS 27 AGND 26 FS ADJUST 25 AGND 24 AUX DAC1 23 AUX DAC2 22 AUX DAC3 TOP VIEW (Not to Scale) 21 VDD 20 MCLK 19 DxCLK 18 DATA IN 17 FRAME IN 16 DGND 15 FRAME OUT
AD7013
ORDERING GUIDE Model AD7013ARS
*RS = SSOP.
Temperature Range -40C to +85C
Package Option* RS-28
SIGNAL VECTOR OFFSET VECTOR
I
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this device features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
REV. A
AD7013
PIN FUNCTION DESCRIPTIONS SSOP Pin Number Mnemonic Function Positive Power Supply for Analog section. A 0.1 F decoupling capacitor should be connected between this pin and AGND. Positive Power Supply for Digital section. A 0.1 F decoupling capacitor should be connected between this pin and DGND. Both V AA and VDD should be externally tied together. Analog Ground. Digital Ground. Both AGND and DGND should be externally tied together. Reference Decoupling Output. A 10 nF decoupling capacitor should be connected between this pin and AGND. Differential Analog Inputs for the I receive channel. These are the primary receive analog inputs and are selected by setting CR12 to a zero in the command register. Differential Analog Inputs for the Q receive channel. These are the primary receive analog inputs and are selected by setting CR12 to a zero in the command register. Auxiliary Differential Analog Inputs for the I receive channel. The Auxiliary inputs are selected by setting CR12 to a one in the command register. Auxiliary Differential Analog Inputs for the Q receive channel. The Auxiliary inputs are selected by setting CR12 to a one in the command register. Analog output from the 10-bit auxiliary DAC. Analog outputs from the 8-bit auxiliary DACs. An external resistor is connected from this pin to ground to determine the fullscale current for AUX DAC1, AUX DAC2, and AUX DAC3. Master Clock, Digital Input. When operating in IS-54 Digital mode this pin should be driven by a 6.2208 MHz CMOS compatible clock source and 5.12 MHz clock source for Analog Mode. Transmit Clock, Digital Output. This is a continuous clock equal to MCLK/2 which can be used to clock the serial port of a DSP. Digital Input. This is used to frame the clocking in of 16-bit words for the control registers serial interface. Digital Input. Transmit Serial Data, digital input. This pin is used to clock in data for the serial interface on the rising edge of DxCLK. Digital Output. This output represents a buffered version of FRAME IN and is controlled by the MODE1 pin. This pin can be used to daisy chain the FRAME IN signal. Digital Input. This pin determines the state of FRAME OUT. When MODE1 is high, FRAME IN is buffered and made available on FRAME OUT. When MODE1 is low, FRAME OUT is in 3-STATE. Output Clock for the receive section interface. Synchronization output for framing I and Q data at the receive interface. Receive Data, digital output. I and Q data are available at this pin via a 16-bit serial interface. Data is valid on the falling edge of RxCLK. I and Q data are clocked out as two 16-bits words, with the I word being clocked first. The last bit in each 16-bit word is a I/Q flag bit, indicating whether that word is an I word or a Q word.
POWER SUPPLY 1 VAA 21 VDD
10, 25, 27 16
AGND DGND
ANALOG SIGNAL AND REFERENCE 28 BYPASS 2, 4 6, 8 3, 5 7, 9 24 3, 22 26 IRx, IRx QRx, QRx AUX IRx, AUX IRx AUX QRx, AUX QRx AUX DAC1 AUX DAC2, AUX DAC3 FS ADJUST
SERIAL INTERFACE AND CONTROL 20 MCLK
19 17 18 15
DxCLK FRAME IN DATA IN FRAME OUT
11
MODE1
RECEIVE INTERFACE AND CONTROL 14 RxCLK 12 RxFRAME 13 RxDATA
REV. A
-5-
AD7013 CONTROL SERIAL INTERFACE TIMING1
Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 Limit at TA = -40C to +85C 160 65 65 20 60 2t1 t1-20 t1-20 25 10 16t5 25 10 0 25 25 25 Units ns min ns min ns min ns min ns max ns ns min ns min ns min ns min ns min ns min ns min ns min ns max ns max ns max
(VAA = +5 V 10%; VDD = +5 V 10%; AGND = DGND =0 V, fMCLK = 6.2208 MHz; TA = TMIN to TMAX, unless otherwise noted)
Description MCLK Cycle Time MCLK High Time MCLK Low Time MCLK Rising Edge to DxCLK Rising Edge Propagation Delay DxCLK Cycle Time DxCLK Minimum High Time DxCLK Minimum Low Time DxCLK Rising Edge to FRAME IN Setup Time DxCLK Rising Edge to FRAME IN Hold Time FRAME IN Cycle Time DxCLK Rising Edge to DATA IN Setup Time DxCLK Rising Edge to DATA IN Hold Time FRAME IN Rising Edge to FRAME OUT Rising Edge Propagation Delay MODE1 Low to FRAME OUT 3-STATE MODE1 High to FRAME OUT Active
NOTE 1 t14 is derived from the measured time taken by the FRAME OUT pin to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 80 pF capacitor. This means that the time quoted in the Timing Characteristics is the
1.6mA
IOL
TO OUTPUT PIN CL 50pF 200A IOH
+2.1V
Figure 1. Load Circuit for Digital Outputs
t1
MxCLK (I)
t2
t3
t4
DxCLK (O)
t5
t6
t9 t8
FRAME IN (I)
t7 t10 t12 t11
DATA IN (I)
DB9
DB8 DATA
DB1
DB0
A3 ADDRESS
A0
S1
S0
IGNORED
t13
FRAME OUT (O)
t14
3 - STATE
t15
MODE1 (I) NOTE: (O) INDICATES AN OUTPUT, (I) INDICATES AN INPUT, MODE1 = LOGIC HIGH
Figure 2. 16-Bit Serial Interface for Writing to the AD7013 Internal Registers
-6-
REV. A
AD7013 RECEIVE SECTION TIMING
Parameter t16 10240t1 6144t1 30 85 2t1 t1-20 t1-20 -10 10 32t1 2t1 -10 10 10t1 64t1 ns max ns max ns min ns max ns ns min ns min ns min ns max ns ns ns min ns max ns min ns max Limit at TA = -40C to +85C
(VAA = +5 V 10%; VDD = +5 V 10%; AGND = DGND = 0 V,fMCLK = 6.2208 MHz; TA = TMIN to TMAX, unless otherwise noted)
Description Power-Up Receive to RxCLK CR13 = 0, Rx Offset Autocalibration On CR13 = 1, Rx Offset Autocalibration Off Propagation Delay from MCLK Rising Edge to RxCLK Rising Edge RxCLK Cycle Time; CR10 = 1; 4x Sampling of the Symbol Rate RxCLK High Pulse Width; CR10 = 1 RxCLK Low Pulse Width; CR10 = 1 RxCLK Rising Edge to RxFRAME Rising Edge RxFRAME Cycle Time; CR10 = 1 RxFRAME High Pulse Width; CR10 = 1 RxDATA Valid After RxCLK Rising Edge DxCLK Rising Edge to Last Falling Edge RxCLK
Units
t17 t18 t19 t20 t21 t22 t23 t24 t25
MCLK (I) The last DxCLK edge which is used to write to Command Reg One, setting CR14 to One The last DxCLK edge which is used to write to Command Reg One, setting CR14 to Zero
t 25
DxCLK (O)
CR14
t16
RxCLK (O)
t17
t18
t19
t21
RxFRAME (O)
t 22
t20
t23 t24
RxDATA (O) I MSB I LSB 1 Q MSB Q LSB 0 I MSB I LSB 1 Q MSB Q LSB 0
15-BIT I WORD
I/Q FLAG BIT
15-BIT Q WORD
I/Q FLAG BIT
FINAL IQ PAIR PRIOR TO POWER DOWN
NOTE: (O) INDICATES AN OUTPUT, (I) INDICATES AN INPUT
Figure 3. Receive Serial Interface Timing with 4x Sampling of the Symbol Rate (CR10 = 1)
REV. A
-7-
AD7013 RECEIVE SECTION TIMING
Parameter t26 10240t1 6144t1 30 85 4t1 2t1-20 2t1-20 -10 +10 64t1 4t1 -10 +10 12t1 128t1 2t1 + 20 2t1 + 20 ns max ns max ns min ns max ns ns min ns min ns min ns max ns ns ns min ns max ns min ns max ns max ns max Limit at TA = -40C to +85C
(VAA = +5 V 10%; VDD = +5 V 10%; AGND = DGND =0 V, fMCLK = 6.2208 MHz; TA = TMIN to TMAX, unless otherwise noted)
Units
Description Power up Receive to RxCLK CR13 = 0; Rx Offset Autocalibration On CR13 = 1; Rx Offset autocalibration Off Propagation Delay from MCLK Rising Edge to RxCLK Rising Edge RxCLK Cycle Time; CR10 = 0; 2x Sampling of the Symbol Rate RxCLK High Pulse Width; CR10 = 0 RxCLK Low Pulse Width; CR10 = 0 RxCLK Rising Edge to RxFRAME Rising Edge RxCLK to RxFRAME Propagation Delay RxFRAME Cycle Time; CR10 = 0 RxFRAME High Pulse Width; CR10 = 0 Propagation Delay from RxCLK Rising Edge to RxDATA Valid DxCLK Rising Edge to Last Falling Edge of RxCLK 3-State to Receive Channel Valid Receive Channel to 3-State Relinquish Time
t27 t28 t29 t30 t31 t32 t33 t34 t35 t36 t37
1
t37 is derived from the measured time taken by the receive channel outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 80 pF capacitor. This means that the time quoted in the Timing Characteristics is the true relinquish time of the part and as such is independent of external loading capacitance.
MCLK (I) The last DxCLK edge which is used to write to Command Reg One, setting CR14 to One The last DxCLK edge which is used to write to Command Reg One, setting CR14 to Zero
t 35
DxCLK (O)
CR14
t26
RxCLK (O)
t27
t 28
t29
t31
RxFRAME (O)
t 32
t30
t34
RxDATA (O) 1MSB 1LSB
t 33
1 Q MSB Q LSB 0
15-BIT I WORD NOTE: (O) INDICATES AN OUTPUT, (I) INDICATES AN INPUT
I/Q FLAG BIT
15-BIT I WORD
I/Q FLAG BIT
Figure 4. Receive Serial Interface Timing with 2 x Sampling of the Symbol Rate (CR10 = 0)
DxCLK (O)
The last DxCLK edge which is used to write to Command Reg One, setting CR14 to Zero
The last DxCLK edge which is used to write to Command Reg One, setting CR14 to One
CR18
t36
RxCLK (O) RxFRAME (O) RxDATA (O) 3- STATE ACTIVE
t 37
3- STATE
NOTE: (O) INDICATES AN OUTPUT, (I) INDICATES AN INPUT
Figure 5. Receive Serial Interface 3-State Timing
-8-
REV. A
AD7013
Rx SAMPLING VERNIER IRx OFFSET ADJUST QRx OFFSET ADJUST COMMAND REGISTER AUX DAC1 AUX DAC2 AUX DAC3
6-BIT LOAD DATA BUFFER
DATA IN DB9 - DB0 MSB A3 - A0 16-BIT SERIAL WORD S1, S0 LSB
Figure 6. AD7013 Registers
Table I. Description and Address Map for AD7013 Internal Registers Register Name COMMAND Address A2 A1 0 1 Register Size 9 Bits Reset State All Zeros
A3 0
A0 0
Description The COMMAND register is used to select various operating modes of the AD7013. A detailed description of the COMMAND register is given in Table II. The VERNIER register allows additional group delay to be introduced into the I and Q ADCs. This provides a means to vary the ADC sampling instant. The contents of the IRx OFFSET register are substracted from the I channel ADC word. When autocalibration is selected, this register is automatically loaded by the AD7013 at the beginning of a normal operation. When user calibration is selected, this register can be externally loaded with a twos complement offset 10-bit word to be subtracted from subsequent ADC samples. The contents of the QRx OFFSET register are substracted from the Q channel ADC word. When auto calibration is selected, this register is automatically loaded by the AD7013 at the beginning of a normal operation. When user calibration is selected this register can be externally loaded with a twos complement offset 10-bit word to be subtracted from subsequent ADC samples. The 10-bit auxiliary DAC current output is determined by this register. The output current is equal to {AUX DAC1 FULL SCALE * N/210} where N is the 10-bit word contained in the AUX DAC1 register and AUX DAC1FULL SCALE is determined by the value of R SET connected between FSADJUST and AGND. The 8-bit auxiliary DAC current output is determined by this register. The output current is equal to {AUX DAC1 FULL SCALE * N/28} where N is the 8-bit word contained in the AUX DAC2 register and AUX DAC2FULL SCALE is determined by the value of RSET connected between FS ADJUST and AGND. The 8-bit auxiliary DAC current output is determined by this register. The output current is equal to {AUX DAC3 FULL SCALE * N/28} where N is the 8-bit word contained in the AUX DAC3 register and AUX DAC3FULL SCALE is determined by the value of R SET connected between FS ADJUST and AGND. When this address in selected, all of the internal registers are initialized to their reset state. When this address is used, a special loading sequence, as shown in Table IV, is used to write to any of the internal registers. No Action. No Action.
VERNIER
0
1
0
0
4 Bits
All Zeros
IRx OFFSET
0
1
0
1
10 Bits
All Zeros
QRx OFFSET 0
1
1
0
10 Bits
All Zeros
AUX DAC1
0
1
1
1
10 Bits
All Zeros
AUX DAC2
1
0
0
0
8 Bits
All Zeros
AUX DAC3
1
0
0
1
8 Bits
All Zeros
RESET 6-Bit LOAD N/A N/A
0 0 0 1
0 0 0 1
0 1 0 1
1 1 0 1
N/A N/A N/A N/A
N/A N/A N/A N/A
REV. A
-9-
AD7013
COMMAND REGISTER ONE
MSB CR19 CR18 CR17 CR16 CR15 CR14 CR13 CR12 CR11 LSB CR10
AUX DAC1
MSB D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB D0
Rx SAMPLING VERNIER REGISTER
MSB RESERVED V3 V2 V1 LSB V0
AUX DAC2 AUX DAC3
MSB D7 D6 D5 D4 D3 D2 D1
LSB D0
Figure 7. Internal AD7013 Registers
Table II. Command Register One CR10 CR11 =0 =1 =0 Low ADC sample rate. The sample rate of the receive ADCs are equal to 2x the symbol rate or equal to MCLK/128. High ADC sample rate. The sample rate of the ADCs are equal to 4x the symbol rate or equal to MCLK/64. RRC Receive FIR filter. This selects the root-raised consine filter response for the receive sigma-delta ADCs. This is used to match the transmit RRC filter as required by the IS-54 standard. The frequency response is shown in Figure 16. Analog Mode FIR filter. This selects a filter response which has a sharper roll-off than the RRC FIR filter and the frequency response has also been scaled to operate at a master clock frequency of 5.12 MHz. This allows the sampling rate of the receive ADCs to be a multiple of 10 kHz as required for analog cellular. The frequency response is shown in Figure 17. Primary ADC inputs. This selects IRx and IRx as the I channel inputs and QRx and QRx as the Q channel inputs. Auxiliary ADC inputs. This selects AUX IRx and AUX IRx as the I channel inputs and AUX QRx and AUX QRx as the Q channel inputs. Auto ADC offset calibration. If auto calibration is selected, then an offset word for both ADCs is calculated each time the receive ADCs are brought out of sleep mode. This allows ADC offsets within the AD7013 to be automatically calibrated out. User ADC offset calibration. When user calibration is selected, then contents of the offset registers are not updated by the AD7013 when brought out of sleep mode. This allows the user to load the offset register externally thereby allowing the AD7013 to also calibrate out external offsets. Receive ADC sleep mode. This enters the I and Q ADCs into a low power sleep mode after outputting the current IQ sample. Receive ADC active mode. This activates the receive ADCs for normal operation. 8-Bit AUX DAC3 sleep mode. This enters the 8-bit auxiliary DAC into a low power sleep mode. 8-Bit AUX DAC3 active mode. This activates the 8-bit auxiliary DAC for normal operation. 8-Bit AUX DAC2 sleep mode. This enters the 8-bit auxiliary DAC into a low power sleep mode 8-Bit AUX DAC2 active mode. This activates the 8-bit auxiliary DAC for normal operation. 10-Bit AUX DAC1 sleep mode. This enters the 10-bit auxiliary DAC into a low power sleep mode. 10-Bit AUX DAC1 active mode. This activates the 10-bit auxiliary DAC for normal operation. 3-State Enable. This enables the 3-state buffers on the receive serial interface. 3-State Disable. This disables the 3-state buffers on the receive serial interface, entering the serial interface into 3-state. No Action.
=1
CR12
=0 =1
CR13
=0
=1
CR14
=0 =1
CR15 CR16 CR17 CR18
=0 =1 =0 =1 =0 =1 =0 =1 =X
CR19
-10-
REV. A
AD7013
RECEIVE SECTION The receive section consists of I and Q receive channels, each comprising of a simple switched-capacitor filter followed by a 15-bit sigma-delta ADC. The data is available on a 16-bit serial interface, interfacing easily to most DSPs. On-board digital filters, which form part of the sigma-delta ADCs, also perform system level filtering. A choice of two digital filter responses are available, optimized for either /4 DQPSK digital mode or the existing analog cellular system. For digital mode, Root-Raised Cosine digital filters can be selected; whereas for analog mode, digital filters with a -3 dB point of 11.4 kHz can be selected. Their amplitude and phase response characteristics provide excellent adjacent channel rejection. A means is also provided to calibrate either on-chip or receive path offsets in both the I and Q channels. The receive section is also provided with a low power sleep mode, drawing only minimal current between receive bursts. Switched Capacitor Input The receive section analog front-end is sampled at MCLK/4 by a switched-capacitor filter. The filter has a zero at MCLK/8 as shown in Figure 8a. The receive channel also contains a digital low-pass filter (further details are contained in the following section) which operates at a clock frequency of MCLK/8. Due to the sampling nature of the digital filter, the pass band is repeated about the operating clock frequency (MCLK/8) and at multiples of the clock frequency (Figure 8b). Because the first null of the switched-capacitor filter coincides with the first image of the digital filter, this image is attenuated by an additional 30 dBs (Figure 8c) further simplifying the external antialiasing requirements. A simple R-C Network can be used to attenuate the digital filter image at MCLK/8 as shown in Figure 9. Receive Channel Differential Inputs The receive channel uses differential inputs to interface more easily to IQ demodulators and also to provide common-mode noise rejection. However, if required the receive channel inputs can also be configured for single ended operation. The primary and auxiliary channels have similar performance and either can be used for differential operation or single-ended operation. The CR12 control bit determines whether the primary or auxiliary inputs are connected to the differential inputs of the sigma-delta modulator. Figure 9 illustrates an antialiasing filter comprised of a single pole RC network with a -3 dB frequency of 159 kHz. The low-pass filter provides sufficient rejection at images of the FIR digital filter illustrated in Figure 10c. For single ended operation, the inverting input should be connected to a bias voltage and the noninverting input should swing 1.3 V around this bias voltage in order to exercise the entire ADC range. In applications where the full 1.3 V range is not required, the on-chip 1.23 V reference can be used to provide the bias voltage. For instance as in Figure 10, an OP295 rail-to-rail low power op amp is used to buffer the BYPASS pin in order to generate a 1.23 VBIAS. The VBIAS is connected to the inverting input thereby setting the single-ended input range equal to 0 V to 2.46 V. Also with the addition of an attenuator circuit the input range can be expanded to 0 V to 4.92 V as shown on the second ADC channel. If the inverting input is tied to AGND, then only half the ADC range is available.
5k IRx I 0.01nF IRx 5k
0dBs FRONT-END ANALOG FILTER TRANSFER MCLK/8 MCLK/4 MCLK/2
AD7013
5k
IQ DEMODULATOR
T
QRx 0.01nF
MHz
Q 5k Q
BYPASS 10nF
QRx
a.
0dBs DIGITAL FILTER TRANSFER FUNCTION MCLK/8 MCLK/4 MCLK/2
Figure 9. External RC Network for Differential Signals
10k AUX IRx 0.1nF AUX IRx 0 TO 2.46 VOLTS
MHz
b.
0dBs SYSTEM FILTER TRANSFER FUNCTION -30 dBs MAX MHz MCLK/8 MCLK/4 MCLK/2
AD7013
AUX QRx 0.1nF AUX QRx BYPASS
10k
10k
0 TO 4.92 VOLTS
c. Figure 8. Switched Capacitor and Digital Filter Transfer Functions
10nF
5V
295
1.23 VOLTS
Figure 10. External RC Network for Single-Ended Signals
REV. A
-11-
AD7013
VBIAS + 0.65 IRx
QUANTIZATION NOISE
VOLTAGE
VBIAS
BAND OF INTEREST
fs /2 388.8kHz
aa.
VBIAS - 0.65
IRx
NOISE SHAPING
10 ... 00
00 ... 00 ADC CODE
01 ... 11
BAND OF INTEREST
fs /2 388.8kHzMHz
Figure 11. ADC Transfer Function for Differential Operation
VBIAS + 1.3
b b.
ROOT RAISED COSINE FIR FILTER
IRx
VOLTAGE
VBIAS
BAND OF INTEREST
fs/2 388.8kHz
c
c. Figure 13. a. Effect of High Oversampling Ratio. b. Use of Noise Shaping to Further Improve SNR. c. Use of Digital Filtering to Remove the Out of Band Quantization Noise
00 ... 00 ADC CODE 01 ... 11
VBIAS - 1.3
IRx
10 ... 00
Figure 12. ADC Transfer Function for Single-Ended Operation
SIGMA-DELTA ADC The AD7013 receive channels employ a sigma-delta conversion technique, which provides a high resolution 15-bit output for both I and Q channels with system filtering being implemented on-chip. The output of the switched-capacitor filter is continuously sampled at MCLK/8, by a charge-balanced modulator, and is converted into a digital pulse train whose duty cycle contains the digital information. Due to the high oversampling rate which spreads the quantization noise from 0 to f S/2, the noise energy which is contained in the band of interest is reduced (Figure 13a). To reduce the quantization noise still further, a high order modulator is employed to shape the noise spectrum, so that most of the noise energy is shifted out of the band of interest (Figure 13b). The digital filter that follows the modulator removes the large out of band quantization noise (Figure 13c), while converting the digital pulse train into parallel 15-bit wide binary data. The 15-bit I and Q data plus an I/Q flag bit is made available, via a serial interface, as a 16-bit word, MSB first.
Digital Filter The digital filters used in the AD7013 receive section carry out two important functions. First, they remove the out of band quantization noise which is shaped by the analog modulator. Second, they are also designed to perform system level filtering, providing the Root-Raised Cosine filter as required for TIA IS-54. Since digital filtering occurs after the A/D conversion process, it can remove noise injected during the conversion process. Analog filtering cannot do this. Also, the digital filter combines low passband ripple with a steep roll off, while also maintaining a linear phase response. This is very difficult to achieve with analog filters. Filter Characteristics The digital filter is a 256-tap FIR filter, clocked at 1/8 the master clock frequency. A choice of two frequency responses are available: a Root-Raised Cosine response (CR11 = 0) and a brick wall response at 11.4 kHz (CR11 = 1) for analog mode. Figure 16 and Figure 17 illustrate the respective frequency responses for both digital mode and analog mode while Figure 18 compares the low frequency response of the digital filters. Due to the low-pass nature of the receive filters there is a settling time associated with step input functions. Output data will not be meaningful until all the digital filter taps have been loaded with data samples taken after the step change. Hence, the AD7013 digital filters have a settling time of 256 x 8t1 (i.e., 329.2 s when MCLK = 6.2208 MHz and 400 s when MCLK = 5.12 MHz).
-12-
REV. A
AD7013
CR14 10240 x t1
POWER-UP SEQUENCE
RECEIVE CHANNEL IN LOW POWER SLEEP MODE
ANALOG SETTLING AFTER POWER-UP
DIGITAL FILTER SETTLING
OFFSET CALIBRATION
ANALOG SETTLING
DIGITAL FILTER SETTLING
NORMAL OPERATION
RxCLK
RxFRAME
Figure 14. Autocalibration Routine After Exiting Low Power Sleep Mode
CR14 6144 x t1 RECEIVE CHANNEL IN LOW POWER SLEEP MODE ANALOG SETTLING AFTER POWER-UP DIGITAL FILTER SETTLING
CALIBRATION SEQUENCE
NORMAL OPERATION
RxCLK RxFRAME
Figure 15. User-Calibration Routine After Exiting Low Power Sleep Mode
REV. A
-13-
AD7013
0 -10 -20 MAGNITUDE - dBs -30 -40 -50 -60 -70 -80 -90 -100 0.0 7.5 15.0 22.5 30.0 37.5 FREQUENCY - kHz 45.0 52.5 60.0
Receive Offset Calibration Included in the digital filter is a means by which receive signal offsets may be calibrated out. Each channel of the digital low-pass filter section has an offset register. The offset register can be made to contain a value representing the dc offset of the preceding analog circuitry. In normal operation, the value stored in the offset register is subtracted from the filter output data before the data appears on the serial output pin. By so doing, dc offsets in the I and Q channels get calibrated out. Autocalibration or user calibration can be selected. Autocalibration will remove internal offsets only while user calibration allows the user to write to the offset register in order to also remove external offsets. The offset registers have enough resolution to hold the value of any dc offset between 153 mV (1/8th of the input range). The 10-bit offset register represents a twos-complement value which is mapped to a 15-bit twos-complement word as shown in Figure 19. The contents of the offset registers are subtracted from their respective ADC samples.
10-BIT I OR Q OFFSET REGISTER
Figure 16. Receive Root Raised Cosine FIR Filter; CR11 = 0, MCLK = 6.2208 MHz
0 -10 -20 MAGNITUDE - dBs -30 -40 -50 -60 -70 -80 -90 -100 0.0 7.5 15.0 22.5 30.0 37.5 FREQUENCY - kHz 45.0 52.5 60.0
D9
D8
D0
0
0
15-BIT I OR Q OFFSET WORD
D14 MSB
D13
D12
D11
D10
D2
D1
D0 LSB
Figure 19. Position of the 10-Bit Offset Word Within the 15-Bit ADC Word
Receive Offset Adjust: Auto-Calibration (CR13 = 0) If receive autocalibration has been selected (CR13 = 0), then the AD7013 will initiate an autocalibration routine each time the receive path is brought out of the low power sleep mode (CR14 = 0). The AD7013 internally disconnects the differential inputs from the input pins and shorts the differential inputs to measure the resulting ADC offset. This is then averaged 16 times to reduce ADC noise, and the averaged result is then placed in the offset register. The input to the ADC is then switched back for normal operation, and after allowing for both analog settling and digital filter settling, the first IQ sample pair is output (Figure 14). Autocalibration will only remove on-chip offsets. Receive Offset Adjust: User Calibration (CR13 = 1) When user calibration has been selected, the receive offset register can be written to, allowing offsets in the IF/RF demodulation circuitry to be also calibrated out. However, the user is now responsible for calibrating out receive offsets belonging to the AD7013. When the receive path enters the low power mode (CR14 = 0), the offset registers remain valid. After powering up, the first IQ sample pair is output once time has elapsed for both the analog circuitry to settle and also for the output of the digital filter to settle as shown in Figure 15.
Figure 17. Receive Analog Mode FIR Filter; CR11 = 1, MCLK = 5.12 MHz
0 -10 -20 -30 ANALOG MODE FILTER RESPONSE DIGITAL MODE FILTER RESPONSE
MAGNITUDE - dBs
-40 -50 -60 -70 -80 -90 -100 0.0 15.0 30.0 45.0
FREQUENCY - kHz
Figure 18. Comparision of the Two Frequency Responses Where Digital Mode was Clocked at 6.2208 MHz and Analog Mode was Clocked at 5.12 MHz
-14-
REV. A
AD7013
ADC Sampling Vernier Also included in the digital filter is the means to vary the sampling instant, as Figure 20 illustrates. The absolute group delay can be varied from a minimum of four symbols to a maximum of four and a half symbols allowing the user to define the sampling instant to a resolution 1/32 of the symbol rate. The vernier can be used to seek the optimum sampling instant for minimum Inter-SymbolInterference (ISI).
LOW SAMPLING RATE; CR10 = 0 SAMPLING PERIOD = 128 x t1 VERNIER = N 0 N 15 VERNIER = 0 8 x t1 x N TIME
Table IV. Loading Sequence for the 6-Bit Interface
DB9-DB0 Ignored Ignored Ignored Ignored Ignored A3-A0 0011 Destination Destination Destination Destination S1, S0 D9, D8 D7, D6 D5, D4 D3, D2 D1, D0 Action D9S1 and D8S0 D7S1 and D6S0 D5S1 and D4S0 D3S1 and D2S0 D1S1 and D0S0 Destination RegD9-D0
Address Address Address Address
Receive Section Digital Interface The receive interface can be connected to DSP processors requiring the use of only one serial port. The 15-bit I and Q samples are made available as 16-bit words, where the last bit in each word is an I/Q flag bit. The serial data is made available on the RxDATA pin, with the I/Q flag indicating whether the 16-bit word being clocked out is an I sample or a Q sample. Although the I data is clocked out before the Q data, internally both samples are processed together. The receive interface (RxCLK, RxFRAME & RxDATA) can be 3Stated by setting CR18 to zero, CR18 should be set high for normal operation. When the receive section is put into sleep mode, by setting CR14 to zero, the receive interface will complete the current IQ cycle before entering into a low power sleep mode. High Sampling Rate (CR10 =1) The timing diagram for the receive interface is shown in Figure 3. The output word rate per channel is equal to 97.2 kHz (MCLK/64) which corresponds to 4 times the symbol rate. When the receive section is brought out of sleep mode (CR14 = 1), the receive section will initiate an offset autocalibration routine if CR13 = 0. Once the receive offset calibration routine is complete then RxCLK will continuously shift out I and Q data, always beginning with I data. RxFRAME provides a framing signal that is used to indicate the beginning of an I or Q, 16-bit data word that is valid on the next falling edge of RxCLK. On coming out of sleep, RxFRAME goes high one clock cycle before the beginning of I data, and subsequently goes high in the same clock cycle as the last bit of each 16-bit word (both I and Q). RxDATA is valid on the falling edge of RxCLK and is clocked out MSB first, with the I/Q flag bit indicating whether the 16-bit word is an I sample or a Q sample.
HIGH SAMPLING RATE; CR10 = 1 SAMPLING PERIOD = 64 x t1 TIME
VERNIER = N 0N7 VERNIER = 0 8 x t1 x N
Figure 20. I and Q ADC Sampling Vernier for 2 x the Symbol Rate and 4 x the Symbol Rate
A 4-bit vernier register is used to set the sampling instant for both the I and Q receive ADCs. When the vernier register is programmed with zero the ADCs will have a minimum group delay of approximately 165 s. Nonzero values in the vernier register will add additional group delay thereby moving the sampling instant for both ADCs. After programming the sampling vernier it takes eight symbols (330 s) for the digital filter to settle. When the ADC is operating at the high rate, vernier values from 8 to 15 yield similar sampling instants as vernier values from 0 to 7, but delayed by an additional 1/4 of a symbol period. Table III. Loading Sequence for the 16-Bit Interface
DB9-DB0 D9-D0 A3-A0 Destination Address S1, S0 Ignored Action Destination RegD9-D0
DxCLK (O) FRAME IN (I)
DATA IN (I)
DB9 IGNORED
DB0
A3
A2
A1
A0
S1 DATA
S0
ADDRESS
NOTE: (O) INDICATES AN OUTPUT, (I) INDICATES AN INPUT
Figure 21. 6-Bit Serial Interface for Internal AD7013 Registers
REV. A
-15-
AD7013
Low Sampling Rate (CR10 = 0) The timing diagram for the receive interface is shown in Figure 4. The output word rate per channel is equal to 48.6 kHz (MCLK/ 128) which corresponds to two times the symbol rate. The low sampling rate operates in a similar manner to that described for the high sampling rate. AUXILIARY DACs One 10-bit auxiliary DAC and two 8-bit auxiliary DACs are provided for extra control functions such as automatic gain control, automatic frequency control and power control. Figure 22 illustrates a simplified block diagram of the auxiliary DACs. The AUX DACs consist of high impedance current sources, designed to operate at very low currents while maintaining their DC accuracy. The DACs are designed using a current segmented architecture. The bit currents corresponding to each digital input are either routed to the analog output (bit = 1) or to AGND (bit = 0). Each of the auxiliary DACs has independent low power sleep modes. The command register has three control bits CR17, CR16 and CR15 which control AUX DAC1, AUX DAC2 and AUX DAC3 respectively. A logic 0 represents low power sleep mode and a logic 1 represents normal operation. The full-scale currents of the auxiliary DACs are controlled by a single external resistor, RSET, connected between the FS ADJUST pin and AGND. The relationship between full-scale current and RSET is given as follows: 10-Bit AUX DAC AUX DACFULL SCALE (mA) = 7992 x VREF (V)/ RSET () 8-Bit AUX DACs AUX DACFULL SCALE (mA) = 3984 x VREF (V)/ RSET () By using smaller values of RSET, thereby increasing AUX DAC fullscale current, improved INL and DNL performance is possible as shown in Table V. Table V. AUX DAC1 INL and DNL as a Function of R SET RSET 18 k 9 k 4.5 k Worst Case INL (LSBs) -1.45 +1.22 +1.18 Worst Case DNL (LSBs) +1.83 +1.59 +1.38
AUX DAC1, AUX DAC2 OR AUX DAC3
PCB Layout Considerations The use of an analog ground plane is recommended, where the ground plane extends around the analog circuitry. Both AGND and DGND should be externally tied together and connected to the analog ground plane. Good power supply decoupling is very important for best ADC performance. A 0.1 F ceramic decoupling capacitor should be connected between VAA and the ground plane. The physical placement of the capacitor (surface mount if possible) is important and should be placed as close to the pin of the device as is physically possible. This is also applied to the V DD pin. Poor power supply decoupling can lead to a degradation in ADC offsets and SNR. The Bypass pin should be decoupled to the ground plane using a 10 nF capacitor. Large capacitor values are not recommended as this can cause the reference not to reach its final value, on power up, before ADC autocalibration has commenced. Capacitive loading of digital outputs should be minimized as much as possible if power dissipation is a critical factor. The charging and discharging of external load capacitances can be a significant contribution to power dissipation, especially when the AD7013 is in a low power sleep mode as the DxCLK remains active.
VREF (1.23V)
AD7013
10-BIT AUX DAC1 8-BIT AUX DAC2 8-BIT AUX DAC3
FULL-SCALE ADJUST CONTROL
RSET
18k
4.5k AGND
9k AGND
9k AGND
AGND
Figure 22. AUX DACs
RFB +5V
1 TO 4 VOLTS
RLOAD
OP-295
AD7013
Digital Interface Communication with the Command register, auxiliary DACs, ADC offset registers and ADC vernier is accomplished via the 3-pin serial interface. Either one of two loading formats may be used to write to any of the AD7013's internal registers. The first format consists of a single 16-bit serial word to write to any internal register (Table III). The second format consists of five 16-bit serial words, where only the last 6 bits in each 16-bit word are used to load five 2-bit data nibbles. The load sequence for this format is given is Table IV. The second format is only enable when the Register Address 3 is used as the destination register as shown in Table I.
FS ADJUST RSET 18k BYPASS AUX DAC 10-BIT 8-BIT 10nF R LOAD 2.4k 11k R FB 5.4k 4.9k
Figure 23. External Op Amp Circuitry to Extend Output Voltage Range
-16-
REV. A
Typical Performance Characteristics-AD7013
APPENDIX 1
1.5
1.5
1
1
DNL ERROR - LSBs
0.5
INL ERROR - LSBS
0.5
0
0
-0.5
-0.5
-1
-1
-1.5
-1.5
0
256
512 DAC CODE
768
1024
0
256
512 DAC CODE
768
1024
10-Bit AUX DAC1 Integral Nonlinearities (INL)
10-Bit AUX DAC1 Differential Nonlinearities (DNL)
0.5
0.5
0.25
INL ERROR - LSBS
DNL ERROR - LSBs
0.25
0
0
-0.25
-0.25
-0.5 0 64 128 DAC CODE 192 256
-0.5
0
64
128 DAC CODE
192
256
8-Bit AUX DAC2 Integral Nonlinearities (INL)
8-Bit AUX DAC2 Differential Nonlinearities (DNL)
0.5
0.5
0.25
INL ERROR - LSBS
DNL ERROR - LSBs 0 64 128 DAC CODE 192 256 0.25
0
0
-0.25
-0.25
-0.5
-0.5 0 64 128 DAC CODE 192 256
8-Bit AUX DAC3 Integral Nonlinearities (INL)
8-Bit AUX DAC3 Differential Nonlinearities (DNL)
REV. A
-17-
AD7013
0 -10 -20 -30 MAGNITUDE - dB MAGNITUDE - dB -40 -50 -60 -70 -80 -90 -100 -110 -120 0 10 20 FREQUENCY - kHz 30 40 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 10 20 FREQUENCY - kHz 30 40
I Channel Analog Mode FFT; MCLK = 5.12 MHz
Q Channel Analog Mode FFT; MCLK = 5.12 MHz
0 -10 -20 -30
MAGNITUDE - dB
0 -10 -20 -30
MAGNITUDE - dB
-40 -50 -60 -70 -80 -90
-40 -50 -60 -70 -80 -90
-100 -110 -120 0 12.15 24.3 FREQUENCY - kHz 36.45 48.6
-100 -110 -120 0 12.15 24.3 FREQUENCY - kHz 36.45 48.6
I Channel Digital Mode FFT; MCLK = 6.2208 MHz
Q Channel Digital Mode FFT; MCLK = 6.2208 MHz
1
1
Q SAMPLES
0
Q SAMPLES
-1 0 I SAMPLES 1
0
-1
-1 -1 0 I SAMPLES 1
/4 DQPSK I and Q Receive Samples
/4 DQPSK Constellation Diagram; Typical Error Vector 2% RMS
-18-
REV. A
AD7013
140 120 NUMBER OF OCCURRENCES
100 80 60 40
20 0 -41 -40 -39 -38 -37 -36 -35 -34 -33 -32 -31 -30 -29 -28 -27 -26 -25 -24 -23 -22 -21 -20 -19 -18 -17 -16 -15 -14 -13 -12 ADC CODE
I Channel ADC Noise Histogram with IRx and IRx Tied Together and Offset Register = 0; Number Codes = 1000, Standard Deviation = 4.44 Codes
140
120 NUMBER OF OCCURRENCES
100 80 60 40
20 0 -41 -40 -39 -38 -37 -36 -35 -34 -33 -32 -31 -30 -29 -28 -27 -26 -25 -24 -23 -22 -21 -20 -19 -18 -17 -16 -15 -14 -13 -12 ADC CODE
Q Channel ADC Noise Histogram with QRx and QRx Tied Together and Offset Register = 0; Number Codes = 1000, Standard Deviation = 3.82 Codes
3
2.5 SLEEP MODE IDD - mA
2 V AA = VDD = +5V 1.5 MCLK = 6.2208 MHz CR14 = CR15 = CR16 = CR17 = 0 1
0.5
0
0
50
100
150
200
DxCLK LOAD CAPACITANCE - pF
AD7013 Sleep Current as a Function of DxCLK Load Capacitance
REV. A
-19-
AD7013
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead SSOP (RS-28)
C1862a-7.5-7/94
0.03 (0.762) 0.022 (0.558)
28
15 0.212 (5.38) 0.205 (5.207) 0.311 (7.9) 0.301 (7.64) 1 14
PIN 1
0.407 (10.34) 0.397 (10.08)
0.07 (1.78) 0.066 (1.67)
0.008 (0.203) 0.002 (0.050)
8 0 0.009 (0.229) 0.005 (0.127) 1. LEAD NO. 1 IDENTIFIED BY A DOT. 2. LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS 0.0256 (0.65) BSC
-20-
REV. A
PRINTED IN U.S.A.

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