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9-BIT LATCHED ECL-TO-TTL SY10H603 SY100H603 FEATURES s s s s s s s s s s 9-bit ideal for byte-parity applications 3-state TTL outputs Flow-through configuration Extra TTL and ECL power/ground pins to minimize switching noise Dual supply 6.0ns max. delay into 50pF, 12ns into 200pF (all outputs switching) PNP TTL inputs for low loading Choice of ECL compatibility: MECL 10KH (10Hxxx) or 100K (100Hxxx) Fully compatible with Motorola MC10H/100H603 Available in 28-pin PLCC package DESCRIPTION The SY10/100H603 are 9-bit, dual supply ECL-to-TTL translators. Devices in the Micrel-Synergy 9-bit translator series utilize the 28-lead PLCC for optimal power pinning, signal flow-through and electrical performance. The devices feature a 48mA TTL output stage and AC performance is specified into both a 50pF and 200pF load capacitance. Latching is controlled by Latch Enable (LEN) and Master Reset (MR) resets the latches. A HIGH on OEECL sends the outputs into the high impedance state. All control inputs are ECL level. The 10H version is compatible with MECL 10KH ECL logic levels. The 100H version is compatible with 100K levels. PIN CONFIGURATION GND VCCT GND Q7 Q5 Q6 BLOCK DIAGRAM Q4 26 27 28 1 2 3 4 25 24 23 22 21 20 19 Q8 OEECL D0 DQ EN D1 DQ EN D2 DQ EN Q2 Q1 Q0 18 17 16 Q3 VCCT Q2 GND Q1 Q0 D8 D7 VCCE D6 D5 D4 D3 TOP VIEW PLCC 15 14 13 12 5 6 7 8 9 10 11 D0 MR LEN D3 DQ EN Q3 ECL D4 DQ EN Q4 TTL PIN NAMES Q5 GND Pin Function TTL Ground (0V) ECL VCC (0V) TTL Supply (+5.0V) ECL Supply (-5.2/-4.5V) Data Inputs (ECL) Data Outputs (TTL) 3-state Control (ECL) Latch Enable (ECL) Master Reset (ECL) Rev.: D Amendment: /0 D5 DQ EN DQ EN DQ EN DQ EN D6 Q6 VCCE VCCT D7 Q7 VEE D0-D8 Q0-Q8 D8 LEN MR Q8 OEECL LEN MR 1 OEECL VEE D1 D2 Issue Date: April, 1998 Micrel SY10H603 SY100H603 TRUTH TABLE LOGIC DIAGRAM D L H X X X LEN L L H X X MR L L L H X OEECL L L L L H Q L H Q0 L Z DC ELECTRICAL CHARACTERISTICS VCCT = 5.0V 10%; VEE = -4.75V to -5.5V (10H Version); VEE = -4.2V to -5.5V (100H Version) TA = 0C Symbol IEE ICC IOS IOZH IOZL Parameter Power Supply Current, ECL Power Supply Current, TTL Output Short Circuit Current Output Disable Current, HIGH Output Disable Current, LOW Min. 45 80 -100 -- -- Max. 63 110 -225 50 -50 TA = +25C Min. 45 80 -100 -- -- Max. 64 110 -225 50 -50 TA = +85C Min. 45 80 -100 -- -- Max. 68 110 -225 50 -50 Unit mA mA mA A A Condition -- -- VOUT = 0V VOUT = 2.7V VOUT = 0.5V AC ELECTRICAL LOGIC DIAGRAM CHARACTERISTICS VCCT = 5.0V 10%; VEE = -4.75V to -5.5V (10H Version); VEE = -4.2V to -5.5V (100H Version) TA = 0C Symbol tPLH tPHL Parameter Propagation Delay to Output D LEN MR tS tH tw(L) tPLZ tPHZ tPZL tPZH tr tf Set-up Time, D to LEN Hold Time, D to LEN LEN Pulse Width, LOW Output Disable Time Output Enable Time Output Rise/Fall Time 1.0V - 2.0V Min. 3.2 6.4 3.5 7.0 3.0 6.0 1.5 0.8 2.0 2.5 4.2 2.0 4.0 0.2 0.2 Max. 6.0 12 6.5 13 6.0 12 -- -- -- 6.5 13 5.0 10 1.2 3.0 TA = +25C Min. 3.2 6.4 3.5 7.0 3.0 6.0 1.5 0.8 2.0 2.5 4.2 2.0 4.0 0.2 0.2 Max. 6.0 12 6.5 13 6.0 12 -- -- -- 6.5 13 5.0 10 1.2 3.0 TA = +85C Min. 3.2 6.4 3.5 7.0 3.0 6.0 1.5 0.8 2.0 2.5 4.2 2.0 4.0 0.2 0.2 Max. 6.0 12 6.5 13 6.0 12 -- -- -- 6.5 13 5.0 10 1.2 3.0 Unit ns ns ns ns ns ns ns ns ns Condition CL = 50pF CL = 200pF CL = 50pF CL = 200pF CL = 50pF CL = 200pF -- -- -- CL = 50pF CL = 200pF CL = 50pF CL = 200pF CL = 50pF CL = 200pF PRODUCT ORDERING CODE Ordering Code SY10H603JC SY10H603JCTR SY100H603JC SY100H603JCTR Package Type J28-1 J28-1 J28-1 J28-1 Operating Range Commercial Commercial Commercial Commercial 2 Micrel SY10H603 SY100H603 28 LEAD PLCC (J28-1) Rev. 03 3 Micrel SY10H603 SY100H603 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA FAX + 1 (408) 980-9191 + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated 4 |
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