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9-BIT LATCHED TTL-TO-ECL
SY10H602 SY100H602
FEATURES
s 9-bit ideal for byte-parity applications s Flow-through configuration s Extra TTL and ECL power/ground pins to minimize switching noise s Dual supply s 3.5ns max. D to Q s PNP TTL inputs for low loading s Choice of ECL compatibility: MECL 10KH (10Hxxx) or 100K (100Hxxx) s Fully compatible with Motorola MC10H/100H602 s Available in 28-pin PLCC package
DESCRIPTION
The SY10/100H602 are 9-bit, dual supply TTL-to-ECL translators with latches. Devices in the Micrel-Synergy 9-bit translator series utilize the 28-lead PLCC for optimal power pinning, signal flow-through and electrical performance. The H602 features D-type latches. Latching is controlled by Latch Enable (LEN), while the Master Reset input resets the latches. A post-latch logic enable is also provided (ENECL), allowing control of the output state without destroying latch data. All control inputs are ECL level. The 10H version is compatible with MECL 10KH ECL logic levels. The 100H version is compatible with 100K levels.
BLOCK DIAGRAM
ENECL D0 DQ EN DQ EN DQ EN DQ EN DQ EN DQ EN DQ EN DQ EN DQ EN Q0
PIN CONFIGURATION
VCCT D3 D5 D4 D2 D1 D0
25 24 23 22 21 20 19
D1
Q1
D2
Q2
D3
Q3
D6 D7 D8 GND MR LEN ENECL
26 27 28 1 2 3 4 5 6 7 8 9 10 11
18 17 16
Q0 Q1 VCCE VCCO Q2 VCCO Q3
TOP VIEW PLCC
15 14 13 12
Q8 Q7 VCCO
Q6
VEE Q5
Q4
ECL
D5
Q5
PIN NAMES
Pin Function TTL Ground (0V) ECL VCC (0V) ECL VCC (0V) -- Outputs TTL Supply (+5.0V) ECL Supply (-5.2/-4.5V) Data Inputs (TTL) Data Outputs (ECL) Enable Control (ECL) Latch Enable (ECL) Master Reset (ECL)
Rev.: D Amendment: /0
D6
Q6
GND VCCE
D7
Q7
VCCO VCCT
D8 LEN MR
Q8
VEE D0-D8 Q0-Q8 ENECL LEN MR
1
Q4
Issue Date: March, 1998
TTL
D4
Micrel
SY10H602 SY100H602
TRUTH TABLE LOGIC DIAGRAM
D L H X X X LEN L L H X X MR L L L H X ENECL H H H H L Q L H Q0 L L
DC ELECTRICAL CHARACTERISTICS
VCCT = 5.0V 10%; VEE = -4.75V to -5.5V (10H Version); VEE = -4.2V to -5.5V (100H Version)
TA = 0C Symbol IEE Parameter Power Supply Current, ECL 10H 100H Power Supply Current, TTL Min. -- -- -- -- Max. 125 122 48 50 TA = +25C Min. -- -- -- -- Max. 125 123 48 50 TA = +85C Min. -- -- -- -- Max. 125 132 48 50 mA -- Unit mA Condition --
ICCH ICCL
AC ELECTRICAL CHARACTERISTICS LOGIC DIAGRAM
VCCT = 5.0V 10%; VEE = -4.75V to -5.5V (10H Version); VEE = -4.2V to -5.5V (100H Version)
TA = 0C Symbol tPLH tPHL Parameter Propagation Delay to Output D LEN MR ENECL Set-up Time, D to LEN Hold Time, D to LEN LEN Pulse Width, LOW Output Rise/Fall Time 20% to 80%, 80% to 20%
(L)
TA = +25C Min. 1.5 2.1 2.1 1.7 2.0 1.0 2.0 0.5 Max. 3.2 3.5 3.5 3.3 -- -- -- 1.5
TA = +85C Min. 1.7 2.4 2.5 1.8 2.0 1.0 2.0 0.5 Max. 3.5 3.7 3.9 3.7 -- -- -- 1.5 ns ns ns ns -- -- -- -- Unit ns Condition --
Min. 1.4 2.0 2.0 1.6 2.0 1.0 2.0 0.5
Max. 3.0 3.4 3.4 3.2 -- -- -- 1.5
tS tH tw tr tf
PRODUCT ORDERING CODE
Ordering Code SY10H602JC SY10H602JCTR SY100H602JC SY100H602JCTR Package Type J28-1 J28-1 J28-1 J28-1 Operating Range Commercial Commercial Commercial Commercial
2
Micrel
SY10H602 SY100H602
28 LEAD PLCC (J28-1)
Rev. 03
3
Micrel
SY10H602 SY100H602
MICREL-SYNERGY
TEL
3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
FAX
+ 1 (408) 980-9191
+ 1 (408) 914-7878
WEB
http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated
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