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19-1534; Rev 1; 10/99
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator
General Description
The MAX3831/MAX3832 are 4:1 multiplexers (muxes) and 1:4 demultiplexers (demuxes) with automatic channel assignment. Operating from a single +3.3V supply, the mux receives four parallel, 622Mbps SDH/SONET channels. These channels are bit interleaved to generate a serial data stream of 2.488Gbps for interfacing to an optical or an electrical driver. A 10-bit-wide elastic buffer tolerates up to 7.5ns skew between any parallel data input and the reference clock. An external 155MHz reference clock is required for the on-chip PLL to synthesize a high-frequency 2.488GHz clock for timing the outgoing data streams. The MAX3831/MAX3832's demux receives 2.488Gbps serial data and the 2.488GHz clock from an external clock/data recovery device (MAX3876), converting it to four 622Mbps LVDS outputs. The MAX3831 provides a 622MHz LVDS clock output, and the MAX3832 provides a 155MHz LVDS clock output. An internal frame detector looks for a 622Mbps SDH/SONET framing pattern and rolls the demux to maintain proper channel assignment at the outputs. These devices also include an embedded pattern generator that enables a full-speed, built-in self-test (BIST). Two different loopback modes provide system test flexibility. A TTL loss-of-frame monitor is included. The MAX3831/MAX3832 are available in 64-pin TQFP-EP (exposed paddle) packages and are specified over the upper commercial (0C to +85C) temperature range.
Features
o +3.3V Single Supply o 1.45W Power Dissipation (MAX3831) o 4-Channel Mux/Demux with Fully Integrated 2.488GHz Clock Generator o Frame Detection Maintains Channel Assignment o 7.5ns Elastic Store Range o 2.5ps RMS Serial-Data Output Random Jitter o 8ps Serial-Data Output Deterministic Jitter o 622Mbps LVDS Parallel Input/Output o 2.488Gbps Serial CML Input/Output o On-Chip Pattern Generator Provides High-Speed BIST o System Test Flexibility: System Loopback, Line Loopback o Loss-of-Frame Indicator
MAX3831/MAX3832
Applications
SDH/SONET Backplanes High-Speed Parallel Links Intrarack/Subrack Interconnects ATM Switching Networks Line Extenders Dense Digital CrossConnects
Ordering Information
PART TEMP. RANGE 0C to +85C 0C to +85C PIN-PACKAGE 64 TQFP-EP 64 TQFP-EP MAX3831UCB MAX3832UCB
Pin Configuration appears at end of data sheet.
Typical Application Circuit
TTL 0.33F TTL TTL TTL +3.3V 0.1F RSETES 155MHz REF CLOCK INPUT 4 4 LVDS CMOS OVERHEAD 4 LVDS 4 LVDS LVDS RCLKI+ RCLKIPDI1+ TO PDI4+ PDI1- TO PDI4PDO1+ TO PDO4+ PDO1- TO PDO4PCLKO+ PCLKOTRIEN TTL GND FIL+ FILTEST LOF PLBEN VCC SCLKISCLKI+ SDICML CML MAX3876 2.5Gbps CDR 2.5Gbps OPTICAL TRANSCEIVER
MAX3831 MAX3832
SDI+ SDO+ SDOLBEN RSETFR
TTL TTL
________________________________________________________________ Maxim Integrated Products
1
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+3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator MAX3831/MAX3832
ABSOLUTE MAXIMUM RATINGS
Positive Supply Voltage (VCC)...............................-0.5V to +5.0V Input Voltage (LVDS, TTL)..........................-0.5V to (VCC + 0.5V) CML Input Voltage ..........................(VCC - 0.8V) to (VCC + 0.5V) FIL+, FIL- Voltage.......................................-0.5V to (VCC + 0.5V) TTL Output Voltage ....................................-0.5V to (VCC + 0.5V) LVDS Output Voltage ..................................-0.5V to (VCC +0.5V) CML Output Currents..........................................................22mA Continuous Power Dissipation (TA = +85C) (Note 1) 64-Pin TQFP-EP (derate 40.0mW/C above +85C) .........2.6W Operating Temperature Range...............................0C to +85C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10sec) .............................+300C
Note 1: Based on empirical data from the MAX3831/MAX3832 evaluation kit.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, LVDS differential load = 100 1%, CML load = 50 1% to VCC, all TTL inputs are open, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C and VCC = +3.3V.) PARAMETER Supply Current LVDS INPUTS AND OUTPUTS Input Voltage Range Differential Input Threshold Threshold Hysteresis Input Impedance Input Common-Mode Current Output Voltage High Output Voltage Low Differential Output Voltage Change in Magnitude of Differential Output Voltage for Complementary States Output Offset Voltage Change in Magnitude of Output Offset Voltage for Complementary States Differential Output Impedance Output Current CML INPUTS AND OUTPUTS Differential Output Voltage Differential Output Impedance Output Common-Mode Voltage Single-Ended Input Voltage Range Differential Input Voltage Swing Differential Input Impedance 2 VIS Figure 2 VCC 0.6 400 85 100 VODp-p 640 85 800 100 VCC - 0.2 VCC + 0.4 1200 115 1000 115 mVp-p V V mVp-p VIN VIDTH VHYST RIN IOS VOH VOL VOD VOD VOS VOS TRIEN = GND TRIEN = VCC Short outputs together (Note 3) 80 >1 120 12 1.125 Figure 1 0.925 250 400 25 1.275 25 LVDS input, VOS = 1.2V 85 0 -100 90 100 270 1.475 115 2400 +100 mV mV mV A V V mV mV V mV M mA SYMBOL ICC CONDITIONS CML inputs and outputs open, LVDS input VOS = 1.2V (Note 2) MAX3831 MAX3832 MIN TYP 440 480 MAX 580 614 UNITS mA
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+3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, LVDS differential load = 100 1%, CML load = 50 1% to VCC, all TTL inputs are open, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C and VCC = +3.3V.) PARAMETER TTL INPUTS AND OUTPUTS Input Voltage High Input Voltage Low Input Current High Input Current Low Output Voltage High Output Voltage Low Output Impedance VIH VIL IIH IIL VOH VOL VIH = 2.0V VIL = 0 IOH = 20A IOL = 2mA TRIEN = GND 6 -250 -550 2.4 0.4 2.0 0.8 -50 -100 V V A A V V k SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX3831/MAX3832
Note 2: When TEST = GND, the pattern generator will consume an additional 30mA. Note 3: Guaranteed by design and characterization.
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, LVDS differential load = 100 1%, CML load = 50 1% to VCC, all TTL inputs are open, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C and VCC = +3.3V.) (Note 4) PARAMETER Parallel Input Data Rate Maximum Parallel Input Skew Serial-Data Output Rate Serial-Data Output Rise/Fall Time Serial-Data Output Random Jitter Serial-Data Output Deterministic Jitter 1:4 DEMULTIPLEXER Serial-Data Input Rate Serial-Data Setup Time Serial-Data Hold Time Parallel-Data Output Rate Parallel-Clock Output Frequency PCLKO to PDO_ Delay LVDS Output Rise/Fall Time LVDS Differential Skew LVDS Channel-to-Channel Skew LVDS Three-State Enable Time Note 4: Note 5: Note 6: Note 7: tSKEW1 tSKEW2 tSU tH PDO PCLKO tCLK-Q MAX3831 MAX3832 MAX3831, Figure 3 20% to 80% Any differential pair PDO1 to PDO4 <100 30 -100 Figure 3 Figure 3 100 100 622.08 622.08 155.52 90 300 350 65 2.48832 Gbps ps ps Mbps MHz ps ps ps ps ns tr, tf SRJ SDJ 20% to 80% (Note 6) (Note 7) 8 tes (Note 5) SYMBOL CONDITIONS MIN TYP 622.08 7.5 2.48832 120 3.5 40 18 MAX UNITS Mbps ns Gbps ps psRMS psp-p psp-p 4:1 MULTIPLEXER WITH CLOCK GENERATOR
AC characteristics are guaranteed by design and characterization. Relative to the positive edge of the 155MHz reference clock. PDI1 to PDI4 aligned to RCLKI at reset. Measured with a reference clock jitter of <1psRMS. Deterministic jitter is the arithmetic sum of pattern-dependent jitter and pulse-width distortion. _______________________________________________________________________________________ 3
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator MAX3831/MAX3832
PDO+ D PDOVPDOSINGLE-ENDED OUTPUT VPDO+ VOH RL = 100 V VOD
|VOD|
VOS VOL
+VOD DIFFERENTIAL OUTPUT 0V (DIFF) 0V -VOD VODp-p = VPDO+ - VPDO-
Figure 1. Definition of the LVDS Output
SDI+ SDI-
200mV MIN 600mV MAX
(SDI+) - (SDI-)
VID
400mVp-p MIN 1200mVp-p MAX
Figure 2. Definition of the CML Input
tSCLK = 1 / fSCLK SCLKI tSU SDI tH
PCLKO tCLK-Q PDO1-PDO4
NOTE: SIGNAL SHOWN IS DIFFERENTIAL. FOR EXAMPLE, SCLKI = (SCLKI+) - (SCLKI-).
Figure 3. Timing Parameters 4 _______________________________________________________________________________________
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator
Typical Operating Characteristics
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
SERIAL-DATA OUTPUT EYE DIAGRAM
MAX3831/2 toc01
MAX3831/MAX3832
SERIAL-DATA OUTPUT JITTER
MAX3831/2 toc02
SUPPLY CURRENT vs. TEMPERATURE
MAX3831/2 toc03
600 500 SUPPLY CURRENT (mA) 400 300 200 100 0 MAX3832 MAX3831
223-1 PRBS PATTERN
WIDEBAND RMS JITTER = 2.48ps
50ps/div
5ps/div
-50
-25
0
25
50
75
100
TEMPERATURE (C)
ELASTIC STORE RANGE
VARIATION OF DATA DELAY AFTER RESET (ns) 8 6 4 2 0 -2 -4 -6 -8 -10 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 DATA TO RCLKI DELAY AT RESET (ns) -20 -50 CHANNEL ALIGNED TO RCLKI 0 ERROR-FREE OPERATION
MAX3831/2 toc04
SERIAL-DATA HOLD TIME
MAX3831/2 toc05
10
100 80 HOLD TIME (ps) 60 40 20
-25
0
25
50
75
100
TEMPERATURE (C)
SERIAL-DATA SETUP TIME
MAX3831/2 toc06
MAX3831 PARALLEL CLOCK-TO-DATA OUTPUT PROPAGATION DELAY vs. TEMPERATURE
PCLKO TO PDO_ PROPAGATION DELAY (ps)
MAX3831/2 toc07
100 80 SETUP TIME (ps)
300 250 200 150 100 50 0
60
40
20
0 -50 -25 0 25 50 75 100 TEMPERATURE (C)
-50
-25
0
25
50
75
100
TEMPERATURE (C)
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+3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator MAX3831/MAX3832
Pin Description
PIN 1, 16, 25, 28, 29, 32, 43, 48, 49, 60, 63 2, 5, 10, 13, 17, 24, 38, 55, 59, 64 3 4 6 NAME GND Supply Ground FUNCTION
VCC SDOSDO+ LBEN
+3.3V Supply Voltage Negative CML Serial-Data Output, 2.488Gbps Positive CML Serial-Data Output, 2.488Gbps Line Loopback Enable. When this TTL input is forced low, the CML serial-data inputs (SDI) route directly to the CML serial-data outputs (SDO). No other inputs or outputs are affected. An internal 15k pull-up resistor pulls LBEN high for normal operation. See Test Loopbacks. Self-Test Enable. When this TTL input is forced low, the built-in pattern generator generates a standard OC-12 SONET-like frame of 12 A1s, 12 A2s, and 9696 bytes of 27 - 1 pseudorandom bits. This also enables an internal serial-system-loopback path. The CML inputs (SDI and the SCLK) and the LVDS inputs are ignored in this mode. An internal 15k pullup resistor pulls TEST high for normal operation. Positive CML Serial-Data Input, 2.488Gbps Negative CML Serial-Data Input, 2.488Gbps Positive CML Serial-Clock Input, 2.488GHz Negative CML Serial-Clock Input, 2.488GHz Negative LVDS Parallel-Clock Output, 622.08MHz (MAX3831); 155.52MHz (MAX3832) Positive LVDS Parallel-Clock Output, 622.08MHz (MAX3831); 155.52MHz (MAX3832) No Connection Frame Reset. When this TTL input is forced low, the frame detector and pattern generator are reset. The LOF output is also asserted low. An internal 15k pull-up resistor pulls RSETFR high for normal operation. TTL Loss-of-Frame Output. Asserts low in a loss-of-frame condition. 3-State Enable. When this TTL input is forced low, all TTL and LVDS outputs go into a highimpedance state. An internal 15k pull-up resistor pulls TRIEN high for normal operation. Negative LVDS Parallel-Data Output, 622Mbps Positive LVDS Parallel-Data Output, 622Mbps Negative LVDS Parallel-Data Input, 622Mbps Positive LVDS Parallel-Data Input, 622Mbps Parallel System Loopback Enable. When this TTL input is forced low, the LVDS parallel inputs route through the elastic store to the LVDS parallel outputs. This bypasses the highspeed mux and demux. An internal 15k pull-up resistor pulls PLBEN high for normal operation. Negative LVDS Reference Clock Input, 155.52MHz Positive LVDS Reference Clock Input, 155.52MHz
7
TEST
8 9 11 12 14 15 18-23, 26, 27 30 31 33 34, 36, 39, 41 35, 37, 40, 42 44, 46, 50, 52 45, 47, 51, 53
SDI+ SDISCLKI+ SCLKIPCLKOPCLKO+ N.C. RSETFR LOF TRIEN PDO4- to PDO1PDO4+ to PDO1+ PDI4- to PDI1PDI4+ to PDI1+
54
PLBEN
56 57
RCLKIRCLKI+
6
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+3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator
Pin Description (continued)
PIN 58 61 62 EP NAME RSETES FILFIL+ Exposed Paddle FUNCTION Elastic Store Reset. The elastic buffer is centered on a rising edge of RSETES, maximizing the elastic store range. Data must be present for 10s before applying a pulse of at least 10ns. An internal 15k pull-up resistor pulls RSETES high for normal operation. Negative PLL Filter Capacitor Input. Connect a 0.33F capacitor between FIL+ and FIL-. Positive PLL Filter Capacitor Input. Connect a 0.33F capacitor between FIL+ and FIL-. Ground. This must be soldered to a circuit board for proper thermal performance (see Package Information).
MAX3831/MAX3832
_______________Detailed Description
The MAX3831/MAX3832 use a 4:1 mux and 1:4 demux with an elastic store buffer to simplify SDH/SONET interconnect I/O routing. The 622Mbps low-voltage differential signal (LVDS) parallel inputs pass through the 10-bit elastic store buffer, which accommodates 7.5ns skew on any single input relative to the 155MHz reference clock input RCLKI. This reference clock is required to synthesize the internal 2.488GHz clock used to drive the elastic store and 4:1 multiplexer. All TTL and LVDS outputs can be placed in a high-impedance state. See Figure 4 for a functional diagram. The 4:1 mux bit-interleaves the parallel data, providing a 2.488Gbps CML serial output to the optical or electrical driver. The CML serial input receives the 2.488Gbps data, the demux deinterleaves it to 622Mbps and sends the data to the frame detector. The frame detector monitors one 622Mbps channel and rolls the demux into the proper channel assignment. The MAX3831/MAX3832 include high-speed, built-in self-test (BIST), which also allows testing of the 622Mbps parallel-system loopback and the 2.488Gbps line loopback.
Due to the inherent uncertainty of the data transitions between the parallel-data inputs there is no bit or frame alignment between these inputs. However, the demux ensures proper channel assignment is maintained.
Bit-Interleaved Multiplexer/ Demultiplexer
The MAX3831/MAX3832 use a bit interleave/deinterleave mux/demux. To guarantee channel assignment, one of the four channels is inverted before multiplexing to provide a reference for the frame detector during demultiplexing. After demultiplexing, the same channel is inverted back to the original data format.
Frame Detector
After a 2.5Gbps serial data is bit deinterleaved into four 622Mbps channels, an SDH/SONET frame detector monitors the fourth channel, looking for the 32-bit pattern (A1A1A2A2) in the OC-12 header. To maintain correct channel assignment, the demux outputs rotate until this 32-bit overhead pattern is reliably detected. A lossof-frame output, LOF, indicates when the received data is in or out of frame. When LOF goes high, the frame pattern is detected and the demux outputs are correctly assigned. When LOF is low, the frame detection circuitry is searching for the correct frame. A RSETFR (TTL, active low) is included to reset the frame detector when necessary. The frame detector uses an algorithm to detect an inframe condition and a loss-of-frame condition; this algorithm is implemented to meet the SONET in-frame and false-frame specs. The frame_search state will occur upon start-up or reset. In this state, the frame detector scans through the incoming serial data searching for the framing pattern in the channel 4 output of the demux. While in this state, if the framing pattern is not found within 250s, the demux channels are shifted (rolled) and the frame search continues (Figure 6). In-frame will be declared if two consecutive framing patterns are found at the correct byte locations within the SONET frame (9720 bytes). If this pattern is not pre7
Elastic Store Buffer
Each parallel-data input, PDI1 to PDI4, passes through its respective 10-bit elastic store buffer. Following an elastic store reset, this buffer accommodates 7.5ns of skew on any input relative to the 155MHz reference clock. Figure 5 illustrates the elastic store buffer relationship with RCLKI. The Elastic Store Range graph in the Typical Operating Characteristics shows the amount of data skew tolerated. Following a 10s power-up period, the locations of the individual data-channel bit transitions are acquired, guaranteeing data preservation. The output of this block passes directly into the 4:1 mux. After power-up, the elastic store buffer must be reset by applying a low pulse on RSETES for at least 10ns.
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+3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator MAX3831/MAX3832
TEST (155MHz) RCLKI+ RCLKILVDS PATTERN GENERATOR 622MHz RSETES 155MHz FREQUENCY GENERATOR 2.488GHz CK PDI1+ PDI1PDI2+ PDI2PDI3+ PDI3PDI4+ PDI4PDO1+ PDO1PDO2+ PDO2PDO3+ PDO3PDO4+ PDO4PLBEN PCLKO+ PCLKOLVDS LVDS FRAME DETECTOR LVDS CK ROTATE 622MHz CLOCK GENERATOR 2.488GHz SCLKI+ SCLKILVDS LVDS D 1:4 DEMUX 2.488Gbps SDI+ SDILVDS 622Mbps PARALLEL LOOPBACK LVDS ES TEST ES LVDS ES SDO+ ES LVDS LINE LOOPBACK 2.488Gbps SYSTEM LOOPBACK 4:1 MUX SDOFIL+ FILTRIEN
MAX3831 MAX3832
LBEN
*
RSETFR LOF
*MAX3831: fPCLKO = 622MHz, MAX3832: fPCLKO = 155MHz
Figure 4. Functional Diagram
DATA INPUT PDI1 PDI2 PDI3 PDI4 RSETES 10ns RCLKI +tes PDI1 PDI2 PDI3 PDI4 -tes C0 D0 C1 D1 B1 A0 B2 A1 DATA OUTPUT OF ELASTIC STORE AT t > to A0 B1 C0 D1 B0 C0 D0 A0 B1 C1 D1 A1 B2 DATA OUTPUT OF ELASTIC STORE AT t = to A0 B1 C0 D1
sent at the correct location (false frame), the state machine will return to the frame_search state described above. While in the in_frame state, each frame will be checked for a framing pattern at the correct location. Four consecutive false frames will cause the state machine to return to the frame_search state described above. The false-frame counter is reset with three or fewer consecutive false frames.
Built-In Self-Test with On-Chip Serial Loopback
An on-chip pattern generator can be enabled to produce a 622Mbps SDH/SONET-like transport overhead followed by a pseudorandom bit sequence. This consists of 12 A1s, 12 A2s, and a pseudorandom bit stream (PRBS = 27 - 1). When TEST is low, this pattern is distributed to all parallel inputs, bypassing the LVDS input buffers. Note, this pattern is skewed by one 622MHz
Figure 5. Example of Elastic Store Function 8 _______________________________________________________________________________________
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator MAX3831/MAX3832
FRAME DETECT
START-UP OR RESET START 250s TIMER
FRAME_SEARCH NO TIMER TIMED OUT? YES ROLL DATA
LOF = 0
FRAME PATTERN DETECTED? YES 1 FRAME DETECTED
NO
RESET BYTE AND FRAME
FRAME PATTERN DETECTED? YES
NO
NO FRAME PATTERN DETECTED? NO YES
IN_FRAME
LOF = 1
FRAME PATTERN DETECTED? NO
YES
FRAME PATTERN DETECTED? YES
NO
FRAME PATTERN DETECTED?
YES
Figure 6. Frame Detection Flow Diagram _______________________________________________________________________________________ 9
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator MAX3831/MAX3832
clock cycle between each channel. In this test mode, serial data is internally looped back to the demux. All frame detect logic is exercised using this mode. The CML inputs (SDI and SCLKI) and LVDS inputs (PDI_) are ignored in this mode. After the BIST mode is enabled, the loss-of-frame flag LOF goes high, indicating that the selftest has passed. In normal operation, TEST is left open (internally pulled high), disabling the pattern generator and accepting data from the parallel input channels.
VCC VCC
50
50 SDO+ SDI+
50
50
Test Loopbacks
Two additional test loopbacks are provided: parallel system loopback and serial line loopback. Parallel System Loopback In parallel system loopback, four 622Mbps parallel input channels are phase aligned by an associated 10bit elastic store and routed to the output LVDS buffers. This loopback is controlled by setting PLBEN low. Normal data transmission is resumed when PLBEN goes high (internally pulled high). Serial Line Loopback Serial line loopback is used for testing the performance of the optical transceiver and the transmission link. The received 2.488Gbps data stream is routed to the transmit CML output buffer. Line loopback is enabled when LBEN is asserted low. When LBEN is left open (internally pulled high), normal serial-data transmission resumes.
SDOSDI-
MAX3876
MAX3831 MAX3832
Figure 7. CML-to-CML Interface
__________Applications Information
Low-Voltage Differential Signal Inputs/Outputs
The MAX3831/MAX3832 have LVDS inputs and outputs for interfacing with high-speed digital circuitry. All LVDS inputs and outputs are compatible with the IEEE-1596.3 LVDS specification. This technology uses 250mV to 400mV differential low-voltage amplitudes to achieve fast transition times, minimize power dissipation, and improve noise immunity. For proper operation, the parallel clock and data LVDS outputs (PCLKO+, PCLKO-, PDO_+, PDO_-) require 100 differential DC termination between the inverting and noninverting outputs. Do not terminate these outputs to ground. The parallel-data LVDS inputs (PDI_+, PDI_-) are internally terminated with 100 differential input resistance and therefore do not require external termination.
LVDS Parallel Interface
The MAX3831 parallel interface includes four OC-12 data inputs, a 155MHz reference clock input, four 622Mbps parallel-data outputs, and a 622MHz parallelclock output (MAX3832, fPCLKO = 155MHz). All parallel inputs and outputs are LVDS compatible to minimize power dissipation, speed transition time, and improve noise immunity. The 155MHz input signal at RCLKI requires a duty cycle between 40% and 60%. The LVDS outputs go into a high-impedance state when TRIEN is forced low. This simplifies system checks by allowing vectors to be forced on the LVDS outputs.
CML Serial Interface
The MAX3831/MAX3832 provide a 2.488Gbps serialdata stream to a driver and accept 2.488Gbps serial data and a 2.488GHz clock signal from an external clock and data recovery device (MAX3876). The highspeed interface is CML compatible, resulting in lower system power dissipation and excellent performance (Figure 7).
Interfacing with PECL/ECL Input Levels
When interfacing with differential PECL input levels, it is important to attenuate the signal while still maintaining 50 termination (Figures 8 and 9). Observe the common-mode input voltage specifications. AC-coupling is required if a VCC other than 3.3V is used to maintain the input common-mode level (Figure 8).
10
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+3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator MAX3831/MAX3832
VCC VCC = 3.3V VCC = 3.3V
50 0.1F PECL LEVELS RT* 100 0.1F 25 SDI25 SDI+
50 50 82 SDI+ 50
82 PECL OUTPUT 82
82
SDI-
RT*
MAX3831 MAX3832
MAX3831 MAX3832
*SELECT RT SUCH THAT THE CORRECT PECL COMMON-MODE LEVEL IS ACHIEVED (TYPICAL PECL OUTPUT CURRENT = 14mA).
Figure 8. PECL-to-CML Interface
Figure 9. Direct Coupling of a PECL Output into the MAX3831/ MAX3832
Layout Techniques
For best performance, use good high-frequency layout techniques. Filter voltage supplies, keep ground connections short, and use multiple vias where possible. Use controlled-impedance transmission lines to interface with the MAX3831/MAX3832 high-speed inputs and outputs. Place power-supply decoupling as close to VCC as possible. To reduce feedthrough, take care to isolate the input signals from the output signals.
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11
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator MAX3831/MAX3832
Pin Configuration
RSETES RCLKI+ RCLKIPLBEN PDI1+ PDI2+ PDI1PDI2GND GND
TOP VIEW
64
63 62 61 60 59 58
57 56 55 54 53 52 51 50 49
GND VCC SDOSDO+ VCC LBEN TEST SDI+ SDI-
GND
48 GND 47 PDI3+ 46 PDI345 PDI4+ 44 PDI443 GND 42 PDO1+ 41 PDO140 PDO2+ 39 PDO238 VCC 37 PDO3+ 36 PDO335 PDO4+ 34 PDO433 TRIEN
FIL+
FIL-
VCC
VCC
1 2 3 4 5 6 7 8 9
VCC 10 SCLKI+ 11 SCLKI- 12 VCC 13 PCLKO- 14 PCLKO+ 15 GND 16
MAX3831 MAX3832
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VCC
N.C.
N.C.
RSETFR
N.C.
N.C.
N.C.
N.C.
GND
N.C.
N.C.
GND
GND
LOF
TQFP-EP
___________________Chip Information
TRANSISTOR COUNT: 14,134
12
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GND
VCC
VCC
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator
Package Information
64L, TQFP.EPS
MAX3831/MAX3832
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13
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator MAX3831/MAX3832
Package Information (continued)
14
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+3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator MAX3831/MAX3832
NOTES
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15
+3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator MAX3831/MAX3832
NOTES
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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