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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4006B MSI 18-stage static shift register Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification 18-stage static shift register DESCRIPTION The HEF4006B is an 18-stage shift register arranged as two 4-stage and two 5-stage shift registers with a common clock input (CP). The two 4-stage shift registers each have a data input (DA, DB) and a data output (O3A, O3B); the two HEF4006B MSI 5-stage shift registers each have a data input (DC, DD) and data outputs from the fourth and fifth stages (O3C, O4C, O3D, O4D). The registers can be operated in parallel or interconnected to form a single shift register of up to 18 bits. Data are shifted into the first register position of each register from the data inputs (DA to DD) and all the data in each register are shifted one position to the right on the HIGH to LOW transition of CP. Fig.2 Pinning diagram. HEF4006BP(N): HEF4006BD(F): HEF4006BT(D): Fig.1 Functional diagram. 14-lead DIL; plastic (SOT27-1) 14-lead DIL; ceramic (cerdip) (SOT73) 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America FUNCTION TABLE Dn D1 X Notes 1. X = state is immaterial 2. 3. = positive-going transition = negative-going transition CP On(5) D1 no change PINNING DA to DD CP data inputs clock input (HIGH to LOW; edge-triggered) O3A to O3D; O4C; O4D data outputs FAMILY DATA, IDD LIMITS category MSI See Family Specifications 4. D1 = either HIGH or LOW 5. The moment D1 appears at O depends on the register length. January 1995 2 Philips Semiconductors Product specification 18-stage static shift register HEF4006B MSI Fig.3 Logic diagram. January 1995 3 Philips Semiconductors Product specification 18-stage static shift register AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays CP On HIGH to LOW 5 10 15 5 LOW to HIGH Output transition times HIGH to LOW 10 15 5 10 15 5 LOW to HIGH Minimum clock pulse width; HIGH Set-up time Dn CP Hold time Dn CP Maximum clock pulse frequency 10 15 5 10 15 5 10 15 5 10 15 5 10 15 fmax thold tsu tWCPH 60 40 30 20 10 5 5 5 5 9 15 18 tTLH tTHL tPLH tPHL 90 40 30 90 40 35 60 30 20 60 30 20 30 20 15 10 5 0 -5 0 0 18 30 36 180 80 60 180 85 70 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz SYMBOL MIN TYP MAX HEF4006B MSI TYPICAL EXTRAPOLATION FORMULA 63 ns + (0,55 ns/pF) CL 29 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 63 ns + (0,55 ns/pF) CL 29 ns + (0,23 ns/pF) CL 27 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL see also waveforms Fig.4 VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (W) 600 fi + (foCL) x VDD2 3200 fi + (foCL) x VDD 11 600 fi + (foCL) x 2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V) VDD2 January 1995 4 Philips Semiconductors Product specification 18-stage static shift register HEF4006B MSI Fig.4 Waveforms showing minimum clock pulse width, and set-up and hold-times for Dn to CP. Set-up and hold times are shown as positive values but may be specified as negative values. January 1995 5 |
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