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CXA2543R
Decoder/Driver/Timing Generator for Color LCD Panels
Description The CXA2543R is an IC designed exclusively to drive the color LCD panel DCX501BK and LCX018AK. This IC greatly reduces the number of circuits and parts required to drive LCD panels by incorporating RGB decoder functions for video signals, driver functions, and a timing generator for driving panels onto a single chip. This chip has a built-in serial interface circuit and electronic attenuators which allow various mode settings and adjustments to be performed through direct control from an external microcomputer, etc. Features * Color LCD panel DCX501BK and LCX018AK driver * Supports NTSC and PAL signals * Supports 16:9 wide display * Supports composite inputs, Y/C inputs and Y/color difference inputs * Serial interface circuit * Electronic attenuators (D/A converter) * BPF, trap and delay line * Sharpness function * 2-point correction circuit * R, G, B signal delay time adjustment circuit * Polarity inversion circuit (line inverted mode) * Supports external RGB input * Supports AC drive for LCD panel during no signal Applications * Compact LCD monitors * LCD viewfinders * Compact liquid crystal projectors, etc. Structure Bipolar CMOS IC 64 pin LQFP (Plastic)
Absolute Maximum Ratings (Ta = 25C) * Supply voltage VCC1 - GND1 6 VCC2 - GND2 14 VCC3 - GND3 14 VDD1 - VSS1 4.5 VDD1 - VSS2 4.5 * * * * *
V V V V
V Analog input pin voltage VINA -0.3 to VCC V Digital input pin voltage VIND -0.3 to VDD1 + 0.3 V Operating temperature Topr -15 to +75 C Storage temperature Tstg -40 to +125 C Allowable power dissipation1 PD (Ta 75C) 350 mW
Operating conditions Supply voltage VCC1 - GND1 VCC2 - GND2 VCC3 - GND3 VDD1 - VSS1 VDD1 - VSS2
4.25 to 5.25 11.0 to 13.5 11.0 to 13.5 2.7 to 3.6 2.7 to 3.6
V V V V V
1 With substrate Size: 30 x 30 x 1.6mm Material: Glass fabric base epoxy
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E98403-PS
CXA2543R
Block Diagram
R OUT
G OUT
B OUT
GND2
GND3
FB PSIG
LOAD
DATA
FB G
VCC3
PSIG
48 +12V
47
46
45
44
43 GND2
42
41
40 +12V
39
38 GND3
37
36
35
34
33
Buf VCC1 49 +4.5V Buf Buf Buf Buf SERIAL BUS I/F POL SW PSIG-BRT CLAMP R-Y IN 52 EXT COLOR & BALANCE C OUT 53 COLOR HUE INT/EXT BLK LIM 54 APC APC 55 VXO HUE HUE COLOR COLOR CONT CONTRAST VXO IN 57 ACC DET V REG 58 REG. KILLER C IN 59 BPF EXT SW 22 PCG PIC CONT HAFC PLL-COUNTER & DECODER CONTRAST RGB -1 GAMMA -2 D/A HD 23 HD 24 FLD IN PS LPF B-BRT BRIGHT BRIGHT VWIN PALSW VXO OUT 56 MATRIX S/H 25 XVST VPAL 26 VST PAL ID DEMOD PAL SW R-BRT SUBBRIGHT POL SW VGATE WIDE VTST 29 XEN PSIGBRIGHT 32 VD
SIG. CENTER 50
SCLK
VCC2
FB R
FB B
RGT
VSS2 31 VSS2
B-Y IN 51
30 EN
FRP
28 VCK1
27 VCK2
TEST3 60
ACC AMP FILT ADJ
21 XPCG
Y IN 61
CLP BGP SBLK V SEP
HCNT H-PULSE
20 HCK1
PIC 62
19 HCK2 HGATE H-SKEW DET PD
F0 ADJ 63
CLAMP
TRAP
DL1
18 HST
SYNC SEP 17 XHST
PWRST 64 H. FILTER
GND1 1 2 3 4 5 6 7 8 9 10 11 12
VSS1 13 14 15
+3V 16
EXT G
EXT R
EXT B
TRAP
S.SEP IN
TEST2
RPD
H.FIL OUT
TEST1
SYNC IN
VD IN
GND1
-2-
VDD1
VSS1
CKO
CKI
CXA2543R
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Symbol TRAP GND1 SYNC IN H.FIL OUT S.SEP IN EXT R EXT G EXT B VD IN TEST1 TEST2 RPD VSS1 CKI CKO VDD1 XHST HST HCK2 HCK1 XPCG PCG HD FLD IN XVST VST VCK2 VCK1 XEN EN VSS2 VD O O O O O O O O I O O O O O O I O O I O I I I I I I/O External trap connection Analog (4.5V) GND Video input for sync separation Video output for sync input Sync separation circuit input External digital input R External digital input G External digital input B External vertical sync input Test (Leave this pin open.) Test (Leave this pin open.) Phase comparator output Digital (3V) GND for oscillation cell Oscillation cell input Oscillation cell output Digital 3V power supply XH start pulse output (HST reversed polarity) H start pulse output H clock pulse 2 output H clock pulse 1 output XPCG pulse output (PCG reversed polarity) PCG pulse output HD pulse output Field identification input XV start pulse output (VST reversed polarity) V start pulse output V clock pulse 2 output V clock pulse 1 output XEN pulse output (EN reversed polarity) EN pulse output Digital (3V) GND VD pulse output (H: Pull up) H H Description
Input pin for open status
-3-
CXA2543R
Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Symbol SCLK DATA LOAD RGT FB PSIG GND3 PSIG VCC3 B OUT FB B GND2 G OUT FB G R OUT FB R VCC2 VCC1 SIG.CENTER B-Y IN R-Y IN C OUT BLK LIM APC VXO OUT VXO IN V REG C IN TEST3 Y IN PIC F0 ADJ PWRST
I/O I I I I O Serial interface clock input Serial interface data input Serial interface load input
Description
Input pin for open status
H H H H
Switches between Normal scan (H) and Reverse scan (L) PSIG signal DC voltage feedback circuit capacitor connection Analog (12V) GND for PSIG
O
PSIG output Analog 12V power supply for PSIG
O O
B signal output B signal DC voltage feedback circuit capacitor connection Analog (12V) GND
O O O O
G signal output G signal DC voltage feedback circuit capacitor connection R signal output R signal DC voltage feedback circuit capacitor connection Analog 12V power supply Analog 4.5V power supply
I I I O I O O I O I I I I O --
R, G, B and PSIG output DC voltage adjustment B-Y demodulator input (or B-Y color difference signal input) R-Y demodulator input (or R-Y color difference signal input) Chroma signal output Black peak limiter level adjustment APC detective filter connection VXO output VXO input Constant voltage capacitor connection Chroma signal input Test (Connect to GND.) Y signal input Y signal frequency response adjustment Internal filter adjusting resistor connection System reset (H: Pull up)
-4-
CXA2543R
Analog Block Pin Description Pin No. Symbol Pin voltage Equivalent circuit Description
VCC1 70A 1k
1
TRAP
--
300 1 130A GND1
External trap connection. Connect the trap between this pin and GND to remove the chroma component. Leave this pin open when using Y/C and Y/color difference input.
2
GND1
0V
VDD1 1k 1k 2.1V
Analog (4.5V) GND.
3
SYNC IN
1.5V
3
30A GND1
Sync input. Normally inputs the Y signal. The standard signal input level is 0.5Vp-p (100% white level from the sync tip).
VDD1 20k
4
H.FIL OUT
0.8V
4
Outputs the video signal for input to the sync separation circuit.
20k
GND1
VDD1
17k
5
S.SEP IN
2.1V
5
Sync separation circuit input. Input the H.FIL OUT (4pin) signal.
1.8V 2.8V
10A GND1
-5-
CXA2543R
Pin No. 6
Symbol
Pin voltage
Equivalent circuit
Description External digital signal inputs. There are two threshold values: Vth1 (= 1.0V) and Vth2 (= 2.0V). When one of the RGB signals exceeds Vth1, all of the RGB outputs go to black level; when an input exceeds Vth2, only the corresponding output goes to white level.
EXT-R
VCC1 30A 6 300
7
EXT-G
--
7 8 50k 2.7V GND1
8
EXT-B
37
FB PSIG
VCC1
42
FB B
37
2.0V 45 FB G
1k
42 45 47 GND2
Smoothing capacitor connection for the feedback circuit of R, G, B and PSIG output DC level control. Use a low-leakage capacitor because of high impedance.
47 38
FB GR GND3 0V
VCC3
Analog (12V) GND for the PSIG circuit.
39
PSIG
VCC2 2
39 10
PSIG signal outputs.
GND3
40
VCC3
12V
12V power supply for the PSIG circuit.
41
B OUT
VCC2
44
G OUT
VCC2 2
41 44 46
20
RGB signal outputs.
20 40A
46 43
R OUT GND2 0V
GND2
Analog (12V) GND. -6-
CXA2543R
Pin No. 48 49
Symbol VCC2 VCC1
Pin voltage 12V 4.5V
VCC2
Equivalent circuit
Description 12V power supply. 4.5V power supply.
150k
50
SIG. CENTER
6.0V
300 50 150k GND2
RGB output DC voltage control. When used with a VCC2 and VCC3 of 12V or more, apply 6V from an external source.
VCC1
51
B-Y IN
51 500 500 10k
--
52
52
R-Y IN
GND1
30A
50A
Color difference demodulation circuit inputs. Color difference signal is input when using Y/color difference input. At this time, the standard signal input level is 0.3Vp-p and the clamp level is approximately 2.8V. Pin 53 signal is input in other modes (except D-PAL). At this time, the DC level is approximately 1.6V.
VCC1
53
C OUT
1.6V
53 350A GND1
Color adjusted chroma signal output. The burst level is 180mVp-p (typ.). (540mVp-p during D-PAL.) Leave this pin open when using Y/color difference input.
VCC1 50k 50k
54
BLK LIM
--
54
Sets the RGB output amplitude (black-black) clip level and the blanking black level for during wide display.
GND1
D-PAL is a demodulation method that uses an external delay line during demodulation; S-PAL is a demodulation method that internally processes chroma demodulation.
-7-
CXA2543R
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description
VCC1
55
APC
2.7V
1k 55
APC detective filter connection. Leave this pin open when using Y/color difference input.
GND1
VCC1
56
VXO OUT
2.9V
56 400A GND1
VXO output. Leave this pin open when using Y/color difference input.
VCC1
500
57
VXO IN
3.2V
57 2.4k 3.2V GND1
VXO input. Leave this pin open when using Y/color difference input.
VCC1
58
V REG
3.6V
58
60k
30k GND1
Smoothing capacitor connection for the internally generated constant voltage source circuit. Connect a capacitor of 1F or more.
VCC1
500 15p
59
C IN
--
59 20k 30A GND1
Video signal input when using composite input. Chroma signal input when using Y/C signal input. Leave this pin open when using Y/color difference input.
-8-
CXA2543R
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description
VCC1
1k
61
Y IN
3.1V
61
70A GND1
Y signal input. The standard signal input level is 0.5Vp-p (100% white level from the sync tip). Input at low impedance (75 or less).
VCC1 20k 30k
62
PIC
--
62
10k BIAS 50A 50A
Adjusts frequency response of luminance signal. Increasing the voltage emphasizes contours.
GND1
VCC1 1k
63
F0 ADJ
3.0V
63
15A GND1
Connect resistance of 15k between this pin and GND1 to adjust the internal filters using the outflow current value. Connect to +4.5V power supply when using Y/C or Y/color difference input.
VDD1 2A 64
64
PWRST
--
1k
TG block system reset pin. The system is reset when this pin is connected to GND. Connect a capacitor between this pin and GND.
GND1
-9-
CXA2543R
Setting Conditions for Measuring Electrical Characteristics Use the electrical characteristics measurement circuit on page 30 when measuring electrical characteristics. Also, the TG (timing generator) block must be initialized by performing Settings 1 and 2 below. Setting 1. System reset After turning on the power, set SW64 to ON and start up V64 from GND in order to activate the TG block system reset. (See Fig. 1-1.) The serial bus will be set to default values. Setting 2. Horizontal AFC adjustment Input SIG5 (VL = 0mV) to (A) and adjust V14 so that WL and WH of the TP12 output waveform are the same. (See Fig. 1-2.) Note) When measuring a band of 2MHz or more for Y signal frequency response or sharpness response among the items being measured, the measurement must be made with sample-and-hold timing (serial bus) set to through (sample-and- hold not performed).
VDD
SIG5 WS
V64 (PWRST) TR TR > 10s TP12 WL WH WL = WH
Fig. 1-1. System reset
Fig. 1-2. Horizontal AFC adjustment
- 10 -
CXA2543R
Electrical Characteristics -- DC Characteristics Unless otherwise specified, Settings 1 and 2 and the following setting conditions are required. VCC1 = 4.5V, VCC2 = 12.0V, VCC3 = 12.0V, GND1 = GND2 = GND3 = 0V, VDD1 = 3.0V, VSS1 = VSS2 = 0V, Ta = 25C SW54, SW62, SW64 = ON SW6, SW7, SW8, SW59 = A SW51, SW52 = B V54 = 0V, V62 = 2.2V Set the serial bus registers to the "Serial Bus Register Initial Settings". Unspecified the serial bus registers should be set to default settings.
Item Symbol Conditions Min. Typ. Max. Unit
Power supply characteristics ICC11 Input SIG4 to (A) and SIG2 (0dB) to (B). Measure the ICC1 current value. COMP input mode Input SIG4 to (A) and SIG2 (0dB) to (B). Measure the ICC1 current value. Y/C input mode Input SIG4 to (A), (D) and (E). Measure the ICC1 current value. SW51, SW52 = A, SW59 = B Y/color difference input mode Input SIG4 to (A) and SIG2 (0dB) to (B). Measure the ICC2 current value. PSIG load capacity CLP = 0pF Input SIG4 to (A) and SIG2 (0dB) to (B). Adjust PSIG-BRT of the serial bus and measure the ICC2 current value when TP39 output is set to 5Vp-p. PSIG load capacity CLP = 10000pF Input SIG4 to (A) and SIG2 (0dB) to (B). Measure the IDD current value. DCX501 and LCX018 (4:3) mode Input SIG4 to (A) and SIG2 (0dB) to (B). Measure the IDD current value. LCX018 (16:9) mode 23 30 37 mA
Current consumption VCC1
ICC12
21
28
35
mA
ICC13
17
23
29
mA
ICC2A Current consumption VCC2, 3 ICC2B
6
8
10
mA
6
8.3
10.5
mA
IDD1 Current consumption VDD IDD2
6
8
10
mA
7.5
10
12.5
mA
- 11 -
CXA2543R
Item
Symbol
Conditions Digital block input pin1 Digital block input pin1 Input pin with pull-up resistor2 VIN = VSS2 VIN = VSS VIN = VDD1 IOH = -1mA3
Min.
Typ.
Max.
Unit
Digital block I/O characteristics Low level input voltage High level input voltage Input current CKI pin low input current CKI pin high input current High level output voltage Output pins except CKO and RPD Low level output voltage Output pins except CKO and RPD High level output voltage CKO pin Low level output voltage CKO pin High level output voltage RPD pin Low level output voltage RPD pin Output off leak current RPD pin VIL VIH II1 II2 II3 VOH1 0.3VDD 0.7VDD -145 -10 10 2.8 -60 -24 V V A A A V
VOL1
IOL = 1mA3
0.3
V
VOH2 VOL2 VOH3 VOL3 IOFF
IOH = -3mA IOL = 3mA IOH = -0.5mA IOL = 0.7mA High impedance status VOUT = VSS or VOUT = VDD1
0.5VDD 0.5VDD VDD - 1.2 1.0 -40 40
V V V V A
1 Digital block input pins: SCLK, DATA, LOAD, VDIN, RGT, FLDIN, CKI 2 Input pins with pull-up resistors: SCLK, DATA, LOAD, VDIN, RGT, FLDIN 3 Output pins except CKO and RPD: XHST, HST, HCK1, HCK2, XPCG, PCG, HD, XVST, VST, VCK1, VCK2, XEN, EN, VD
- 12 -
CXA2543R
Electrical Characteristics -- AC Characteristics Unless otherwise specified, Settings 1 and 2 and the following setting conditions are required. VCC1 = 4.5V, VCC2 = 12.0V, VCC3 = 12.0V, GND1 = GND2 = GND3 = 0V, VDD1 = 3.0V, VSS1 = VSS2 = 0V, Ta = 25C SW54, SW62, SW64 = ON SW6, SW7, SW8 = A SW51, SW52, SW59 = B V54 = 0V, V62 = 2.2V Set the serial bus registers to the "Serial Bus Register Initial Values". Unspecified serial bus registers should be set to default settings. Unless otherwise specified, measure the non-inverted outputs for TP41, TP44 and TP46.
Item Y signal block Video maximum gain Contrast characteristics TYP Contrast characteristics MIN GV GCNTTP GCNTMN FCYYC Y signal frequency response 1 FCYCMN FCYCMP Input SIG4 to (A) and measure the ratio between the output amplitude (white-black) and input amplitude at TP44. Input SIG4 to (A) and measure the ratio between the output amplitude (white-black) and input amplitude at TP44. Input SIG4 to (A) and measure the ratio between the output amplitude (white-black) and input amplitude at TP44. Assume the output amplitude at TP44 when SIG7 (0dB, no burst, 100kHz) is input to (A) as 0dB. Vary the frequency of the input signal to obtain the frequency with an output amplitude of -3dB. V62 = 1.5V Y/C input Composite input (NTSC) Composite input (PAL) 19 13 -9 5.0 2.5 3.0 22 17 -5 25 21 -1 dB dB dB MHz MHz MHz Symbol Conditions Min. Typ. Max. Unit
Y signal frequency response 2
FCL
Assume the output amplitude at TP44 when SIG7 (0dB, no burst, 100kHz) is input to (A) as 0dB. Vary the frequency of the input signal to obtain the frequency with an output amplitude of -3dB. V62 = 1.5V, Load 500pF Assume the output amplitude at TP44 when SIG7 (100kHz) is input to (A) as 0dB. Set SIG7 to 2.5MHz and measure GSHP1X and GSHP1N as the amounts by which the output amplitude at TP44 changes when V62 = 4V and 0V, respectively. Assume the output amplitude at TP44 when SIG7 (100kHz) is input to (A) as 0dB. Set SIG7 to 2.0MHz and measure GSHP2X and GSHP2N as the amounts by which the output amplitude at TP44 changes when V62 = 4V and 0V, respectively. Input SIG2 (0dB) to (A). Using a spectrum analyzer, measure the input and the 3.58MHz or 4.43MHz component of TP44, and obtain CRLEKY = 150mV x 10 CLK/20 using their difference CLK. Input SIG9 (VL = 150mV) to (A). Measure the delay time from the 2T pulse peak of the input signal to the peak of the non-inverted output at TP44. Y/C input Composite input (NTSC) Composite input (PAL)
5.0
MHz
Picture quality adjustment variable amount 1 (Y/C input) Picture quality adjustment variable amount 2 (composite input)
GSHP1X GSHP1N GSHP2X GSHP2N
10
14 -2 0
dB dB dB -2 dB
6
9 -4
Carrier leak (residual carrier)
CRLEKY
30
mV
TDYYC Y signal I/O delay time TDYCMN TDYCMP
250 570 570
350 670 670
450 770 770
ns ns ns
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CXA2543R
Item Chroma signal block
Symbol
Conditions
Min.
Typ.
Max.
Unit
ACC amplitude characteristics 1
ACC1
ACC amplitude characteristics 2
ACC2
Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB/+6dB/-20dB, 3.58MHz burst/chroma phase = 180, or 4.43MHz burst/chroma phase = 135) to (B). Measure the output amplitude at TP53, assuming the output corresponding to 0dB, +6dB and -20dB as V0, V1 and V2, respectively. ACC1 = 20 log (V1/V0) ACC2 = 20 log (V2/V0) SW59 = A Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, 3.58MHz burst/chroma phase = 180, or 4.43MHz burst/chroma phase = 135) to (B). Changing the SIG2 burst frequency, measure the frequency f1 at which the TP44 output appears (the killer mode is canceled). NTSC: FAPCN = f1 - 3579545Hz PAL: FAPCP = f1 - 4433619Hz SW59 = A
NTSC
-3
0
3
dB
PAL
-3
0
3
dB
NTSC
-4
-1
2
dB dB
PAL
-4
-1
2
FAPCN
NTSC
500
Hz
APC pull-in range
FAPCP
PAL
500
Hz
Color adjustment characteristics MAX Color adjustment characteristics MIN HUE adjustment range MAX HUE adjustment range MIN
GCOLMX
GCOLMN
Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, 3.58MHz burst/chroma phase = 180) to (B). Assume the chroma output amplitude when serial bus register COLOR = 80H, 0FFH and 0H as V0, V1 and V2, respectively. GCOLMX = 20 log (V1/V0) GCOLMN = 20 log (V2/V0) SW59 = A Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, burst/chroma phase variable) to (B). Assume the phase at which the output amplitude at TP44 reaches a minimum when serial bus register HUE = 80H, 0FFH and 0H as 0, 1 and 2, respectively. HUEMX = 1 - 0 HUEMN = 2 - 0 SW59 = A Input SIG5 (VL = 150mV) to (A) and SIG2 (level variable, 3.58MHz burst/chroma phase = 180, or 4.43MHz burst/chroma phase = 135) to (B), and measure the output amplitude at TP44. Gradually reduce the SIG3 amplitude level and measure the level at which the killer operation is activated. SW59 = A
4
6
dB
-25
-15
dB
HUEMX
-30
-40
deg
HUEMN
30
60
deg
ACKN Killer operation input level ACKP
NTSC
-37
-31
dB
PAL
-34
-28
dB
- 14 -
CXA2543R
Item
Symbol VRBN
Conditions Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, 3.58MHz) to (B) and change the chroma phase. Assume the maximum amplitude at TP41 as VB, the maximum amplitude at TP44 as VG, and the maximum amplitude at TP46 as VR. VRBN = VR/VB, VGBN = VG/VB SW59 = A Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, 3.58MHz) to (B) and change the chroma phase. Assume the phase at which the amplitude at TP41, TP44 and TP46 reaches a maximum as B, G and R, respectively. RBN = R - B, GBN = G - B SW59 = A Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, 4.43MHz) to (B) and change the chroma phase. Assume the maximum amplitude at TP41 as VB, the maximum amplitude at TP44 as VG, and the maximum amplitude at TP46 as VR. VRBP = VR/VB, VGBP = VG/VB SW59 = A Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, 4.43MHz) to (B) and change the chroma phase. Assume the phase at which the amplitude at TP41, TP44 and TP46 reaches a maximum as B, G and R, respectively. RBP = R - B, GBP = G - B SW59 = A Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB, 100kHz, no burst) to (D). Assume the output amplitude at TP41 (100kHz) when serial bus register COLOR = 80H as VC0, when COLOR = 0H as VC2, and when SIG1 is set to -10dB and COLOR = 0FFH as VC1. GEXCMX = 20 log (VC1/VC0) + 10 GEXCMN = 20 log (VC2/VC0) SW51, SW52 = A Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB, 100kHz, no burst) to (D) and (E). Assume the output amplitude at TP41 (100kHz) as VB and the output amplitude at TP46 (100kHz) as VR. VEXCBL = VR/VB SW51, SW52 = A Input SIG5 (VL = 150mV) to (A) and SIG1 (-6dB, 100kHz, no burst) to (D) and (E). Assume the output amplitude at TP46 (100kHz) and TP41 (100kHz) when serial bus register HUE = 80H as VR0 and VB0, respectively, when HUE = 0FFH as VR1 and VB1, respectively, and when HUE = 0H as VR2 and VB2, respectively. GEXRMX = 20 log (VR1/VR0) GEXRMN = 20 log (VR2/VR0) GEXBMX = 20 log (VB1/VB0) GEXBMN = 20 log (VB2/VB0) SW51, SW52 = A
Min. 0.53
Typ. 0.63
Max. 0.73
Unit
Demodulation output amplitude ratio (NTSC)
VGBN
0.25
0.32
0.39
RBN Demodulation output phase difference (NTSC)
99
109
119
deg
GBN
230
242
254
deg
Demodulation output amplitude ratio (PAL)
VRBP
0.65
0.75
0.85
VGBP
0.33
0.40
0.47
RBP Demodulation output phase difference (PAL)
80
90
100
deg
GBP
232
244
256
deg
Color difference input color adjustment characteristics MAX Color difference input color adjustment characteristics MIN
GEXCMX
4
6
dB
GEXCMN
-20
-15
dB
Color difference balance
VEXCBL
0.8
1.0
1.2
Color difference input balance adjustment R
GEXRMX
2
3
dB
GEXRMN
-3
-2
dB
Color difference input balance adjustment B
GEXBMX
-3
-2
dB
GEXBMN
2
3
dB
- 15 -
CXA2543R
Item
Symbol
Conditions Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB, 100kHz, no burst) to (D). Assume the output amplitude at TP41 (100kHz) as VEXB and the output amplitude at TP44 (100kHz) as VEXBG. VEXGBN = VEXBG/VEXB SW51, SW52 = A Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB, 100kHz, no burst) to (E). Assume the output amplitude at TP46 (100kHz) as VEXR and the output amplitude at TP44 (100kHz) as VEXRG. VEXGRN = VEXRG/VEXR SW51, SW52 = A Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB, 100kHz, no burst) to (D). Assume the output amplitude at TP41 (100kHz) as VEXB and the output amplitude at TP44 (100kHz) as VEXBG. VEXGBP = VEXBG/VEXB SW51, SW52 = A Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB, 100kHz, no burst) to (E). Assume the output amplitude at TP46 (100kHz) as VEXR and the output amplitude at TP44 (100kHz) as VEXRG. VEXGRP = VEXRG/VEXR SW51, SW52 = A
Min.
Typ.
Max.
Unit
VEXGBN G-Y matrix characteristics (NTSC) VEXGRN
0.22
0.25
0.28
0.47
0.53
0.58
VEXGBP G-Y matrix characteristics (PAL) VEXGRP
0.16
0.19
0.22
0.48
0.53
0.58
RGB signal output block RGB signal and PSIG output DC voltage Input SIG5 (VL = 0mV) to (A). Adjust serial bus register BRIGHT so that the output (black-black) at TP44 is 9Vp-p and measure the DC voltage at TP39, TP41, TP44 and TP46. Input SIG5 (VL = 0mV) to (A). Adjust serial bus register BRIGHT so that the output (black-black) at TP44 is 9Vp-p, measure the DC voltage at TP39, TP41, TP44 and TP46, and obtain the maximum difference between each of these values. Input SIG3 to (A). Vary V54 and measure the maximum value VLIMMX and minimum value VLIMMN of the voltage range (black-black) over which the black limiter operates for the TP39, TP41, TP44 and TP46 outputs. Assume the value whenV54 = 0V as VLIMMX, and when V54 = 4.5V as VLIMMN. Input SIG5 (VL = 0mV) to (A) and measure the output (black-black) at TP41, TP44 and TP46 when serial bus register BRIGHT = 0H. Input SIG5 (VL = 0mV) to (A) and measure the output (black-black) at TP41, TP44 and TP46 when serial bus register BRIGHT = 0FFH. 9.0
VOUT
5.85
6.00
6.15
V
RGB signal and PSIG output DC voltage difference
VOUT
0
100
mV
RGB and PSIG output limiter operation voltage
VLIMMX
Vp-p
VLIMMN
5.2
Vp-p
BRTMX Amount of change in brightness BRTMN
9.0
Vp-p
4.0
Vp-p
- 16 -
CXA2543R
Item
Symbol PSIGMX
Conditions Input SIG5 (VL = 0mV) to (A) and measure the output (black-black) at TP39 when serial bus register PSIG-BRT = 0H. Input SIG5 (VL = 0mV) to (A) and measure the output (black-black) at TP39 when serial bus register PSIG-BRT = 0FFH. Input SIG5 (VL = 0mV) to (A) and measure the difference between the outputs (black-black) at TP41 and TP46 and the output (black-black) at TP44 when serial bus registers R-BRT = B-BRT = 0H and when R-BRT = B-BRT = 0FFH. Input SIG4 to (A) and obtain the level difference between the maximum and minimum non-inverted output amplitudes (white-black) at TP41, TP44 and TP46. Input SIG4 to (A) and obtain the level difference between the non-inverted output amplitudes (white-black) and the inverted output amplitudes at TP41, TP44 and TP46. Input SIG4 to (A) and obtain the level difference between the maximum and minimum black levels of both the inverted and non-inverted outputs at TP41, TP44 and TP46. Input SIG8 to (A). Adjust the non-inverted output black level at TP44 to 6.0 - 4.5V with serial bus register BRIGHT and the non-inverted output amplitude (white-black) at TP44 to 3.5V with serial bus register CONTRAST. Measure VG1, VG2 and VG3. G 1 = 20 log (VG1/0.0357) G 2 = 20 log (VG2/0.0357) G 3 = 20 log (VG3/0.0357) (See Fig. 5 for definitions of VG1, VG2 and VG3.) Input SIG8 to (A) and adjust serial bus register BRIGHT so that the output at TP44 is 9Vp-p (black-black). Read the point where the gain of the non-inverted output at TP44 changes when serial bus register 1 = 0H and 0FFH from the input signal IRE level. V 1MN when 1 = 0H, and V 1MX when 1 = 0FFH. Input SIG8 to (A) and adjust serial bus register BRIGHT so that the output at TP44 is 9Vp-p (black-black). Read the point where the gain of the non-inverted output at TP44 changes when serial bus register 2 = 0H and 0FFH from the input signal IRE level. V 2MN when 2 = 0H, and V 2MX when 2 = 0FFH. Input SIG4 to (A) and adjust serial bus register PSIG-BRT so that the output at TP39 is 9Vp-p (black-black). Measure the time it takes to change to an amplitude of 9Vp-p. tPSIGH: rising edge, tPSIGL: falling edge Input SIG5 (VL = 350mV) to (A) and measure the voltage (whitewhite) at which the white limiter activates for inverted output and non-inverted output at TP41, TP44 and TP46, respectively. Input SIG5 (VL = 0mV) to (A) and adjust V54 so that the output at TP44 is 9Vp-p (black-black). Measure the DC voltage at TP41, TP44 and TP46 and obtain the difference versus the RGB output voltage VOUT.
Min.
Typ.
Max. 1.5
Unit Vp-p
Amount of change in PSIG PSIGMN
9.0
Vp-p
Amount of change in sub-brightness Difference in gain between RGB output signals
SBBRT
1.5
2.0
V
GRGB
-0.5
0
0.5
dB
Difference in RGB output inverted/non- GINV inverted gain Difference in black level potential between VBL RGB output signals G1 gain G2 G3
-0.5
0
0.5
dB
300
mV
23.0
26.0
29.0
dB
12.0
15.0
18.0
dB
18.0
21.0
25.0
dB
V 1MN 1 adjustment variable range V 1MX
0
IRE
100
IRE
V 2MN 2 adjustment variable range V 2MX
100
IRE
0
IRE
tPSIGH
PSIG transition time
1.5
3.0
s
tPSIGL
VWLIM
1.5
3.0
s
RGB output white limiter operation voltage Black limiter DC voltage difference
1.3
1.5
1.7
V
VBLIM
0
100
mV
- 17 -
CXA2543R
Item White limiter DC voltage difference
Symbol VWLIM
Conditions Input SIG5 (VL = 350mV) to (A). Measure the DC voltage at TP41, TP44 and TP46 and obtain the difference versus the RGB output voltage VOUT. Input SIG8 to (A). Assume the black limiter level of the output at TP41, TP44 and TP46 when serial bus register BRIGHT = 0H as VDRB and the white limiter level when BRIGHT = OFFH as VDRW. VDROFF = VDRW - VDRB
Min.
Typ. 0
Max. 100
Unit mV
RGB output range when FRP polarity reverse is stopped
VDROFF
3.0
V
Filter characteristics Assume the chroma amplitude at TP53 when SIG5 (VL = 0mV) is input to (A) and SIG1 (0dB at input center frequency (3.58Hz or 4.43Hz)) is input to (B) as 0dB. Obtain the amount by which the output at TP53 is attenuated when the frequencies noted on the right are input. SW59 = A NTSC 1.5MHz PAL 2.0MHz -16 -16 -7 -8 -40 -10 -10 -2 -3 -30 dB dB dB dB dB
Amount of BPF attenuation
ATBPF
NTSC 5.5MHz PAL 6.8MHz
ATRAPN Amount of TRAP attenuation ATRAPP
Input SIG2 (0dB, 3.58Hz and 4.43Hz) to (A) NTSC and measure the output at TP44. Assume the amplitude at TP44 during Y/C input mode as 0dB, and obtain the amount of PAL attenuation during COMP input mode. Assume the amplitude of the 100kHz component of the output at TP44 when SIG5 (VL = 150mV) is input to (A) and SIG1 (0dB, 3.58Hz + 100kHz) is input to (B) as 0dB. Obtain the frequency which attenuates the beat component of the output by 3dB when the SIG1 frequency is increased with respect to 3.58MHz. SW59 = A
-40
-30
dB
R-Y, B-Y and LPF characteristics
DEMLPF
0.8
1.0
1.3
MHz
Sync separation, TG block Input sync signal width sensitivity Input SIG5 (VL = 0mV, VS = 143mV, WS variable) to (A) and confirm that it is synchronized with the HD output at TP23. Gradually narrow the WS of SIG5 from 4.7s and obtain the WS at which synchronization with the HD output at TP23 is lost. Input SIG5 (VL = 0mV, WS = 4.7s, VS = variable) to (A) and confirm that it is synchronized with the HD output at TP23. Gradually reduce the VS of SIG5 from 143mV and obtain the VS at which synchronization with the HD output at TP23 is lost. Input SIG5 (VL = 0mV, WS = 4.7s, VS = 143mV) to (A) and measure the delay time with the RPD output at TP12. TDSYL is from the falling edge of the input HSYNC to the falling edge of the RPD output at TP12, and TDSYH is from the falling edge of the input HSYNC to the rising edge of the RPD output at TP12. Input SIG5 (VL = 0mV, WS = 4.7s, VS = 143mV, horizontal frequency variable) to (A) and confirm that it NTSC is synchronized with the HD output at TP23. Obtain the frequency fH at which the input and output are synchronized by changing the horizontal frequency of SIG5 from the non-synchronized condition. PAL HPLLN = fH - 15734 HPLLP = fH - 15625 430
WSSEP
2.0
s
Sync separation input sensitivity
VSSEP
40
60
mV
TDSYL Sync separation output delay time TDSYH
630
830
ns
4.7
5.0
5.3
s
HPLLN Horizontal pull-in range HPLLP
500
Hz
500
Hz
- 18 -
CXA2543R
Item Output transition time (P123 pin)
Symbol tTLH tTHL
Conditions Input SIG5 (VL = 0mV) to (A). Measure the transition time for each output. Load = 30pF (See Fig. 3.) Input SIG5 (VL = 0mV) to (A). Measure HCK1/HCK2. Load = 30pF (See Fig. 4.) Input SIG5 (VL = 0mV) to (A). Measure the HCK1/HCK2 duty. Load = 30pF
Min.
Typ.
Max. 30 30
Unit ns ns
Cross-point time difference
T
10
ns
HCK duty
DTYHC
47
50
53
%
External I/O characteristics VTEXTB External RGB input threshold voltage VTEXTW Input SIG5 (VL = 0mV) to (A) and SIG6 (VL variable) to (C). Raise the SIG6 amplitude (VL) from 0V and assume the voltage where the outputs at TP41, TP44 and TP46 go to black level as VTEXTB. Then raise the amplitude further and assume the voltage where these outputs go to white level as VTEXTW. SW6, SW7, SW8 = B Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 3V) to (C). Measure the rise delay time TD1EXT and the fall delay time TD2EXT of the outputs at TP41, TP44 and TP46. (See Fig. 2.) SW6, SW7, SW8 = B Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 1.7V) to (C). Measure the difference from the black level of the outputs at TP41, TP44 and TP46. SW6, SW7, SW8 = B Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 2.7V) to (C). Measure the difference from the black level of the outputs at TP41, TP44 and TP46. SW6, SW7, SW8 = B Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 2.7V) to (C). Measure the minimum pulse width at which each of the outputs at TP41, TP44 and TP46 reach the white limiter. SW6, SW7, SW8 = B 0.8 1.0 1.2 V
1.8
2.0
2.2
V
Propagation delay time between external RGB input and output
TDEXTH
50
100
150
ns
TDEXTL
50
100
150
ns
Output blanking level during external RGB input Output white level during external RGB input Minimum pulse width during external RGB input
EXTBK
0
V
EXTWT
3.5
V
TEXTMIN
180
ns
Serial transfer block ts0 Data setup time ts1 th0 Data hold time th1 tw1L Minimum pulse width tw1H tw2 LOAD setup time, activated by the rising edge of SCLK. (See Fig. 6.) DATA setup time, activated by the rising edge of SCLK. (See Fig. 6.) LOAD hold time, activated by the rising edge of SCLK. (See Fig. 6.) DATA hold time, activated by the rising edge of SCLK. (See Fig. 6.) SCLK pulse width. SCLK pulse width. LOAD pulse width. (See Fig. 6.) (See Fig. 6.) (See Fig. 6.) 1 150 150 150 150 160 160 ns ns ns ns ns ns s
- 19 -
Description of Electrical Characteristics Measurement Methods Serial Bus Register Initial Values
Serial bus Mode settings DAC settings S/H B-BRT 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H SHS1 SHS1 -- SHS1 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H SHS1 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H SHS1 SHS1 SHS1 SHS1 SHS1 SHS1 SHS1 SHS1 SHS1 SHS1 SHS1 SHS1 SHS1 SHS1 SHS1 SHS1 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H HUE COLOR BRIGHT CONTRAST R-BRT 1 2 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H PSIG-BRT 80H 80H 80H 80H 80H 78H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H -- 80H (-: don't care, ADJ: adjustment, SET: setting)
CXA2543R
Item System Panel -- -- -- -- -- -- -- LCX018 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 16:9 4:3 -- -- -- -- -- -- NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC Aspect
Symbol
Input
Horizontal AFC adjustment
COMP
ICC11
COMP
Current consumption VCC1
ICC12
Y/C
ICC13
Y/color difference
ICC2A Current consumption VCC2,3 ICC2B
COMP
COMP
Power supply characteristics Setting 2
Current consumption VDD
IDD1
COMP
IDD2
COMP
Digital block I/O characteristics
- 20 -
Low level input voltage
VIL
COMP
High level input voltage
VIH
COMP
Input current
II1
COMP
CKI pin low input current
II2
COMP
CKI pin high input current II3
COMP
High level output voltage
VOH1
COMP
Low level output voltage VOL1
COMP
High level output voltage
VOH2
COMP
Low level output voltage VOL2
COMP
High level output voltage
VOH3
COMP
Low level output voltage VOL3
COMP
Output off leak current
IOFF
COMP
Serial bus Mode settings System NTSC -- Through 80H 80H 0A0H 0FFH 80H 80H 0H 0H 0H 0H 0H 0H 80H 80H 80H 80H 80H 80H 60H 96H 80H 80H 96H 96H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 0H 80H 80H 80H 80H 80H 80H 0A0H 0A0H 0A0H 0A0H 0A0H 0A0H 60H 60H 60H 60H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H Through Through Through Through Through Through Through Through Through Through Through Through Through Through -- -- -- -- -- -- -- -- -- -- -- -- -- -- NTSC NTSC NTSC NTSC PAL NTSC NTSC NTSC NTSC NTSC -- -- NTSC PAL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Panel Aspect S/H HUE COLOR BRIGHT CONTRAST R-BRT B-BRT 1 2 DAC settings PSIG-BRT 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H (-: don't care, ADJ: adjustment, SET: setting)
Item
Symbol
Input
Video maximum gain GV
COMP
Contrast characteristics TYP
GCNTTP
COMP
Contrast characteristics MIN Y/C
GCNTMN COMP
FCYYC
Y signal frequency response 1
FCYCMN
COMP
FCYCMP Y/C Y/C Y/C
COMP
Y signal frequency response 2
FCL
Y signal block
GSHP1X
Picture quality adjustment variable amount 1
- 21 -
Y/C
GSHP1N
Picture quality adjustment variable amount 2
GSHP2X
COMP
GSHP2N COMP
Carrier leak
CRLEKY COMP
TDYYC
Y signal I/O delay time
TDYCMN
COMP
TDYCMP
COMP
CXA2543R
Serial bus Mode settings DAC settings S/H B-BRT 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 60H 60H 60H 80H 80H 80H 80H 80H 80H Through -- Through 80H 80H 80H 80H 80H Through 80H -- 80H 60H 60H 60H 60H 60H 60H 60H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H Through Through Through Through Through Through Through Through Through Through Through Through Through Through Through Through Through 80H 80H 80H 80H 80H 80H 0H 80H 96H 0FFH 80H 96H 80H 0H 96H 80H 80H 0FFH 96H 80H 80H 80H 80H 96H 80H 80H 80H 80H 96H 80H 80H 80H 80H 96H 80H 80H 80H 80H 96H 80H 80H 80H 80H 96H 80H 80H 80H 80H 96H 80H 80H HUE COLOR BRIGHT CONTRAST R-BRT 1 2 PSIG-BRT 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H (-: don't care, ADJ: adjustment, SET: setting)
CXA2543R
Item System NTSC -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PAL NTSC PAL NTSC PAL NTSC NTSC NTSC NTSC NTSC PAL NTSC NTSC NTSC NTSC PAL PAL PAL PAL Panel Aspect
Symbol
Input
ACC amplitude characteristics 1
ACC1
COMP
ACC1
COMP
ACC amplitude characteristics 2
ACC2
COMP
ACC2
COMP
FAPCN
COMP
APC pull-in range
FAPCP
COMP
Color adjustment characteristics MAX
GCOLMX COMP
Color adjustment characteristics MIN
GCOLMN COMP
HUE adjustment range MAX
Chroma signal block
- 22 -
HUEMX
COMP
HUE adjustment range MIN
HUEMN COMP
Killer operation input level
ACKN
COMP
ACKP
COMP
Demodulation output VRBN amplitude ratio NTSC VGBN
COMP
COMP
Demodulation output phase difference NTSC
RBN
COMP
GBN
COMP
Demodulation output amplitude ratio PAL
VRBP
COMP
VGBP
COMP
Demodulation output phase difference PAL
RBP
COMP
GBP
COMP
Serial bus Mode settings DAC settings S/H B-BRT 80H 0H 0H Through 80H 80H 80H 0FFH 96H HUE COLOR BRIGHT CONTRAST R-BRT 1 2 PSIG-BRT 80H System Panel -- -- -- Aspect
Item
Symbol
Input
Color difference input Y/color color adjustment GEXCMX difference characteristics MAX -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Through Through Through Through Through -- Through -- Through 80H 80H 80H 80H 80H 80H 80H -- 80H Through 80H 80H 80H 80H 80H 80H 80H 80H -- 80H 80H Through -- 80H 80H Through 96H 96H ADJ ADJ 0H 0H 0H 0FFH 80H 80H -- 80H 80H 96H Through -- 80H 80H 96H Through 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H -- 0H 80H 80H 96H Through -- 0FFH 80H 80H 96H Through -- 0H 80H 80H 96H Through 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H -- 0FFH 80H 80H 80H 96H Through -- 80H 80H 80H 80H 96H Through 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H -- -- -- -- -- NTSC NTSC PAL PAL -- -- -- -- -- -- -- -- -- 80H 80H 80H 80H 0H 96H Through 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H
Color difference input Y/color color adjustment GEXCMN difference characteristics MIN
80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 64H 64H 0FFH 0FFH 0FFH 0FFH 0FFH 0H
Color difference balance VEXCBL Y/color difference
Color difference input balance adjustment R
GEXRMX Y/color difference
GEXRMN
Chroma signal block
Color difference input balance adjustment B
GEXBMX
GEXBMN
RGB signal output block
- 23 -
-- -- -- -- -- -- -- --
G-Y matrix characteristics NTSC
VEXGBN
VEXGRN
G-Y matrix characteristics PAL
VEXGBP
VEXGRP
Y/color difference Y/color difference Y/color difference Y/color difference Y/color difference Y/color difference Y/color difference
RGB signal and PSIG VOUT output DC voltage
RGB signal and PSIG output VOUT DC voltage difference
RGB and PSIG output VLIMMX limiter operation voltage VLIMMN
Amount of change in BRTMX brightness BRTMN
Amount of change in PSIGMX PSIG PSIGMN
CXA2543R
(-: don't care, ADJ: adjustment, SET: setting)
Serial bus Mode settings DAC settings S/H B-BRT SET 80H 80H 0H 0H 0H 0H 0H 0H Through Through Through 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 0B4H 80H SET HUE COLOR BRIGHT CONTRAST R-BRT 1 2 PSIG-BRT 80H 80H 80H System Panel -- -- -- -- -- -- -- -- -- Aspect
Item
Symbol
Input -- -- --
Amount of change in SBBRT sub-brightness
Difference in gain between GRGB RGB output signals
Difference in RGB output inverted/non-inverted gain -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Through Through -- -- -- Through 80H 80H 80H -- -- -- Through 80H -- -- -- Through 80H -- -- -- Through 80H 80H 80H 80H 80H 80H 80H -- -- -- Through 80H 80H -- -- -- Through 80H 80H ADJ ADJ ADJ 60H 60H 0B4H 0H 0B4H -- -- -- Through 80H 80H ADJ -- -- -- Through 80H 80H ADJ ADJ 46H 46H 46H 46H 80H 80H 0FFH 80H 0FFH -- -- -- Through 80H 80H ADJ ADJ -- -- -- Through 80H 80H ADJ ADJ 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H -- -- -- Through 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H
GINV
Difference in black level potential between VBL RGB output signals
0H 78H 78H 78H 0H 0FFH 0H 0H 0H 0H 0H 0H 0H
0H 0D7H 0D7H 0D7H 0H 0H 0H 0FFH 0H 0H 0H 0H 0H
80H 80H 80H 80H 80H 80H 80H 80H 0FFH 0FFH 80H 80H 80H
G1
gain
G2
G3
RGB signal output block
- 24 -
-- -- -- -- Through 80H 80H SET
1 adjustment variable range
V 1MN
V 1MX
2 adjustment variable range
V 2MN
V 2MX
tPSIGH
PSIG transition time
tPSIGL
RGB output white limiter VWLIM operation voltage
Black limiter DC voltage difference
VBLIM
White limiter DC voltage difference
VWLIM
RGB output range when FRP polarity reverse is stopped
CXA2543R
VDROFF
80H
80H
80H
0H
0H
80H
(-: don't care, ADJ: adjustment, SET: setting)
Serial bus Mode settings DAC settings S/H B-BRT 80H 80H 0H 0H 0H 0H 0H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H Through 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 80H 80H 80H 80H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H Through 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 60H 60H 80H 60H 80H 60H 80H 80H 60H 80H 80H 60H 80H 80H 60H 80H 80H 60H 80H 80H 60H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 60H Through Through Through Through Through Through Through Through Through Through Through Through Through Through Through Through Through HUE COLOR BRIGHT CONTRAST R-BRT 1 2 PSIG-BRT 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H Input COMP -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SET SET Y/C NTSC -- -- -- -- NTSC PAL -- -- -- -- -- -- -- -- -- PAL NTSC -- System Panel Aspect
Item
Symbol
Amount of BPF attenuation
ATBPF
ATRAPN
Amount of TRAP attenuation
ATRAPP
Filter characteristics
R-Y, B-Y and LPF characteristics DEMLPF
Input sync signal width sensitivity WSSEP COMP COMP COMP COMP COMP COMP -- -- -- -- -- -- -- -- --
Sync separation input sensitivity VSSEP
Sync separation output delay time
TDSYL
TDSYH
HPLLN
Horizontal pull-in range
HPLLP
tTLH
Sync separation, TG block
External I/O characteristics
- 25 -
-- -- -- -- -- -- -- -- Through Through 80H 80H 80H 80H 64H 80H
Output transition time
tTHL
Cross-point time difference
T
HCK duty
DTYHC
External RGB input threshold voltage
VTEXTB
VTEXTW
Propagation delay time between TDEXTH external RGB input and output TDEXTL
Output blanking level during external RGB input
EXTBK
Output white level during external RGB input
EXTWT
80H 80H
80H 80H
80H 80H
0H 0H
0H 0H
80H 80H (-: don't care, ADJ: adjustment, SET: setting)
CXA2543R
Minimum pulse width during external RGB input
TEXTMIN
CXA2543R
3V SIG6 0V TP41, 44, 46 non-inverted output TDEXTH
50% TDEXTL
Fig. 2. Conditions for measuring the delay between external RGB input and output
90% 50% 10% tTLH tTHL T T
Fig. 3. Output transition time measurement conditions
Fig. 4. Cross-point time difference measurement conditions
White VG3
Non-inverted output
VG2
3.5V
Black 1.5V
VG1
Input
Fig. 5. characteristics measurement conditions
- 26 -
CXA2543R
DATA
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
ts1
th1
SCLK
50%
tw1H
tw1L
LOAD
50%
ts0
th0
tw2
Fig. 6. Serial transfer block measurement conditions
- 27 -
CXA2543R
Input Waveforms SG No. Waveform
Sine wave video signal: With/without burst Amplitude and frequency variable
SIG1
150mV 143mV
150mV
Value noted on left: 0dB
Chroma signal: Burst, chroma frequency (3.579545MHz, 4.433619MHz) Chroma phase and burst frequency variable
SIG2
150mV 143mV Value noted on left: 0dB
Ramp waveform
SIG3
143mV 1H
357mV
5-step staircase waveform
150mV
SIG4
143mV 1H
VL
SIG5
VS fH WS
VL amplitude variable VS variable: 143mV unless otherwise specified WS variable: 4.7s unless otherwise specified fH variable: 15.734kHz (NTSC) or 15.625kHz (PAL) unless otherwise specified
- 28 -
CXA2543R
SG No.
30s 5s
Waveform
VL amplitude variable
SIG6
VL
Horizontal sync signal
75mV Frequency variable
SIG7
143mV
175mV
10-step staircase waveform
357mV
SIG8
143mV 1H
2T pulse waveform VL amplitude variable VS variable: 143mV unless otherwise specified WS variable: 4.7s unless otherwise specified fH variable: 15.734kHz (NTSC) or 15.625kHz (PAL) unless otherwise specified WS
VL
SIG9
VS fH
- 29 -
CXA2543R
Electrical Characteristics Measurement Circuit
+12V TP46 ICC2 47 0.1 300p 300p 300p 10000p TP36 TP35 TP34 TP33 +4.5V ICC1 47 0.1 49 VCC1 0.01 (D) (E) SW51 A 0.01 B A 0.01 B SW52 TP53 50 SIG.CENTER 51 B-Y IN 52 R-Y IN 53 C OUT 54 BLK LIM V54 SW54 55 APC 15k 0.22 0.068 2 57 VXO IN 1 58 V REG (B) SW59 A 59 C IN B TP60 1 61 Y IN SW62 62 PIC V62 15k 6 V64 SW64 63 F0 ADJ
H.FIL OUT SYNC IN
TP44
TP41
TP39
0.47 48
VCC2
0.47 45
FB G
0.47 43
GND2
0.47 40
VCC3
47
FB R
46
R OUT
44
G OUT
42
FB B
41
B OUT
39
PSIG
38
GND3
37
FB PSIG
36
RGT
35
LOAD
34
DATA
33
SCLK
VD 32 VSS2 31 EN 30 XEN 29 VCK1 28 VCK2 27 VST 26 XVST 25 FLD IN 24 HD 23 PCG 22 XPCG 21 HCK1 20 HCK2 19 HST 18
TP32
TP30 TP29 TP28 TP27 TP26 TP25 TP24 TP23 TP22 TP21 TP20 TP19 TP18 TP17 3V ICC3 47 0.1
1 56 VXO OUT
60 TEST3
64 PWRST
TRAP GND1
S.SEP IN
XHST 17
TEST1 TEST2 EXT G EXT R EXT B VD IN VSS1 CKI VDD1 RPD CKO
1
2
3
4
5
6
7
8
9
10
11
12
13
14 L
15 4 C
16
0.47 0.033
TP12 750 SW6 SW7 SW8 B AB A B A TP9 TP10 TP11 1k 220p
6800p
5 (A) (C)
10k 3.3
33k 3 10k 0.01 V14
1 Used crystal: KINSEKI CX-5F Frequency deviation: within 30ppm, frequency temperature characteristics: within 30ppm, load capacity: 16pF NTSC: 3.579545MHz PAL: 4.433619MHz 2 NTSC: shorted, PAL: 18pF 3 Variable Capcitance Diode: 1T369 (SONY)
4 DCX501 mode: L value: 4.7H, C value: 22pF LCX018 (4:3) mode: L value: 4.7H, C value: 22pF LCX018 (16:9) mode: L value: 2.2H, C value: 33pF 5 Trap (TDK) NTSC: NLT4532-S3R6B PAL: NLT4532-S4R4 6 Resistance value tolerance: 2%, temperature coefficient: 200ppm or less
- 30 -
CXA2543R
Description of Operation The CXA2543R incorporates the three functions of an RGB decoder block, an RGB driver block and a timing generator (TG) block onto a single chip using Bi-CMOS technology. 1) RGB decoder block * Input mode switching The input mode can be switched between composite input, Y/C input and Y/color difference input by the serial bus settings. During composite input: The composite signal is input to Pins 3, 59 and 61. During Y/C input: The Y signal is input to Pins 3 and 61, and the C signal to Pin 59. During Y/color difference input: The Y signal is input to Pins 3 and 61, the B-Y signal to Pin 51, and the R-Y signal to Pin 52. * System switching The input system can be switched between NTSC and PAL (DPAL using external delay lines and SPAL ) by the serial bus settings. * Trap, BPF The center frequency of the built-in trap and BPF can be switched to 3.58Hz during NTSC and 4.43Hz during PAL. During composite input, the Y signal enters the trap circuit and the C signal enters the BPF. These signals do not pass through the trap or BPF during Y/C input and Y/color difference input. * ACC detection, ACC amplifier The amplitude of the burst signal output from the ACC amplifier is detected and the ACC amplifier is controlled to maintain the burst signal amplitude at a constant level. * VXO, APC detection The VXO local oscillation circuit is a crystal oscillation circuit. The phases of the input burst signal and the VXO oscillator output are compared in the APC detection block, and the detective output is used to form a PLL loop that controls the VXO oscillation frequency, which means that the need for adjustments is eliminated. * External inputs These are digital inputs with two thresholds. When one of the RGB inputs is higher than the lower threshold Vth1 ( 1.0V), all RGB outputs go to black level. When the higher threshold Vth2 ( 2.0V) is exceeded, the output for only the signal in question goes to white level, while the other outputs remain at black level.
- 31 -
CXA2543R
2) RGB driver block * correction In order to support the characteristics of LCD panels, the I/O characteristics are as shown in Fig. 1. The characteristics change as shown in Fig. 2 by adjusting the serial bus register 1, and as shown in Fig. 3 by adjusting 2.
B' Output B A A Output A' B A Output B' B
Input
Input
Input
Fig. 1
Fig. 2
Fig. 3
* Sample-and-hold circuit As LCD panels sample RGB signals simultaneously, RGB signals output from the CXA2543R must be sampled-and-hold in sync with the LCD panel drive pulses.
R S/H1 S/H4 HCK1
G
S/H2
S/H4
A
B B S/H3 S/H4 C SH1 SH2 SH3 SH4
DCX501 RGT = H (normal) SHS1 SH1 SH2 SH3 SH4 LCX018 RGT = H (normal) SHS1 SH1 SH2 SH3 SH4 A B SHS2 C A SHS3 B C SH1 SH2 SH3 SH4 RGT = L (inverted) SHS1 SHS2 SHS3 B SHS2 A SHS3 C SH1 SH2 SH3 SH4 RGT = L (inverted) SHS1 B A SHS2 A C SHS3 C B SH1: R signal SH pulse SH2: G signal SH pulse SH3: B signal SH pulse SH4: RGB signal SH pulse
Through Through Through A C C B B A
Through Through Through C B A
Through Through Through B A C A C B C B A
Through Through Through C B A
The sample-and-hold circuit performs sample-and-hold by receiving the SH1 to SH4 pulses from the TG block. Since LCD panels perform color coding using an RGB delta arrangement, each horizontal line must be compensated by 1.5 dots. This relationship is reversed during right/left inversion. This compensation timing is also generated by the TG block. The sample-and-hold timing changes according to the phase relationship with the HCK1 pulse, so the timing should be set to SHS1, 2 or 3 in accordance with the actual board. - 32 -
CXA2543R
* RGB output RGB outputs (Pins 41, 44, and 46) are inverted each horizontal line by the FRP pulse supplied from the TG block as shown in the figure below. Feedback is applied so that the center voltage (Vsig center) of the output signal matches the reference voltage (VCC2 + GND2)/2 (or the voltage input to SIG CENTER (Pin 50)). In addition, the white level output is clipped by the Vsig center 0.7V, and the black level output is clipped by the limiter operation point that is adjusted at the BLKLIM (Pin 54).
Video IN
FRP Black level limiter
RGB OUT
White level limiter Vsig center White level limiter
Black level limiter
3) TG block * PLL and AFC circuits The TG block contains a PLL circuit phase comparator and frequency division counter, and a PLL circuit can be comprised by connecting an external VCO circuit. The PLL error detection signal is generated at the following timing. The phase comparison output of the entire bottom of HSYNC and the internal frequency division counter becomes RPD. RPD output is converted to DC error with the lag-lead filter, and then it changes the capacitance of variable capacitance diode to stabilize the oscillation frequency at 1066fH in the DCX501BK and LCX018AK (4:3) mode, 1417fH in the LCX018AK (16:9) mode. The PLL of this system is adjusted by setting the the reverse bias voltage of the varicap diode (V14) so that the point at which RPD changes is at the center of the window depicted in the figure below.
H SYNC WS
RPD WL WH WL = WH
* H position The horizontal display position can be set at 2fH intervals in 32 different ways by the serial bus settings. The picture center is set at the internal default value, but because there is a difference between the RGB signal and the drive pulse delays on the actual board, the picture center may not match the design center. In this case, adjust with the serial bus. - 33 -
CXA2543R
* Right/left inversion The LCD panel is arranged in a delta arrangement, where identical signal lines are offset by 1.5 dots from adjoining lines. For this reason, a 1.5-bit offset is attached to the horizontal start pulse (HST) between odd lines and even lines. HCK and S/H are also 1.5-bit offset. When the panel is driven by left scan (Reverse scan), this offset relationship is inverted for even and odd lines. Moreover, since the dot arrangement is asymmetrical, the HST position is also changed. RGT = H: Right scan mode RGT = L: Left scan mode
Right scan (Normal scan) Left scan (Reverse scan)
H SCANNER
V SCANNER
Display area
LCD panel
* WIDE mode (DCX501BK mode) Setting the WIDE mode by switching the aspect with the serial bus shifts the unit to WIDE mode. In the DCX501BK mode, the aspect ratio is converted through pulse eliminator processing, allowing 16:9 quasi-WIDE display. During WIDE mode, vertical pulse eliminator scanning of 1/4 for NTSC or 1/2 and 1/4 for PAL are performed, and the video signal is compressed to achieve a 16:9 aspect ratio. In addition, in areas outside the display area, black is displayed in the 28 lines, respectively at the top and bottom of this display area by performing high-speed scanning The method of black display is a writing method by PSIG. By setting PSIG level during high-speed scanning to black display level and writing this black display level at the PCG timing, reliable black display is realized within the limited V blanking period. During this period, HST is masked and video signal input is limited. See the attached sheets for detailed timing.
Vertical high-speed scanning
Black display area
28 LINES
225 LINES
Display area
Display area
169 LINES
Black display area 4:3 display 16:9 display
28 LINES
Vertical pulse eliminator scanning DCX501BK
- 34 -
CXA2543R
During high-speed scanning VCKn
During normal-speed scanning
Double-speed scanning HST Stop
FRP (Internal pulse) 1H cycle
PCG
* AC driving of LCD panels during no signal HST, XHST, HCK1, HCK2, VST, XVST, VCK1, VCK2, PCG, XPCG, EN, XEN, HD, VD, and FRP are made to run freely so that the LCD panel is AC driven even when there is no composite sync from the SYNC IN pin. During this time, the HSYNC separation circuit stops and the PLL counter is made to run freely. In addition, the VSYNC separation circuit is also stopped, so the auxiliary V counter is used to create the reference pulse for generating VD, VST and XVST. The cycle of this v counter is designed to be 525/2H for NTSC and 625/2H for PAL. However, when there is no vertical sync signal for 5 fields, the no signal state is assumed and the free running VD, VST and XVST pulses are generated from the next field. In addition, RPD is kept at high impedance when there is no signal in order to prevent the AFC circuit from causing errors due to phase comparison.
- 35 -
CXA2543R
Description of Serial Control Operation 1) Control method Control data consists of 16 bits of data which is loaded one bit at a time at the rising edge of SCLK. This loading operation starts from the falling edge of LOAD and is completed at the next rising edge. (D13 to D15 are dummy data.) Digital block control data is established by the vertical sync signal and the LOAD "H". If data is transferred multiple times for the same item, the data immediately before the vertical sync signal is valid. Analog (electronic attenuator) block control data becomes valid each time the LOAD signal is input.
DATA
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SCLK LOAD
Serial transfer timing 2) Serial data map The serial data map is as follows. D15 D14 D13 D12 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 D11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 D10 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 1 D9 0 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 1 D8 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 D7 D6 D5
Aspect
D4
Supported panel
D3
D2
D1
D0
S/H phase
System
Input switching
FRP polarity 0 0 0 0 0
Y/color VD FRP256 Up/down SYNC HD Mode difference inversion inversion GEN polarity polarity clamp
0 0 0 0 0
0 0 0
0
0
PAL External FIELD determi decima V SYNC -nation -tion
H-POSITION HD-POSITION
PCG width EN width HUE
0 0
0 0
PCG position EN position
COLOR BRIGHT CONTRAST R-BRT B-BRT 1 2 PSIG-BRT
TEST
Note) Any data transfer performed when addresses D8, D9, D10, D11, D12 = 1, 1, 1, 1, 1 (shadowed portion) will result in test mode regardless of other data settings. Do not transfer data with these addresses set this way. - 36 -
CXA2543R
3) Serial data mode settings (X: don't care) * Input switching D1 D0 0 X Composite input (default) 1 0 Y/C input 1 1 Y/color difference input * System switching D3 D2 0 X NTSC (default) 1 0 D-PAL 1 1 S-PAL * Supported panel switching D4 0 DCX501BK (default) 1 LCX018AK * Aspect switching D5 0 4:3 (default) 1 16:9 * Sample-and-hold timing switching D7 D6 0 0 SHS1 (default) 0 1 SHS2 1 0 SHS3 1 1 Through (sample-and-hold not performed) * HD output polarity switching D0 0 Negative polarity (default) 1 Positive polarity * VD output polarity switching D1 0 Negative polarity (default) 1 Positive polarity * Y/color difference clamp position switching This switches the position at which the R-Y and B-Y input signals are clamped during Y/color difference input mode. D2 0 Pedestal position (default) 1 SYNC position * Mode switching This is the test mode. Set to normal mode. D3 0 Normal mode (default) 1 Test mode - 37 -
CXA2543R
* Sync generator function This stops outputs other than VD and HD of the TG block. D4 0 OFF (default) 1 ON Note) Make sure that Vcc2, 3 (12V) and LCD panel power supply should be turned OFF during sync generator ON. * Up/down inversion function This switches the up/down inverted display. D5 0 DOWN (normal display) (default) 1 UP (up/down inverted display) * FRP256 field inversion This further inverts the polarity of the RGB output that is inverted every 1H for 256 fields. D6 0 OFF (default) 1 ON * FRP polarity inversion function D7 0 ON (1H inversion) (default) 1 OFF (polarity not inverted) * External field identification input switching Internal field identification is not performed and an externally field input source is used. D0 0 OFF (internal identification) (default) 1 ON (external input) * External VSYNC input switching Internal VSYNC separation is not performed and an externally input VSYNC is used. D1 0 OFF (internal separation) (default) 1 ON (external input) * PAL pulse elimination switching This switches on/off the PAL pulse elimination function during PAL mode. D2 0 ON (elimination performed) (default) 1 OFF (elimination not performed)
- 38 -
CXA2543R
* H position setting D4 D3 D2 D1 D0 0 0 0 0 0 : : : : : 1 0 0 0 0 (default) : : : : : 1 1 1 1 1 Variable in 2fH (= 1 bit) increments
CLK (internal) 10001 HST 10000 01111 1 step 1 step
* HD phase setting D4 D3 D2 D1 D0 0 0 0 0 0 (default) : : : : : 1 1 1 1 1 Variable in 4fH (= 1 bit) increments
HSYNC HD 00000 11111 31 steps
- 39 -
CXA2543R
* PCG pulse position This sets the PCG pulse position (A in the figure below). D1 D0 0 0 (default) 1 1 DCX501 and LCX018 (4:3) mode: variable in 6fH (= 1 bit) increments LCX018 (16:9) mode: variable in 9fH (= 1 bit) increments * PCG pulse width This sets the PCG pulse width (B in the figure below). D5 D4 0 0 (default) 1 1 DCX501 and LCX018 (4:3) mode: variable in 8fH (= 1 bit) increments LCX018 (16:9) mode: variable in 12fH (= 1 bit) increments * EN pulse position This sets the EN pulse position (C in the figure below). D1 D0 0 0 (default) 1 1 DCX501 and LCX018 (4:3) mode: variable in 4fH (= 1 bit) increments LCX018 (16:9) mode: variable in 6fH (= 1 bit) increments * EN pulse width This sets the EN pulse width (D in the figure below). D5 D4 0 0 (default) 1 1 DCX501 and LCX018 (4:3) mode: variable in 8fH (= 1 bit) increments LCX018 (16:9) mode: variable in 12fH (= 1 bit) increments
HSYNC PCG B A EN D C
Setting Correspondence Table Set the positions and widths for the EN and PCG pulses as follows when driving the DCX501BK and the LCX018AK. DCX501BK Width D5 PCG pulse EN pulse 0 0 D4 0 0 Position D1 0 0 D0 0 0 - 40 - PCG pulse EN pulse D5 1 0 LCX018AK Width D4 0 0 Position D1 0 1 D0 0 1
CXA2543R
4) Serial data electronic attenuator (D/A converter) settings * HUE D7 D6 1 0 * COLOR D7 D6 1 0 * BRIGHT D7 D6 1 0 * CONTRAST D7 D6 1 0 * R-BRT D7 D6 1 0 * B-BRT D7 D6 1 0 * 1 D7 D6 0 0 * 2 D7 D6 0 0 * PSIG-BRT D7 D6 0 0
D5 0 D5 0 D5 0 D5 0 D5 0 D5 0 D5 0 D5 0 D5 0
D4 0 D4 0 D4 0 D4 0 D4 0 D4 0 D4 0 D4 0 D4 0
D3 0 D3 0 D3 0 D3 0 D3 0 D3 0 D3 0 D3 0 D3 0
D2 0 D2 0 D2 0 D2 0 D2 0 D2 0 D2 0 D2 0 D2 0
D1 0 D1 0 D1 0 D1 0 D1 0 D1 0 D1 0 D1 0 D1 0
D0 0 (default) D0 0 (default) D0 0 (default) D0 0 (default) D0 0 (default) D0 0 (default) D0 0 (default) D0 0 (default) D0 0 (default)
5) Test mode Test mode results if data is sent to the following addresses. For this reason, do not perform data transfer using these addresses. D12 1 D11 1 D10 1 D9 1 D8 1 D7 D6 D5 D4 D3 D2 D1 D0
Note) If data transfer is performed in these addresses, the chip will enter test mode regardless of the data set.
- 41 -
CXA2543R
DCX501BK Color Coding Diagram The delta arrangement is used for the color coding in the LCD panels with which this IC is compatible. Note that the shaded region within the diagram is not displayed.
DCX501BK pixel arrangement
HSW1 HSW2 HSW3 HSW266 HSW267 HSW268
dummy1 Vline1 Vline2 Vline3
R B R B R B R B
G R G R G R G R G B R G
B G B G B G B G B G B
R B R
G R
B G
R B
G R
B G
R B
G R
B G
R B
Photo-shielding area GBRG R G B R
1
GBRGBRGBRGBRG Display area BRGBRGBRGBRGBR G B R G B R G B R G B B G R B G R B G B G R B G R B R B G R B G R G R B G R B G B G R B G R B R B G R B G R G R B G R B G B G R B G R B R B G R B G R G R B G R B G B G R B G R 1 R B G R G R 225 227
R
R
Vline224 Vline225 dummy2
R
R
R
R
Precharge SW 2 800 803 1
- 42 -
LCX018AK Pixel Arrangement (4:3)
EVEN = 1083 dots ODD = 1083 dots
EVEN = 7 dots ODD = 8 dots
Side Black
2
GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW
EVEN = 133 dots ODD = 132 dots
4:3 Area
44 45 46 47 311 312 313 314 356 357
EVEN = 803 dots ODD = 804 dots (effective 11.651mm) EVEN = 133 dots ODD = 132 dots
Side Black
DR1
EVEN = 7 dots ODD = 7 dots
DL1
DL2
1
DR2
GATE SW GATE SW GATE SW GATE SW
GATE SW GATE SW GATE SW GATE SW GATE SW
2 dots
B RGB R GB RG BRG BRGB RGBRG B RGB RGB RGB RGB RGBRGBRG B RGB RGBRGB RGB RGB RGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR RGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR
RGBRGB RG B
1
B RGB R GB RG BRG BRGB RGBRG B RGB RGB RGB RGB RGBRGBRG B RGB RGBRGB RGB RGB
2
RGBRGB RG B
3
B RGB R GB RG BRG BRGB RGBRG B RGB RGB RGB RGB RGBRGBRG B RGB RGBRGB RGB RGB
225 dots (effective 8.775mm)
2 dots
- 43 -
4
RGBRGB RG B RGBR GBRGB RGB RG BRGB RGB RGB RGBRG BRGBRGBRGBR GBRGBRGB R B RGB R GB RG BRG BRGB RGBRG B RGB RGB RGB RGB RGBRGBRG B RGB RGBRGB RGB RGB RGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR RGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR RGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR RGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR RGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR RGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR RG B R GB R G B RG B RG B RG B RG B RG B RG B RG B RG B R G B RGB R GB R G B R G B R
RGBRGB RG B
B RGB R GB RG BRG BRGB RGBRG B RGB RGB RGB RGB RGBRGBRG B RGB RGBRGB RGB RGB
RGBRGB RG B
B RGB R GB RG BRG BRGB RGBRG B RGB RGB RGB RGB RGBRGBRG B RGB RGBRGB RGB RGB
RGBRGB RG B
B RGB R GB RG BRG BRGB RGBRG B RGB RGB RGB RGB RGBRGBRG B RGB RGBRGB RGB RGB
RGBRGB RG B
224
B RGB R GB RG BRG BRGB RGBRG B RGB RGB RGB RGB RGBRGBRG B RGB RGBRGB RGB RGB
225
RGBRGB RG B
B RGB R GB RG BRG BRGB RGBRG B RGB RGB RGB RGB RGBRGBRG B RGB RGBRGB RGB RGB
RGBRGB RG B
B RGB R GB RG BRG BRGB RGBRG B RGB RGB RGB RGB RGBRGBRG B RGB RGBRGB RGB RGB
RGBRGBRGB
CXA2543R
LCX018AK Pixel Arrangement (16:9)
EVEN = 1083 dots ODD = 1083 dots
EVEN = 7 dots ODD = 8 dots EVEN = 1069 dots ODD = 1068 dots (effective 15.493mm)
2
GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW
EVEN = 7 dots ODD = 7 dots
355 356 357 DR1 DR2
DL1
DL2
1
3
GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW
GATE SW GATE SW GATE SW GATE SW
2 dots
BRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGB
RGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR
1
BRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGB
2
RGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR
3
BRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGB
4
RGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR BRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGB
RGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR
225 dots (effective 8.775mm)
2 dots
- 44 -
BRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGB
RGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR
BRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGB
RGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR
BRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGB
RGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR
224
BRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGB
225
RGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR
BRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGB
RGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR
BRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGB
RGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR
CXA2543R
DCX501BK Horizontal Direction Timing Chart NTSC/PAL
Unless otherwise specified, serial settings are the default values. RGT: H (Normal scan) 1066fH
MCK 4.7s (79fH) 4.7s (79fH) 2.0s (34fH) 20.5fH 4.5s (75fH) 12fH
SYNC
(BLK)
HD
HST1
HCK1
HCK2
- 45 -
EVEN FIELD 7.5s (125.5fH) 1.5s (25fH) 76fH 1.0s (17fH) 6.0s (101fH) 2.5s (42fH) EVEN FIELD
SH3 (Internal pulse) SH1 (Internal pulse) SH4 (Internal pulse) SH2 (Internal pulse) FRP (Internal pulse) 5.0s (83.5fH)
ODD FIELD
VCK1
VCK2
VST/VD
PCG
EN
EN (PAL) PSIGFRP (Internal pulse)
ODD FIELD
ODD LINE CXA2543R
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field.
DCX501BK Horizontal Direction Timing Chart NTSC/PAL
Unless otherwise specified, serial settings are the default values. RGT: H (Normal scan) 1066fH
MCK 4.7s (79fH) 4.7s (79fH) 2.0s (34fH) 19fH 4.5s (75fH) 12fH
SYNC
(BLK)
HD
HST1
HCK1
HCK2
- 46 -
EVEN FIELD 124fH 1.5s (25fH) 76fH 1.0s (17fH) 6.0s (101fH) 2.5s (42fH) EVEN FIELD
SH3 (Internal pulse) SH1 (Internal pulse) SH4 (Internal pulse) SH2 (Internal pulse) FRP (Internal pulse) 82fH
ODD FIELD
VCK1
VCK2
VST/VD
PCG
EN
EN (PAL) PSIGFRP (Internal pulse)
ODD FIELD
EVEN LINE CXA2543R
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field.
DCX501BK Horizontal Direction Timing Chart NTSC/PAL
Unless otherwise specified, serial settings are the default values. RGT: L (Reverse scan) 1066fH
MCK 4.7s (79fH) 4.7s (79fH) 2.0s (34fH) 20.5fH 4.5s (75fH) 12fH
SYNC
(BLK)
HD
HST1
HCK1
HCK2
- 47 -
EVEN FIELD 7.5s (125.5fH) 1.5s (25fH) 76fH 1.0s (17fH) 6.0s (101fH) 2.5s (42fH) EVEN FIELD
SH3 (Internal pulse) SH1 (Internal pulse) SH4 (Internal pulse) SH2 (Internal pulse) FRP (Internal pulse) 5.0s (83.5fH)
ODD FIELD
VCK1
VCK2
VST/VD
PCG
EN
EN (PAL) PSIGFRP (Internal pulse)
ODD FIELD
ODD LINE CXA2543R
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field.
DCX501BK Horizontal Direction Timing Chart NTSC/PAL
Unless otherwise specified, serial settings are the default values. RGT: L (Reverse scan) 1066fH
MCK 4.7s (79fH) 4.7s (79fH) 2.0s (34fH) 4.5s (75fH) 22fH 12fH
SYNC
(BLK)
HD
HST1
HCK1
HCK2
- 48 -
EVEN FIELD 127fH 1.5s (25fH) 76fH 1.0s (17fH) 6.0s (101fH) 2.5s (42fH) EVEN FIELD
SH3 (Internal pulse) SH1 (Internal pulse) SH4 (Internal pulse) SH2 (Internal pulse) FRP (Internal pulse) 85fH
ODD FIELD
VCK1
VCK2
VST/VD
PCG
EN
EN (PAL) PSIGFRP (Internal pulse)
ODD FIELD
EVEN LINE CXA2543R
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field.
LCX018AK Horizontal Direction Timing Chart (4:3) NTSC/PAL
Unless otherwise specified, serial settings are the default values. RGT: H (Normal scan), PCG width: LH, EN position: HH Master Clock: 16.773MHz (NTSC) / 16.656MHz (PAL) PLL Counter N: 1066fH
MCK 4.7s (79fH) 4.7s (79fH) 2.0s (34fH) 4.5s (75fH) 35.5fH 6fH
SYNC
(BLK)
HD
HST1
HCK1
HCK2
SH1 (Internal pulse) SH2 (Internal pulse)
- 49 -
EVEN FIELD 4.5s (76fH) 1.0s (17fH) 2.5s (41fH) 6.0s (101fH) EVEN FIELD 0.5s (8fH)
SH4 (Internal pulse)
SH3 (Internal pulse) FRP (Internal pulse)
ODD FIELD
7.0s (117.5fH) 4.5s (75.5fH) 2.2s (37fH)
VCK1
VCK2
VST/VD
PCG
EN
EN (PAL) PSIGFRP (Internal pulse)
ODD FIELD
ODD LINE CXA2543R
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field.
LCX018AK Horizontal Direction Timing Chart (4:3) NTSC/PAL Unless otherwise specified, serial settings are the default values. RGT: H (Normal scan), PCG width: LH, EN position: HH Master Clock: 16.773MHz (NTSC) / 16.656MHz (PAL) PLL Counter N: 1066fH
MCK 4.7s (79fH) 4.7s (79fH) 2.0s (34fH) 4.5s (75fH) 34fH 6fH
SYNC
(BLK)
HD
HST1
HCK1
HCK2
SH1 (Internal pulse)
SH2 (Internal pulse) SH4 (Internal pulse)
- 50 -
EVEN FIELD 4.5s (76fH) 1.0s (17fH) 2.5s (41fH) 6.0s (101fH) EVEN FIELD 0.5s (8fH)
SH3 (Internal pulse) FRP (Internal pulse)
ODD FIELD
116fH 74fH 2.2s (37fH)
VCK1
VCK2
VST/VD
PCG
EN
EN (PAL)
PSIGFRP (Internal pulse)
ODD FIELD
EVEN LINE
CXA2543R
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field.
LCX018AK Horizontal Direction Timing Chart (4:3) NTSC/PAL Unless otherwise specified, serial settings are the default values. RGT: L (Reverse scan), PCG width: LH, EN position: HH Master Clock: 16.773MHz (NTSC) / 16.656MHz (PAL) PLL Counter N: 1066fH
MCK 4.7s (79fH) 4.7s (79fH) 2.0s (34fH) 4.5s (75fH) 35.5fH 6fH
SYNC
(BLK)
HD
HST1
HCK1
HCK2
SH1 (Internal pulse) SH2 (Internal pulse) SH4 (Internal pulse)
- 51 -
EVEN FIELD 4.5s (76fH) 1.0s (17fH) 2.5s (41fH) 6.0s (101fH) EVEN FIELD 0.5s (8fH)
SH3 (Internal pulse) FRP (Internal pulse)
ODD FIELD
7.0s (117.5fH) 4.5s (75.5fH) 2.2s (37fH)
VCK1
VCK2
VST/VD
PCG
EN
EN (PAL)
PSIGFRP (Internal pulse)
ODD FIELD
ODD LINE
CXA2543R
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field.
LCX018AK Horizontal Direction Timing Chart (4:3) NTSC/PAL
Unless otherwise specified, serial settings are the default values. RGT: L (Reverse scan), PCG width: LH, EN position: HH Master Clock: 16.773MHz (NTSC) / 16.656MHz (PAL) PLL Counter N: 1066fH
MCK 4.7s (79fH) 4.7s (79fH) 2.0s (34fH) 4.5s (75fH) 37fH 6fH
SYNC
(BLK)
HD
HST1
HCK1
HCK2
- 52 -
EVEN FIELD 4.5s (76fH) 1.0s (17fH) 2.5s (41fH) 6.0s (101fH) EVEN FIELD 0.5s (8fH)
SH1 (Internal pulse) SH2 (Internal pulse) SH4 (Internal pulse) SH3 (Internal pulse) FRP (Internal pulse) 119fH
ODD FIELD
VCK1 2.2s (37fH)
77fH
VCK2
VST/VD
PCG
EN
EN (PAL)
PSIGFRP (Internal pulse)
ODD FIELD
EVEN LINE
CXA2543R
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field.
LCX018AK Horizontal Direction Timing Chart (16:9) NTSC/PAL
Unless otherwise specified, serial settings are the default values. RGT: H (Normal scan), PCG width: LH, EN position: HH Master Clock: 22.295MHz (NTSC) / 22.141MHz (PAL) PLL Counter N: 1417fH
MCK 4.7s (105fH) 4.7s (105fH) 2.0s (45fH) 47.5fH 4.5s (100fH) 6fH
SYNC
(BLK)
HD
HST1
HCK1
HCK2
SH1 (Internal pulse)
SH2 (Internal pulse) SH4 (Internal pulse)
- 53 -
EVEN FIELD 4.5s (101fH) 1.0s (22fH) 2.5s (57fH) 6.0s (134fH) EVEN FIELD 0.5s (11fH)
SH3 (Internal pulse) FRP (Internal pulse)
ODD FIELD
7.0s (156.5fH) 4.5s (100.5fH) 2.2s (51fH)
VCK1
VCK2
VST/VD
PCG
EN
EN (PAL)
PSIGFRP (Internal pulse)
ODD FIELD
ODD LINE
CXA2543R
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field.
LCX018AK Horizontal Direction Timing Chart (16:9) NTSC/PAL
Unless otherwise specified, serial settings are the default values. RGT: H (Normal scan), PCG width: LH, EN position: HH Master Clock: 22.295MHz (NTSC) / 22.141MHz (PAL) PLL Counter N: 1417fH
MCK 4.7s (105fH) 4.7s (105fH) 2.0s (45fH) 46fH 4.5s (100fH) 6fH
SYNC
(BLK)
HD
HST1
HCK1
HCK2
SH1 (Internal pulse)
SH2 (Internal pulse) SH4 (Internal pulse)
- 54 -
EVEN FIELD 4.5s (101fH) 1.0s (22fH) 2.5s (57fH) 6.0s (134fH) EVEN FIELD 0.5s (11fH)
SH3 (Internal pulse) FRP (Internal pulse)
ODD FIELD
155fH 99fH 2.2s (51fH)
VCK1
VCK2
VST/VD
PCG
EN
EN (PAL)
PSIGFRP (Internal pulse)
ODD FIELD
EVEN LINE
CXA2543R
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field.
LCX018AK Horizontal Direction Timing Chart (16:9) NTSC/PAL
Unless otherwise specified, serial settings are the default values. RGT: L (Reverse scan), PCG width: LH, EN position: HH Master Clock: 22.295MHz (NTSC) / 22.141MHz (PAL) PLL Counter N: 1417fH
MCK 4.7s (105fH) 4.7s (105fH) 2.0s (45fH) 47.5fH 4.5s (100fH) 6fH
SYNC
(BLK)
HD
HST1
HCK1
HCK2
- 55 -
EVEN FIELD 4.5s (101fH) 1.0s (22fH) 2.5s (57fH) 6.0s (134fH) EVEN FIELD 0.5s (11fH)
SH1 (Internal pulse) SH2 (Internal pulse) SH4 (Internal pulse) SH3 (Internal pulse) FRP (Internal pulse) 7.0s (156.5fH)
ODD FIELD
VCK1 2.2s (51fH)
4.5s (100.5fH)
VCK2
VST/VD
PCG
EN
EN (PAL)
PSIGFRP (Internal pulse)
ODD FIELD
ODD LINE CXA2543R
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field.
LCX018AK Horizontal Direction Timing Chart (16:9) NTSC/PAL
Unless otherwise specified, serial settings are the default values. RGT: L (Reverse scan), PCG width: LH, EN position: HH Master Clock: 22.295MHz (NTSC) / 22.141MHz (PAL) PLL Counter N: 1417fH
MCK 4.7s (105fH) 4.7s (105fH) 2.0s (45fH) 49fH 4.5s (100fH) 6fH
SYNC
(BLK)
HD
HST1
HCK1
HCK2
- 56 -
EVEN FIELD 4.5s (101fH) 1.0s (22fH) 2.5s (57fH) 6.0s (134fH) EVEN FIELD 0.5s (11fH)
SH1 (Internal pulse) SH2 (Internal pulse) SH4 (Internal pulse) SH3 (Internal pulse) FRP (Internal pulse) 158fH
ODD FIELD
VCK1 2.2s (51fH)
102fH
VCK2
VST/VD
PCG
EN
EN (PAL)
PSIGFRP (Internal pulse)
ODD FIELD
EVEN LINE
CXA2543R
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field.
DCX501BK Vertical Direction Output Pulse NTSC Vertical Direction Timing Chart
XVD
XHD
CSYNC
(BLK)
VST
VCK1
VCK2
FRP (Internal pulse)
- 57 -
ODD FIELD
HST
EN
PCG
VD
FRP (Internal pulse) (1F inversion)
FLD (Internal pulse)
SBLK (Internal pulse)
CXA2543R
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field.
DCX501BK Vertical Direction Output Pulse NTSC Vertical Direction Timing Chart
XVD
XHD
CSYNC
(BLK)
VST
VCK1
VCK2
FRP (Internal pulse)
- 58 -
EVEN FIELD
HST
EN
PCG
VD
FRP (Internal pulse)
(1F inversion)
FLD (Internal pulse)
SBLK (Internal pulse)
CXA2543R
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field.
DCX501BK Vertical Direction Output Pulse PAL Vertical Direction Timing Chart
XVD
XHD
CSYNC
(BLK)
VST
VCK1
VCK2
FRP (Internal pulse)
- 59 -
ODD FIELD
HST
EN
PCG
VD
FRP (Internal pulse)
(1F inversion)
FLD (Internal pulse)
SBLK (Internal pulse)
CXA2543R
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field.
DCX501BK Vertical Direction Output Pulse PAL Vertical Direction Timing Chart
XVD
XHD
CSYNC
(BLK)
VST
VCK1
VCK2
FRP (Internal pulse)
- 60 -
EVEN FIELD
HST
EN
PCG
VD
FRP (Internal pulse) (1F inversion)
FLD (Internal pulse)
SBLK (Internal pulse)
CXA2543R
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field.
DCX501BK Vertical Direction Output Pulse NTSC WIDE Vertical Direction Timing Chart
1/4 pulse eliminator
169-line display area
169-line display area
XVD
XHD
CSYNC
(BLK)
VST
VCK1
VCK2
FRP (Internal pulse)
- 61 -
ODD FIELD
HST
EN
PCG
VD
FRP (Internal pulse)
(1F inversion)
FLD (Internal pulse)
SBLK (Internal pulse)
CXA2543R
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field.
DCX501BK Vertical Direction Output Pulse NTSC WIDE Vertical Direction Timing Chart
1/4 pulse eliminator
169-line display area
169-line display area
XVD
XHD
CSYNC
(BLK)
VST
VCK1
VCK2
FRP (Internal pulse)
- 62 -
EVEN FIELD
HST
EN
PCG
VD
FRP (Internal pulse)
(1F inversion)
FLD (Internal pulse)
SBLK (Internal pulse)
CXA2543R
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field.
DCX501BK Vertical Direction Output Pulse PAL WIDE Vertical Direction Timing Chart
1/2 and 1/4 pulse eliminator
169-line display area
XVD
XHD
CSYNC
(BLK)
VST
VCK1
VCK2
FRP (Internal pulse)
- 63 -
ODD FIELD
HST
EN
PCG
VD
FRP (1F inversion) (Internal pulse)
FLD (Internal pulse)
SBLK (Internal pulse)
CXA2543R
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field.
DCX501BK Vertical Direction Output Pulse PAL WIDE Vertical Direction Timing Chart
1/2 and 1/4 pulse eliminator
169-line display area
XVD
XHD
CSYNC
(BLK)
VST
VCK1
VCK2
FRP (Internal pulse)
- 64 -
EVEN FIELD
HST
EN
PCG
VD
FRP (1F inversion) (Internal pulse)
FLD (Internal pulse)
SBLK (Internal pulse)
CXA2543R
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field.
LCX018AK Vertical Direction Output Pulse NTSC Vertical Direction Timing Chart (DOWN)
XVD
XHD
CSYNC
(BLK)
VST
VCK1
VCK2
FRP (Internal pulse)
- 65 -
ODD FIELD
HST
EN
PCG
VD
FRP (Internal pulse)
(1F inversion)
FLD (Internal pulse)
SBLK (Internal pulse)
CXA2543R
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field.
LCX018AK Vertical Direction Output Pulse NTSC Vertical Direction Timing Chart (DOWN)
XVD
XHD
CSYNC
(BLK)
VST
VCK1
VCK2
FRP (Internal pulse)
- 66 -
EVEN FIELD
HST
EN
PCG
VD
FRP (Internal pulse)
(1F inversion)
FLD (Internal pulse)
SBLK (Internal pulse)
CXA2543R
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field.
LCX018AK Vertical Direction Output Pulse PAL Vertical Direction Timing Chart (DOWN)
XVD
XHD
CSYNC
(BLK)
VST
VCK1
VCK2
FRP (Internal pulse)
- 67 -
ODD FIELD
HST
EN
PCG
VD
FRP (Internal pulse)
(1F inversion)
FLD (Internal pulse)
SBLK (Internal pulse)
CXA2543R
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field.
LCX018AK Vertical Direction Output Pulse PAL Vertical Direction Timing Chart (DOWN)
XVD
XHD
CSYNC
(BLK)
VST
VCK1
VCK2
FRP (Internal pulse)
- 68 -
EVEN FIELD
HST
EN
PCG
VD
FRP (Internal pulse)
(1F inversion)
FLD (Internal pulse)
SBLK (Internal pulse)
CXA2543R
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field.
LCX018AK Vertical Direction Output Pulse NTSC Vertical Direction Timing Chart (UP)
XVD
XHD
CSYNC
(BLK)
VST
VCK1
VCK2
FRP (Internal pulse)
- 69 -
ODD FIELD
HST
EN
PCG
VD
FRP (Internal pulse)
(1F inversion)
FLD (Internal pulse)
SBLK (Internal pulse)
CXA2543R
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field.
LCX018AK Vertical Direction Output Pulse NTSC Vertical Direction Timing Chart (UP)
XVD
XHD
CSYNC
(BLK)
VST
VCK1
VCK2
FRP (Internal pulse)
- 70 -
EVEN FIELD
HST
EN
PCG
VD
FRP (Internal pulse)
(1F inversion)
FLD (Internal pulse)
SBLK (Internal pulse)
CXA2543R
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field.
LCX018AK Vertical Direction Output Pulse PAL Vertical Direction Timing Chart (UP)
XVD
XHD
CSYNC
(BLK)
VST
VCK1
VCK2
FRP (Internal pulse)
- 71 -
ODD FIELD
HST
EN
PCG
VD
FRP (Internal pulse)
(1F inversion)
FLD (Internal pulse)
SBLK (Internal pulse)
CXA2543R
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field.
LCX018AK Vertical Direction Output Pulse PAL Vertical Direction Timing Chart (UP)
XVD
XHD
CSYNC
(BLK)
VST
VCK1
VCK2
FRP (Internal pulse)
- 72 -
EVEN FIELD
HST
EN
PCG
VD
FRP (Internal pulse)
(1F inversion)
FLD (Internal pulse)
SBLK (Internal pulse)
CXA2543R
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field.
CXA2543R
Application Circuit (NTSC/PAL, COMP and Y/C input)
To LCD panel +12V 0.1 47 0.47 0.47 0.47 0.47
Buff
+3V
+12V
3.3k
To Serial controller
IN
OUT
3.3k 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
B OUT
PSIG
R OUT
GND2
GND3
FB PSIG
G OUT
+4.5V 49 VCC1 0.1 47 0.01
LOAD
DATA
SCLK
FB G
VCC2
FB B
FB R
VCC3
RGT
Sample PSIG buffer circuit VD 32 VSS2 31 EN 30 XEN 29 VCK1 28 VCK2 27 VST 26 XVST 25 FLD IN 24 To LCD panel HD 23 PCG 22 XPCG 21 HCK1 20 HCK2 19 HST 18
50 SIG.CENTER 0.01 51 B-Y IN 0.01 +4.5V 47k 0.01 52 R-Y IN 53 C OUT
54 BLK LIM 55 APC
0.22
15k 0.068
1 56 VXO OUT 2 57 VXO IN 1 58 V REG
C IN
Y/C COMP 1 59 C IN 60 TEST3
+4.5V
61 Y IN 62 PIC 0.01 6 15k 63 F0 ADJ
47k
H.FIL OUT
0.01
SYNC IN
S.SEP IN
64 PWRST
XHST 17
TEST1
TEST2
EXT G
EXT R
TRAP
EXT B
GND1
VD IN
VSS1
CKI
VDD1
RPD
CKO
1
2
3
4
5
6 750
7
8
9
10
11 1k
12
13
14 L
15 4 C
16
+3V
COMP/Y IN
220p 0.033 0.47 10k 5 3.3
47
0.1
6800p
33k 3 10k 0.01 12V 47k
1 Used crystal: KINSEKI CX-5F Frequency deviation: within 30ppm, frequency temperature characteristics: within 30ppm, load capacity: 16pF NTSC: 3.579545Hz PAL: 4.433619Hz 2 NTSC: shorted, PAL: 18pF 3 Variable Capcitance Diode: 1T369 (SONY)
4 DCX501 mode: L value: 4.7H, C value: 22pF LCX018 (4:3) mode: L value: 4.7H, C value: 22pF LCX018 (16:9) mode: L value: 2.2H, C value: 33pF 5 Trap (TDK) NTSC: NLT4532-S3R6B PAL: NLT4532-S4R4 6 Resistance value variation: 2%, temperature coefficient: 200ppm or less Connect to +4.5V during Y/C input
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 73 -
CXA2543R
Application Circuit (NTSC/PAL, Y/color difference input)
To LCD panel +12V 0.1 47 0.47 0.47 0.47 0.47
Buff
+3V
+12V
3.3k
To Serial controller
IN
OUT
3.3k 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
G OUT
B OUT
PSIG
FB R
VCC3
R OUT
GND2
GND3
FB PSIG
+4.5V 49 VCC1 0.1 47 0.01
LOAD
DATA
SCLK
FB G
VCC2
FB B
RGT
Sample PSIG buffer circuit VD 32 VSS2 31 EN 30 XEN 29 VCK1 28 VCK2 27 VST 26 XVST 25 FLD IN 24 To LCD panel HD 23 PCG 22 XPCG 21 HCK1 20 HCK2 19 HST 18
50 SIG.CENTER 0.1 B-Y IN 0.1 R-Y IN +4.5V 47k 0.01 55 APC 56 VXO OUT 57 VXO IN 1 58 V REG 59 C IN 60 TEST3 1 +4.5V 61 Y IN 62 PIC 0.01 +4.5V 63 F0 ADJ 52 R-Y IN 53 C OUT 54 BLK LIM 51 B-Y IN
47k
H.FIL OUT
0.01
SYNC IN
S.SEP IN
64 PWRST
XHST 17
TEST1
TEST2
EXT G
EXT R
TRAP
EXT B
GND1
VD IN
VSS1
CKI
VDD1
RPD
CKO
1
2
3
4
5 750
6
7
8
9
10
11 1k
12
13
14 L
15 2 C
16
+3V
COMP/Y IN
220p 0.033 0.47
47
0.1
6800p
10k 3.3
33k 1 10k 0.01 +12V 47k
1 Variable Capcitance Diode: 1T369 (SONY) 2 DCX501 mode: L value: 4.7H, C value: 22pF LCX018 (4:3) mode: L value: 4.7H, C value: 22pF LCX018 (16:9) mode: L value: 2.2H, C value: 33pF
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 74 -
CXA2543R
Example of Representative Characteristics
HUE adjustment characteristics
60 40 20 0 -20 -40 -25 -60 0 20 40 60 80 0A0 0C0 0E0 0FF NT PAL DAC value -30 0 20 40 60 80 0A0 0C0 0E0 0FF DAC value 10 5 0
COLOR adjustment characteristics
HUE adjustment angle [deg]
Gain [dB]
-5 -10 -15 -20
BRIGHT adjustment characteristics
6 12 11 10 9 8 7 6 0A0 0C0 0E0 0FF Non-inverted black Inverted black 25
CONTRAST adjustment characteristics
Non-inverted output black level [V]
Output gain [dB]
4 3 2 1 0 0 20 40 60 80
Inverted output black level [V]
5
20 15 10 5 0 -5 0 20 40 60 80 0A0 0C0 0E0 0FF DAC value
DAC value
SUB-BRIGHT adjustment characteristics
1.5 10
PSIG-BRIGHT adjustment characteristics
Output level with respect to G output [V]
1.0 0.5 0 -0.5 -1.0 -1.5 0 20 40 60 80 0A0 0C0 0E0 0FF DAC value
8
Output level [Vp-p]
6
4
2
0 0 20 40 60 80 0A0 0C0 0E0 0FF DAC value
- 75 -
CXA2543R
Color difference balance adjustment
5 4 3 2
Color difference COLOR adjustment characteristics
10 5 0
Gain [dB]
1 0 -1 -2 -3 -4 -5 0 20 40 60 80 0A0 0C0 0E0 0FF B-Y output DAC value R-Y output
Gain [dB]
-5 -10 -15 -20 0 20 40 60 80 0A0 0C0 0E0 0FF DAC value
Sharpness characteristics (COMP, NTSC)
15 10 5 0 -5 15 10 5 0
Sharpness characteristics (COMP, PAL)
Gain [dB]
0 1 2 3 4 5 0V 2.25V 4.5V
Gain [dB]
-5 -10 -15 -20 -25 -30 0 1 2 3 4 5 0V 2.25V 4.5V Frequency [MHz]
-10 -15 -20 -25 -30 Frequency [MHz]
Sharpness characteristics (Y/C)
20 15 10 5 0
Black level limiter adjustment characteristics
10 9
Limiter level [Vp-p]
0 2 4 6 8 10 0V 2.25V 4.5V
8 7 6 5 4 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Pin voltage [V]
Gain [dB]
-5 -10 -15 -20 -25 Frequency [MHz]
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CXA2543R
Notes on Operation The CXA2543R contains digital circuits, so the set board pattern must be designed in consideration of undesired radiation, interference to analog circuits, etc. Care should also be taken for the following items when designing the pattern. * Make the IC power supply and GND patterns as plain as possible. In particular, GND and VSS should not be separated and should be connected to the same GND pattern as close to the pins as possible. * Connect the by-pass capacitors between the power supplies and GND as close to the pins as possible. * The trap connected to Pin 1 should be located as close to the pin as possible. Also, don't pass other signal lines close to this pin or the connected trap. * The wiring for the crystal and capacitor connected to Pins 56 and 57 should be as short as possible in order to prevent floating capacitance. Don't pass other signal lines close to these pins in order to prevent interference such as color unevenness. In addition, the APC pull-in characteristics vary significantly according to the characteristics of the used crystal and the wiring pattern, so be sure to thoroughly investigate these items before using the set. * The resistor connected to Pin 63 should be located as close to the pin as possible. Also, take care not to pass other signal lines close to this pin. The composite/Y signal and the external R-Y and B-Y signals are clamped at the inputs using the capacitors connected to the input pins, so these signals should be input at sufficiently low impedance. The C signal is received by the internal capacitor, so this signal should be directly input at low impedance. The smoothing capacitor of the DC level control feedback circuit in the output block should have a leak current with a small absolute value and variance. A thorough study of the external buffer for PSIG output should be made before deciding on a circuit to ascertain that it sufficiently brings out the characteristics of the LCD panel. If this IC is used in connection with a circuit other than an LCD, it may cause that circuit to malfunction depending on the order power is supplied to the circuits. Thoroughly study the consequences of using this IC with other circuits before deciding on its use. Since this IC utilizes a C-MOS structure, it may latch up due to excessive noise or power surge greater than the maximum rating of the I/O pins, or due to interface with the power supply of another circuit, or due to the order in which power is supplied to circuits. Be sure to take measures against the possibility of latch up. Do not apply a voltage higher than VDD or lower than VSS to I/O pins. Do not use this IC under operating conditions other than those given. Absolute maximum rating values should not be exceeded even momentarily. Exceeding ratings may damage the device, leading to eventual breakdown. This IC has a MOS structure which is easily damaged by static electricity, so thorough measures should be taken to prevent electrostatic discharge. - 77 -
CXA2543R
Package Outline
Unit: mm
64PIN LQFP (PLASTIC)
12.0 0.2 10.0 0.2 48 49 33 32 0.15 0.05 0.1
A 64 17
1 1.25 0.5
+ 0.08 0.18 - 0.03
16
1.7 MAX 0.1 M
0.1 0.1
0 to 10
DETAIL A
0.5 0.2
(0.5)
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING 42 ALLOY 0.3g LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT
SONY CODE EIAJ CODE JEDEC CODE
LQFP-64P-L061 LQFP064-P-1010-AY
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