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FEATURES CMOS 10-Bit 20 MSPS Sampling A/D Converter Pin-Compatible 8-Bit Option Power Dissipation: 160 mW +5 V Single Supply Operation Differential Nonlinearity: 0.5 LSB Guaranteed No Missing Codes Power Down (Standby) Mode Three-State Outputs Digital I/Os Compatible with +5 V or +3.3 V Logic Adjustable Reference Input Small Size: 28-Lead SOIC, 28-Lead SSOP, or 48-Lead Thin Quad Flatpack (TQFP)
CLK SHA AIN REFTF REFTS
A/D
10-Bit 20 MSPS 160 mW CMOS A/D Converter AD876
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD DRVDD
SHA
GAIN
SHA
GAIN
SHA
GAIN
A/D
STBY
D/A
A/D
D/A
A/D
D/A
THREESTATE
CORRECTION LOGIC REFBS REFBF
AD876
OUTPUT BUFFERS
(MSB) D9 D0 (LSB)
CML
AVSS
DVSS
DRVSS
PRODUCT DESCRIPTION
The AD876 is a CMOS, 160 mW, 10-bit, 20 MSPS analog-todigital converter (ADC). The AD876 has an on-chip input sample-and-hold amplifier. By implementing a multistage pipelined architecture with output error correction logic, the AD876 offers accurate performance and guarantees no missing codes over the full operating temperature range. Force and sense connections to the reference inputs minimize external voltage drops. The AD876 can be placed into a standby mode of operation reducing the power below 50 mW. The AD876's digital I/O interfaces to either +5 V or +3.3 V logic. Digital output pins can be placed in a high impedance state; the format of the output is straight binary coding. The AD876's speed, resolution and single-supply operation ideally suit a variety of applications in video, multimedia, imaging, high speed data acquisition and communications. The AD876's low power and single-supply operation satisfy requirements for high speed portable applications. Its speed and resolution ideally suit charge coupled device (CCD) input systems such as color scanners, digital copiers, electronic still cameras and camcorders.
The AD876 comes in a space saving 28-lead SOIC and 48-lead thin quad flatpack (TQFP) and is specified over the commercial (0C to +70C) temperature range.
PRODUCT HIGHLIGHTS Low Power
The AD876 at 160 mW consumes a fraction of the power of presently available 8- or 10-bit, video speed converters. Powerdown mode and single-supply operation further enhance its desirability in low power, battery operated applications such as electronic still cameras, camcorders and communication systems.
Very Small Package
The AD876 comes in a 28-lead SOIC, 28-lead SSOP, and 48lead surface mount, thin quad flat package. The TQFP package is ideal for very tight, low headroom designs.
Digital I/O Functionality
The AD876 offers three-state output control.
Pin Compatible Upgrade Path
The AD876 offers the option of laying out designs for eight bits and migrating to 10-bit resolution if prototype results warrant.
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1998
AD876-SPECIFICATIONS +2.0 V, f
Parameter RESOLUTION DC ACCURACY Integral Nonlinearity (INL) Differential Nonlinearity (DNL) No Missing Codes Offset Error Gain Error ANALOG INPUT Input Range Input Capacitance REFERENCE INPUT Reference Top Voltage Reference Bottom Voltage Reference Input Resistance Reference Input Current Reference Top Offset Reference Bottom Offset DYNAMIC PERFORMANCE Effective Number of Bits fIN = 1 MHz fIN = 3.58 MHz fIN = 10 MHz Signal-to-Noise and Distortion (S/N+D) Ratio fIN = 1 MHz fIN = 3.58 MHz fIN = 10 MHz Total Harmonic Distortion (THD) fIN =1 MHz fIN = 3.58 MHz fIN =10 MHz Spurious Free Dynamic Range2 Full Power Bandwidth Differential Phase Differential Gain POWER SUPPLIES Operating Voltage AVDD 1 DVDD1 DRVDD Operating Current IAVDD IDVDD IDRVDD POWER CONSUMPTION TEMPERATURE RANGE Specified 0 3.5 1.6
(TMIN to T MAX with AVDD = +5.0 V, DVDD = +5.0 V, DRVDD = +3.3 V, VREFB = +4.0 V, VREFB = CLOCK = 20 MSPS, unless otherwise noted)
AD876JR-8 Typ Max 8 0.3 1.0 0.1 0.75 GUARANTEED 0.1 0.1 2 5.0 4.0 2.0 250 8.0 35 35 4.5 2.5 3.5 1.6 AD876 Typ 10 1.0 0.5 1 GUARANTEED 0.4 0.2 2 5.0 4.0 2.0 250 8.0 35 35 4.5 2.5
Min
Min
Max
Units Bits LSB LSB % FSR % FSR V p-p pF V V mA mV mV
7.4
7.8 7.8 7.5 49 49 47 -62 -62 -60 -65 150 0.5 1
8.2
9.0 9.0 8.2 56 56 51 -62 -62 -60 -65 150 0.5 1
Bits Bits Bits dB dB dB dB dB dB dB MHz Degree %
46
51
-56
-56
+4.5 +4.5 +3.0 20 12 0.1 160
+5.25 +5.25 +5.25 25 16 1 190 +70
+4.5 +4.5 +3.0 20 12 0.1 160 0
+5.25 +5.25 +5.25 25 16 1 190 +70
Volts Volts Volts mA mA mA mW C
NOTES 1 AVDD and DV DD must be within 0.5 V of each other to maintain specified performance levels. 2 3.58 MHz Input Frequency. Specifications subject to change without notice. See Definition of Specifications for additional information.
-2-
REV. B
AD876 DIGITAL SPECIFICATIONS f
Parameter LOGIC INPUT High Level Input Voltage
(TMIN to TMAX with AV DD = +5.0 V, DV DD = +5.0 V, DRVDD = +3.3 V, V REFT = +4.0 V, VREFB = +2.0 V, CLOCK = 20 MSPS, CL = 20 pF unless otherwise noted)
Symbol VIH VIL IIH IIL IIL CIN VOH 3.0 5.0 5.0 VOL 3.6 5.25 5.25 COUT IOZ 5 -10 10 0.7 1.05 0.4 V V V pF A 2.4 3.8 2.4 V V V DRVDD 3.0 5.0 5.25 3.0 5.0 5.25 5.0 5.0 5.0 Min 2.4 4.0 4.2 0.6 1.0 1.05 +10 +50 +10 5 AD876 Typ Max Units V V V V V V A A A pF
Low Level Input Voltage
High Level Input Current Low Level Input Current Low Level Input Current (CLK Only) Input Capacitance LOGIC OUTPUTS High Level Output Voltage (IOH = 50 A) (IOH = 0.5 mA) Low Level Output Voltage (IOL = 50 A) (IOL = 0.6 mA) Output Capacitance Output Leakage Current
Specifications subject to change without notice.
-10 -50 -10
TIMING SPECIFICATIONS
Symbol Maximum Conversion Rate1 Clock Period Clock High Clock Low Output Delay Pipeline Delay (Latency) Aperture Delay Time Aperture Jitter tC tCH tCL tOD Min 20 23 23 10 50 25 25 20 3.5 4 22 Typ Max Units MHz ns ns ns ns Clock Cycles ns ps
NOTE 1 Conversion rate is operational down to 10 kHz without degradation in specified performance.
SAMPLE N AIN
SAMPLE N+1
SAMPLE N+2
t CH
t CL
CLK
tC
OUT DATA N-4 DATA N-3 DATA N-2 DATA N-1
t OD
DATA N
Figure 1. Timing Diagram
REV. B
-3-
AD876
PIN FUNCTION DESCRIPTIONS
Symbol D0 (LSB) D1-D4 D5-D8 D9 (MSB) THREESTATE STBY CLK CML REFTF REFBF REFTS REFBS AIN AVDD AVSS DVDD DVSS DRVDD DRVSS
SOIC Pin No. 3 4-7 8-11 12 16
TQFP Pin No. 1 2-5 8-11 12 23
Type DO DO DO DI
Name and Function Least Significant Bit. Data Bits 1 through 4. Data Bits 5 through 8. Most Significant Bit. THREE-STATE = LOW THREE-STATE = HIGH or N/C Normal Operating Mode High Impedance Outputs STBY = LOW or N/C STBY = HIGH Normal Operating Mode Standby Mode Clock Input. Bypass Pin for an Internal Bias Point. Reference Top Force. Reference Bottom Force. Reference Top Sense. Reference Bottom Sense. Analog Input. +5 V Analog Supply. Analog Ground. +5 V Digital Supply. Digital Ground. +3.3 V/+5 V Digital Supply. Supply for digital input and output buffers. +3.3 V/+5 V Digital Ground. Ground for digital input and output buffers.
17 15 26 22 24 21 25 27 28 1 18 14, 19, 20 2 13
24 22 38 30 34 29 35 39 42 44 26 17, 27, 28 45 16
DI DI AO AI AI AI AI AI P P P P P P
Type: AI = Analog Input; AO = Analog Output; DI = Digital Input; DO = Digital Output; P = Power.
PIN CONFIGURATIONS SOIC/SSOP
DRVDD AVSS
TQFP
AVDD CML AIN
AVSS DRVDD
1 2 3 4 5 6 7 8 9
28 AVDD 27 AIN 26 CML 25 REFBS 24 REFBF D0 1 D1 2 D2 3 D3 4 D4 5 6 7 D5 8 D6 9 D7 10 D8 11 D9 12
48 47 46 45 44 43 42
41 40 39 38 37 36 35 REFBS 34 REFBF 33 32
*D0 *D1
D2 D3 D4 D5 D6
AD876
TOP VIEW (Not to Scale)
23 NC 22 REFTF 21 REFTS 20 DVSS 19 DVSS 18 DVDD 17 STBY 16 THREE-STATE 15 CLK
AD876
TOP VIEW (Not to Scale)
31 30 REFTF 29 REFTS 28 DV SS 27 DV SS 26 DV DD 25
D7 10 D8 11 D9 12 DRVSS 13 DVSS 14
* PINS D0 AND D1 ARE LEFT OPEN
FOR THE AD876JR-8 NC = NO CONNECT
13 14 15 16 17 18 19 20 21 22 23 24 THREE-STATE DRVSS DVSS STBY CLK
-4-
REV. B
AD876
ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE
Parameter AVDD DVDD, DRVDD AVSS AIN REFTS, REFTF REFBS, REFBF Digital Inputs, CLK Junction Temperature Storage Temperature Lead Temperature (10 sec)
With Respect to Min AVSS DVSS, DRVSS DVSS, DRVSS AVSS AVSS DVSS, DRVSS -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -65
Max Units +6.5 +6.5 +0.5 +6.5 +6.5 +6.5 +150 +150 Volts Volts Volts Volts Volts Volts C C
Model
Temperature Range
Package Description
Package Options R-28 ST-48 R-28 R-28 RS-28 RS-28 RS-28
AD876JR 0C to +70C AD876JST-Reel 0C to +70C AD876JR-8 AD876AR AD876ARS AD876JRS AD876JRS-8
28-Lead SOIC 48-Lead TQFP (Tape and Reel 13") 0C to +70C 28-Lead SOIC -40C to +85C 28-Lead SOIC -40C to +85C 28-Lead SSOP 0C to +70C 28-Lead SSOP 0C to +70C 28-Lead SSOP
+300 C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability.
DVDD DRVDD DVDD DVDD DRVDD DRVDD
DVSS DVSS DVSS DRVSS DVSS DRVSS
DRVSS
a) D0-D9
b) Three-State, Standby
AVDD
c) CLK
REFTF
AVDD AVDD AVSS INTERNAL REFERENCE VOLTAGE AVSS AVSS AVDD
REFTS
d) AIN
REFBS
AVDD AVSS
INTERNAL REFERENCE VOLTAGE
REFBF
AVSS
Figure 2. Equivalent Circuits
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD876 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
-5-
AD876-Typical Performance Characteristics
1 0 -10 0.5 -20 -30 DNL - LSBs -40 0 dB -50 -60 -0.5 -70 3RD -80 -1
0 64 128 192 256 320 384 448 512 576 640 704 768 832 896 960
THD 2ND
-90 1 FREQUENCY - MHz 10
CODE OFFSET
Figure 3. AD876 Typical DNL
Figure 6. THD vs. Input Frequency 2nd, 3rd Harmonics
2
60
0
55
-2 GAIN - dB
50
dB 1 10 100 FREQUENCY - MHz 1000
-4
45
-6
40
-8
35
-10
30
5
10
15 20 CLOCK FREQUENCY - MHz
25
30
Figure 4. Full Power Bandwidth
Figure 7. SINAD vs. CLK Frequency (AIN = -0.5 dB)
60
180 170
55 160 50 150 mW 140 130 40 120 35 110 100 101 INPUT FREQUENCY - MHz 102
dB
45
30 100
0
5
10 15 CLOCK FREQUENCY - MHz
20
25
Figure 5. SINAD vs. Input Frequency (fCLK = 20 MSPS, AIN = -0.5 dB)
Figure 8. Power Consumption vs. Sample Rate
-6-
REV. B
AD876
1 HARMONICS (dBc) -68.02 6TH -77.74 -72.85 7TH -75.62 -70.68 8TH -75.98 -78.09 9TH -81.20 THD = -64.12 SNR = 48.73 SINAD = 48.61 SFDR = -68.02
PIPELINE DELAY (LATENCY)
2ND 3RD 4TH 5TH
The number of clock cycles between conversion initiation and the associated output data being made available. New output data is provided every clock cycle.
REFERENCE TOP/BOTTOM OFFSET
3
2 6 9 8 5
4 7
Resistance between the reference input and comparator input tap points causes offset errors. These errors can be nulled out by using the force-sense connection as shown in the Reference Input section.
THEORY OF OPERATION
The AD876 implements a pipelined multistage architecture to achieve high sample rate with low power. The AD876 distributes the conversion over several smaller A/D subblocks, refining the conversion with progressively higher accuracy as it passes the results from stage to stage. As a consequence of the distributed conversion, the AD876 requires a small fraction of the 1023 comparators used in a traditional flash type A/D. A sample-andhold function within each of the stages permits the first stage to operate on a new input sample while the second and third stages operate on the two preceding samples.
Figure 9. AD876JR-8 Typical FFT (fIN = 3.58 MHz, AIN = -0.5 dB, fCLOCK = 20 MSPS)
1 HARMONICS (dBc) -68.91 6TH -80.55 -73.92 7TH -82.02 -68.67 8TH -81.02 -73.26 9TH -88.94 THD = -64.24 SNR = 55.71 SINAD = 55.14 SFDR = -68.67 5 6 8 9 2 4 7
2ND 3RD 4TH 5TH
APPLYING THE AD876
DRIVING THE ANALOG INPUT
3
Figure 10. AD876 Typical FFT (fIN = 3.58 MHz, AIN = -0.5 dB, fCLOCK = 20 MSPS)
DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITY (INL)
Integral nonlinearity refers to the deviation of each individual code from a line drawn from "zero" through "full scale". The point used as "zero" occurs 1/2 LSB before the first code transition. "Full scale" is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to the true straight line.
DIFFERENTIAL NONLINEARITY (DNL, NO MISSING CODES)
Figure 11 shows the equivalent analog input of the AD876, a sample-and-hold amplifier (SHA). Bringing CLK to a logic low level closes Switches 1 and 2 and opens Switch 3. The input source connected to AIN must charge capacitor CH during this time. When CLK transitions from logic "low" to logic "high," Switch 1 opens first, placing the SHA in hold mode. Switch 2 opens subsequently. Switch 3 then closes, connects the feedback loop around the op amp, and forces the output of the op amp to equal the voltage stored on CH. When CLK transitions from logic "high" to logic "low", Switch 3 opens first. Switch 2 closes and reconnects the input to CH. Finally, Switch 1 closes and places the SHA in track mode. The structure of the input SHA places certain requirements on the input drive source. The combination of the pin capacitance, CP, and the hold capacitance, CH, is typically less than 5 pF. The input source must be able to charge or discharge this capacitance to 10-bit accuracy in one half of a clock cycle. When the SHA goes into track mode, the input source must charge or discharge capacitor CH from the voltage already stored on CH (the previously captured sample) to the new voltage. In the worst case, a full-scale voltage step on the input, the input source must provide the charging current through the RON (50 ) of Switch 2 and quickly settle (within 1/2 CLK period). This situation corresponds to driving a low input impedance. On the other hand, when the source voltage equals the value previously stored on CH , the hold capacitor requires no input current and the equivalent input impedance is extremely high. Adding series resistance between the output of the source and the AIN pin reduces the drive requirements placed on the source. Figure 12 shows this configuration. The bandwidth of the particular application limits the size of this resistor. To maintain the performance outlined in the data sheet specifications, the resistor should be limited to 200 or less. For applications with signal bandwidths less than 10 MHz, the user may increase the size of the series resistor proportionally. Alternatively, adding a shunt capacitance between the AIN pin and -7-
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. It is often specified in terms of the resolution for which no missing codes (NMC) are guaranteed.
OFFSET ERROR
The first transition should occur at a level 1/2 LSB above "zero." Offset is defined as the deviation of the actual first code transition from that point.
GAIN ERROR
The first code transition should occur for an analog value 1/2 LSB above nominal negative full scale. The last transition should occur for an analog value 1 1/2 LSB below the nominal positive full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between the first and last code transitions. REV. B
AD876
analog ground can lower the ac source impedance. The value of this capacitance will depend on the source resistance and the required signal bandwidth. The input span of the AD876 is a function of the reference voltages. For more information regarding the input range, see the DRIVING THE REFERENCE TERMINALS section of the data sheet.
AD876
3
20 kHz. At a sample clock frequency of 20 MHz, the dc bias current at 3 V dc is approximately 30 A. If we choose R2 equal to 1 k and R1 equal to 50 , the parallel capacitance should be a minimum of 0.008 F to avoid attenuating signals close to 20 kHz. Note that the bias current will cause a 31.5 mV offset from the 3 V bias. In systems that must use dc-coupling, use an op amp to levelshift a ground-referenced signal to comply with the input requirements of the AD876. Figure 14 shows an AD817 configured in inverting mode with ac signal gain of -1. The dc voltage at the noninverting input of the op amp controls the amount of dc level shifting. A resistive voltage divider attenuates the REFBF signal. The op amp then multiplies the attenuated signal by 2. In the case where REFBF = 1.6 V, the dc output level will be 2.6 V. The AD817 is a low cost, fast settling, single supply op amp with a G = -1 bandwidth of 29 MHz. The AD818 is similar to the AD817 but has a 50 MHz bandwidth. Other appropriate op amps include the AD8011, AD812 (a dual), and the AD8001.
Rf = 4.99k +VCC 0.1 F NC 0Vdc 2V p-p RIN = 4.99k 3k REFBF 14.7k NC
1 AIN CP 2 CH
Figure 11. AD876 Equivalent Input Structure
< VS 200 AIN
Figure 12. Simple AD876 Drive Requirements
In many cases, particularly in single-supply operation, accoupling offers a convenient way of biasing the analog input signal at the proper signal range. Figure 13 shows a typical configuration for ac-coupling the analog input signal to the AD876. Maintaining the specifications outlined in the data sheet requires careful selection of the component values. The most important concern is the f -3 dB high-pass corner that is a function of R2, and the parallel combination of C1 and C2. The f -3 dB point can be approximated by the equation
f -3 dB = 1 [2 x x ( R2) Ceq ]
AD876
AD817 OR AD818
AIN
Figure 14. Bipolar Level Shift
where Ceq is the parallel combination of C1 and C2. Note that C1 is typically a large electrolytic or tantalum capacitor that becomes inductive at high frequencies. Adding a small ceramic or polystyrene capacitor on the order of 0.01 F that does not become inductive until negligibly higher frequencies maintains a low impedance over a wide frequency range.
AD876
AIN R2 C2 3V VBIAS IB
An integrated difference amplifier such as the AD830 is an alternate means of providing dc level shifting. The AD830 provides a great deal of flexibility with control over offset and gain. Figure 15 shows the AD830 precisely level-shifting a unipolar, ground-referenced signal. The reference voltage, REFBS, determines the amount of level-shifting. The ac gain is 1. The AD830 offers the advantages of high CMRR, precise gain, offset, and high-impedance inputs when compared with a discrete implementation. For more information regarding the AD830, see the AD830 data sheet.
+12V 0.1 2V 0 VB AD830 VB 0.1 VB +2V
C1 VIN
R1
AD876
AIN
Figure 13. AC-Coupled Inputs
-12V REFBS
There are additional considerations when choosing the resistor values. The ac-coupling capacitors integrate the switching transients present at the input of the AD876 and cause a net dc bias current, IB, to flow into the input. The magnitude of this bias current increases with increasing dc signal level and also increases with sample frequency. This bias current will result in an offset error of (R1 + R2) x IB. If it is necessary to compensate this error, consider making R2 negligibly small or modifying VBIAS to account for the resultant offset. As an example, assume that the input to the AD876 must have a dc bias of 3 V and the minimum expected signal frequency is
Figure 15. Level Shifting with the AD830
REFERENCE INPUT DRIVING THE REFERENCE TERMINALS
The AD876 requires an external reference on pins REFTF and REFBF. The AD876 provides reference sense pins, REFTS and REFBS, to minimize voltage drops caused by external and internal wiring resistance. A resistor ladder, nominally 250 , connects pins REFTF and REFBF. -8- REV. B
AD876
Figure 16 shows the equivalent input structure for the AD876 reference pins. There is approximately 5 of resistance between both the REFTF and REFBT pins and the reference ladder. If the force-sense connections are not used, the voltage drop across the 5 resistors will result in a reduced voltage appearing across the ladder resistance. This reduces the input span of the converter. Applying a slightly larger span between the REFTF and REFBF pins compensates this error. Note that the temperature coefficients of the 5 resistors are 1350 ppm. The user should consider the effects of temperature when not using a force-sense reference configuration.
5
ance changes associated with the reference inputs. The simplified diagram of Figure 16 shows that the reference pins connect to a capacitor for one-half of the clock period. The size of the capacitor is a function of the analog input voltage. The external reference must be able to maintain a low impedance over all frequencies of interest in order to provide the charge required by the capacitance. By supplying the requisite charge, the reference voltages will be relatively constant and performance will not degrade. For some reference configurations, voltage transients will be present on the reference lines; this is particularly true during the falling edge of CLK. It is important that the reference recovers from the transients and settles to the desired level of accuracy prior to the rising edges of CLK. There are several reference configurations suitable for the AD876 depending on the application, desired level of accuracy, and cost trade-offs. The simplest configuration, shown in Figure 18, utilizes a resistor string to generate the reference voltages from the converter's analog power supply. The 0.1 F bypass capacitors effectively reduce high-frequency transients. The 10 F capacitors act to reduce the impedances at the REFTF and REFBF pins at lower frequencies. As input frequencies approach dc, the capacitors become ineffective, and small voltage deviations will appear across the biasing resistors. This application can maintain 10-bit accuracy for input frequencies above approximately 200 Hz. 8-bit applications can use this circuit for input frequencies above approximately 50 Hz.
AD876
NC 140 +5V 10 F 10 F 250 ( 1%) 10 F 2V REFBF 0.1 F ( 1%) REFTS
REFTF REFTS
AD876
V1 DACS CLK C (VIN) CLK
RLADDER 250 V2
REFBS REFBF 5
Figure 16. AD876 Equivalent Reference Structure
Do not connect the REFTS and REFBS pins in configurations that do not use a force-sense reference. Connecting the force and sense lines together allows current to flow in the sense lines. Any current allowed to flow through these lines must be negligibly small. Current flow causes voltage drops across the resistance in the sense lines. Because the internal D/As of the AD876 tap different points along the sense lines, each D/A would receive a slightly different reference voltage if current were flowing in these wires. To avoid this undesirable condition, leave the sense lines unconnected. Any current allowed to flow through these lines must be negligibly small (<100 A). The voltage drop across the internal resistor ladder determines the input span of the AD876. The driving voltages required at the V1 and V2 points are respectively +4 V and +2 V. Calculate the full-scale input span from the equation
Input Span (V ) = REFTS - REFBS
4V 0.1 F
REFTF 250 ( 15%)
NC NC = NO CONNECT
REFBS
This results in a full-scale input span of approximately +2 V when REFTS = +4 V and REFBS = +2 V In order to maintain the requisite 2 V drop across the internal ladder, the external reference must be capable of providing approximately 8.0 mA. The user has flexibility in determining both the full-scale span of the analog input and where to center this voltage. Figure 17 shows the range over which the AD876 can operate without degrading the typical performance.
(1.6, 4.5) 4.5 REFTF, REFTS 4.0 3.5 (1.6, 3.5) 3.0 2.5 1.0 1.5 2.0 2.5 REFBF, REFBS 3.0 (2.5, 3.5) (2.5, 4.5)
Figure 18. Low Cost Reference Circuit
This reference configuration provides the lowest cost but has several disadvantages. These disadvantages include poor dc power supply rejection and poor accuracy due to the variability of the internal and external resistors. The AD876 offers force-sense reference connections to eliminate the voltage drops associated with the internal connections to the reference ladder. Figure 19 shows a suggested circuit using an AD826 dual, high speed op amp. This configuration uses 3.6 V and 1.6 V reference voltages for REFT and REFB, respectively. The connections shown in Figure 19 configure the op amps as voltage followers.
Figure 17. AD876 Reference Ranges
While the previous issues address the dc aspects of the AD876 reference, the user must also be aware of the dynamic impedREV. B -9-
AD876
C3 0.1 F
AD876
REFTS +5V 6 REFT 5 8 7 C2 0.1 F REFBS 2 6 REFB 3 C5 0.1 F REFBF C1 0.1 F C4 0.1 F REFTF
common ground, are effectively removed by the AD876's high common-mode rejection. High frequency noise sources, VN1 and VN2, are shunted to ground by decoupling capacitors. Any voltage drops between the analog input ground and the reference bypassing points will be treated as input signals by the converter via the reference inputs. Consequently, the reference decoupling capacitors should be connected to the same analog ground point used to define the analog input voltage. (For further suggestions, see the "Grounding and Layout Rules" section of the data sheet.)
4V VN1 REFTF
1/2 AD826
1/2 AD826
4
Figure 19. Kelvin Connected Reference Using the AD826
AD876
REFBF 2V VN2 AIN
By connecting the op amp feedback through the sense connections of the AD876, the outputs of the op amps automatically adjust to compensate for the voltage drops that occur within the converter. The AD826 has the advantage of being able to maintain stability while driving unlimited capacitive loads. As a result, 0.1 F capacitors C1, C2, and C3 can connect directly to the outputs of the op amps. These decoupling capacitors reduce high frequency transients. Capacitors C4 and C5 shunt across the internal resistors of the force sense connections and prevent instability. This configuration provides excellent performance and a minimal number of components. The circuit also offers the advantage of operating from a single +5 V supply. While alternative op amps may also be suitable, consider the stability of these op amps while driving capacitive loads. The circuit shown in Figure 20 allows a wider selection of op amps when compared with the previous configuration. An
AD876
20k 47nF 22 F 10 REFTF REFT 1/2 OP-295 20k 47nF 10 REFBF REFB 1/2 OP-295 10 F 0.1 F REFBS 10 F 0.1 F REFTS
Figure 21. Recommended Bypassing for the Reference Inputs
CLOCK INPUT
The AD876 clock input is buffered internally with an inverter powered from the DRVDD pin. This feature allows the AD876 to accommodate either +5 V or +3.3 V CMOS logic input signal swings with the input threshold for the CLK pin nominally at DRVDD /2. The AD876's pipelined architecture operates on both rising and falling edges of the input clock. To minimize duty cycle variations the recommended logic family to drive the clock input is high speed or advanced CMOS (HC/HCT, AC/ACT) logic. CMOS logic provides both symmetrical voltage threshold levels and sufficient rise and fall times to support 20 MSPS operation. The AD876 is designed to support a conversion rate of 20 MSPS; running the part at slightly faster clock rates may be possible, although at reduced performance levels. Conversely, some slight performance improvements might be realized by clocking the AD876 at slower clock rates. The power dissipated by the correction logic and output buffers is largely proportional to the clock frequency; running at reduced clock rates provides a reduction in power consumption. Figure 8 illustrates this trade-off.
DIGITAL INPUTS AND OUTPUTS
Figure 20. Kelvin Connected Reference Using the OP295
OP295 dual, single-supply op amp provides stable 3.6 V and 1.6 V reference voltages. The AD822 dual op amp is also suitable for single-supply applications. Each half of the OP295 is compensated to drive the 10 F and 0.1 F decoupling capacitors at the REFTF and REFBF pins and maintain stability. Like any high resolution converter, the layout and decoupling of the reference is critical. The actual voltage digitized by the AD876 is relative to the reference voltages. In Figure 21, for example, the reference return and the bypass capacitors are connected to the shield of the incoming analog signal. Disturbances in the ground of the analog input, that will be commonmode to the REFT, REFB, and AIN pins because of the
Each of the AD876 digital control inputs, THREE-STATE and STBY, has an input buffer powered from the DRVDD supply pins. With DRVDD set to +5 V, all digital inputs readily interface with +5 V CMOS logic. For interfacing with lower voltage CMOS logic, DRVDD can be set to 3.3 V, effectively lowering the nominal input threshold of all digital inputs to 3.3 V/2 = 1.65 V. The format of the digital output is straight binary. Table I shows the output format for the case where REFTS = 4 V and REFBS = 2 V.
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REV. B
AD876
Table I. Output Data Format
Approx. AIN (V) >4 4 3 2 <2 X THREE- DATA STATE D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 1 1 1 1 0 0 Z 1 1 0 0 0 Z 1 1 0 0 0 Z 1 1 0 0 0 Z 1 1 0 0 0 Z 1 1 0 0 0 Z 1 1 0 0 0 Z 1 1 0 0 0 Z 1 1 0 0 0 Z 1 1 0 0 0 Z
For DRVDD = 5 V, the AD876 output signal swing is compatible with both high speed CMOS and TTL logic families. For TTL, the AD876 on-chip, output drivers were designed to support several of the high speed TTL families (F, AS, S). For applications where the clock rate is below 20 MSPS, other TTL families may be appropriate. For interfacing with lower voltage CMOS logic, the AD876 sustains 20 MSPS operation with DRVDD = 3.3 V. In all cases, check your logic family data sheets for compatibility with the AD876 Digital Specification table.
THREE-STATE OUTPUTS
A low power mode feature is provided such that for STBY = HIGH and the clock disabled, the static power of the AD876 will drop below 50 mW.
GROUNDING AND LAYOUT RULES
As is the case for any high performance device, proper grounding and layout techniques are essential in achieving optimal performance. The analog and digital grounds on the AD876 have been separated to optimize the management of return currents in a system. It is recommended that a printed circuit board (PCB) of at least 4 layers employing a ground plane and power planes be used with the AD876. The use of ground and power planes offers distinct advantages: 1. The minimization of the loop area encompassed by a signal and its return path. 2. The minimization of the impedance associated with ground and power paths. 3. The inherent distributed capacitor formed by the power plane, PCB insulation, and ground plane. These characteristics result in both a reduction of electromagnetic interference (EMI) and an overall improvement in performance. It is important to design a layout which prevents noise from coupling onto the input signal. Digital signals should not be run in parallel with the input signal traces and should be routed away from the input circuitry. Separate analog and digital grounds should be joined together directly under the AD876. A solid ground plane under the AD876 is also acceptable if the power and ground return currents are managed carefully. A general rule of thumb for mixed signal layouts dictates that the return currents from digital circuitry should not pass through critical analog circuitry. For further layout suggestions, see the AD876 Evaluation Board data sheet.
DIGITAL OUTPUTS
The digital outputs of the AD876 can be placed in a high impedance state by setting the THREE-STATE pin to HIGH. This feature is provided to facilitate in-circuit testing or evaluation. Note that this function is not intended for enabling/ disabling the ADC outputs from a bus at 20 MSPS. Also, to avoid corruption of the sampled analog signal during conversion (3.5 clock cycles), it is highly recommended that the AD876 outputs be enabled on the bus prior to the first sampling. For the purpose of budgetary timing, the maximum access and float delay times (tDD, tHL shown in Figure 15) for the AD876 are 150 ns.
THREE-STATE
t DD
D0-D9 ACTIVE
t HL
HIGH IMPEDANCE
Figure 22. High-Impedance Output Timing Diagram
Each of the on-chip buffers for the AD876 output bits (D0-D9) is powered from the DRVDD supply pins, separate from AVDD or DVDD. The output drivers are sized to handle a variety of logic families while minimizing the amount of glitch energy generated. In all cases, a fan-out of one is recommended to keep the capacitive load on the output data bits below the specified 20 pF level.
REV. B
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AD876
TP3 1 U4 74F04 +5VD JP4 C50 10 F +5VD JP1 15 16 STBY VP6 3ST VP5 4 3 R1 51 U4 74F04 2 CLK_IN TP1 TP4
J1
+
U1 AD876
DVSS 13 3_STATE DRVSS 12 9 17 STBY DB9 18 DVDD DB8 11 8 19 SUBST 20 NC 21 REFTS 22 REFTF NC 23 REFBF 24 REFBS 25 CML 26 AIN DB7 10 7 DB6 9 6 DB5 8 DB4 7 DB3 DB2 DB1 DB0 6 5 4 5 4 3 2 1 0 0 1 2 3 4 CLK 14
JP2 VP8 C62 0.1 F
REFTS VP3 REFTS REFTF REFBF REFBS VP4 REFBS REFTF VP1 REFBF VP2 C64 0.1 F
5 6 7 8 9
1 19 9 8 7 6 5 4 3 2
U2 74ALS541 G1 G2 Y7 11 A7 Y6 12 A6 Y5 13 A5 Y4 14 A4 Y3 15 A3 Y2 16 A2 Y1 17 A1 Y0 18 A0 U3
P1 P1 D9 R2* D8 R3* D5 D6 D7 D8 D9 D7 R4* D6 R5* D5 R6* D4 R7* D3 R8* D2 R9* D1 R10* P1 P1 P1
1 3 5 7 9
P1 P1 P1 P1
2 4 6 8
P1 10 P1 12 P1 14 P1 16 P1 18 P1 20 P1 22 P1 24 P1 26 P1 28 P1 30 P1 32 P1 34 P1 36 P1 38 P1 40
P1 11 P1 13 P1 15 P1 17 P1 19 P1 21 P1 23 P1 25 P1 27 P1 29 P1 31
27 AVDD 28
DRVDD 3 2 AV
SS
1
1 19 9 8 7 6 5 4 3 2
G1 G2 A7 A6 A5 A4 A3 A2 A1 A0
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
11 12 13 14 15 16 17 18
D0 R11* D0 D1 D2 D3 D4
R12*
P1 33 P1 35 P1 37 P1 39
74ALS541 C56 0.1 F C4 10 F
+
+
C2 10 F +5VA +5VD
+
C49 10 F
R16 1k DC_IN R14 100 EXT_CM 2 JP5 1 AIN J2 C1 0.1 F TP18
R17 1.13k
*R2-R12 = 20
C54 0.1 F
R18 1k
3 INT_CM
TP2
C3 47 F
+
R15 51
Figure 23. AD876 Evaluation Board Schematic
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REV. B
AD876
Figure 24. Silkscreen Layer, Component Side PCXB Layout
Figure 25. Silkscreen Layer, Circuit Side PCB Layout
REV. B
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AD876
Figure 26. Component Side PCB Layout
Figure 27. Circuit Side PCB Layout -14-
REV. B
AD876
Figure 28. Ground Layer PCB Layout
REV. B
Figure 29. Power Layer PCB Layout -15-
AD876
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
R-28 28-Lead Wide Body (SOIC)
C1991a-0-1/98
0.0291 (0.74) x 45 0.0098 (0.25) 8 0 0.0500 (1.27) 0.0157 (0.40) 0.039 (1.00) REF
36 37 25 24
0.7125 (18.10) 0.6969 (17.70)
28 15
1
14
PIN 1
0.1043 (2.65) 0.0926 (2.35)
0.0118 (0.30) 0.0040 (0.10)
0.0500 (1.27) BSC
0.0192 (0.49) 0.0138 (0.35)
SEATING 0.0125 (0.32) PLANE 0.0091 (0.23)
ST-48 28-Lead Plastic Thin Quad Flatpack (TQFP)
0.059 +0.008 -0.004 (1.50 +0.2 -0.1) 0.02 0.008 (0.5 0.2) 0.055 0.002 (1.40 0.05)
0.354 0.008 (9.00 0.2) SQ
SEATING PLANE TOP VIEW
(PINS DOWN)
0.4193 (10.65) 0.3937 (10.00)
0.2992 (7.60) 0.2914 (7.40)
0.276 0.004 (7.0 0.1) SQ
0.004 0.002 (0.1 0.05) (3.5 3.5)
48
13 1 12
0 MIN
0.005 +0.002 -0.0008 (0.127 +0.05 -0.02)
0.02 0.003 (0.50 0.08)
0.007 +0.003 -0.001 (0.18 +0.08 -0.03)
RS-28 28-Lead Shrink Small Outline Package (SSOP)
PRINTED IN U.S.A.
8 0 0.03 (0.762) 0.022 (0.558) 0.407 (10.34) 0.397 (10.08)
28
15
0.311 (7.9) 0.301 (7.64)
1
14
0.078 (1.98) PIN 1 0.068 (1.73)
0.07 (1.79) 0.066 (1.67)
0.008 (0.203) 0.0256 (0.65) 0.002 (0.050) BSC
0.015 (0.38) 0.010 (0.25)
SEATING 0.009 (0.229) PLANE 0.005 (0.127)
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0.212 (5.38) 0.205 (5.21)
REV. B

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